Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"Mounard Le Fougueux" <blinkingCursor@NonEventHorizon.com> wrote in message news:m-idnbXwRNOyRD_YnZ2dnUVZ_tqnnZ2d@adelphia.com... <snip> > my guess is that it decided to use that "unused" IOB for some internal > routing purposes to meet explicit constraints. > > I am now using the FPGA editor (post route) to verify that fact. > > Inthe xilinx 6.3.3 tools, there is an option for unused pins under > Configuration properies, but I belive that only applies to configuration > pins, such as JTAG or M0 -M2 pins only. I didn't watch the thread early on so I reviewed it before posting. You didn't mention the package and associated pin number. It could be that this is a "dual purpose" pin that might have a separate configuration bit in bitgen that controls whether it's a user IO after configuration or continues to be driven. The Done/Busy line was a problem for one engineer on a recent thread where the pin became a user-IO too early. If your bitgen setup somehow changed to allow a dedicated pin to maintain its function, that could be what's causing the problems. If FPGA Editor comes up with an unused I/O, please look at whether the pin is dual-purpose. There were problems many, many years back even with the VREF pins during power-up when VREF wasn't even used on the bank; those problems should be long gone but sometimes other glitches show up to remind us who we are. - John_HArticle: 114251
Hi Manfred, These package markings indicate rev A silicon. Hope this helps, Subroto Datta On Jan 5, 12:09 am, "Manfred Balik" <manfred.ba...@tuwien.ac.at> wrote: > from the Cyclone II errata sheet: > The die revision is identified by the alphanumeric character (Z) before the > fab code (first two alphanumeric characters) in the date code printed on the > top side of the device. > A X?Z ## #### > ^ Die Revision > > my EP2C20F484C8N is labeld with (looks a little bit different :-( ): > K CAA9T0619A > is the die Revision A???? > I need this to know, because I use dual clock FIFOs. (Do I need the > workaround of the "M4K block write operations may fail ..."-error in the > Revision A?) > > Thanks, ManfredArticle: 114252
As Austin answered, DDS = phase accumulator is the nicest solution, provided you have a reasonably fast clock available, (significantly higher than your desired "VCO" output) and you can tolerate the resulting deterministic jitter of one accumulator clock period. Otherwise you have to dive into analog territory, which is far less predictable. Peter Alfke On Jan 8, 9:17 am, John <n...@null.com> wrote: > Is there a way to create a variable clock that behaves like a VCO using the Virtex 4? If not clock, how about variable analog voltage?Article: 114253
Hi there, I have been posting these messages to all relevant groups to get more help on the subject topic. So far I have received very good help and links. Here is the problem statement. I have an FPGA board with Spartan3-1000 on it connected with a SATA controller. The SATA controller can be hooked up with a SATA storate device. There is A/D on the board connected to the FPGA. THis makes my realtime, embedded data acquisition system. I need to store the sampled data on the hard disk and later on read it back for post analysis. For that, I need to implement a FAT file system inside FPGA. Can anyone guide me how to implement this on FPGA? I dont need complex FATs like FAT32/FAT16 etc, I am ok with a simple one like one used in digital cameras where the files are automatically named. I have been exploring microblaze and ucLinux for this but still haven't got a grip on it. Can anyone suggest how to get going with it quickly? Thanks FarhanArticle: 114254
Hello everyone, when i wanted to delete a net in hard macro design, the fpga_editor always crashed. Does anyone know why? thanks Li Peng (Perry) Division of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, P. R. ChinaArticle: 114255
Hi, I'm designing the logic for a project with very slow memory. My question is about the behaviour of the PowerPC data cache in V4FX, when writing to memory. In the PPC block datasheet pg 72 is said, that the PLB DCU cannot pipeline multiple write requests. I imagine the following situation: 1. store-without-allocate is set (no allocation) 2. PPC software writes to memory location A (cache miss) 3. DCU starts PLB write cycle A 4. PLB slave receives data and acks to the master 5. PLB slave initiates (slow) memory access in the background 6. PPC software writes to memory location B (cache miss) 7. DCU starts PLB write cycle B 8. PLB slave is not ready, acks address but can't accept data. 9. PPC software writes to memory location C (cache hit) Does the PPC reach step 9 immediately, although the DCU is being blocked in step 8? If yes, does the PPC immediately finish step 9 (recognizing that wait for DCU is not necessary)? Kind regards, MarcArticle: 114256
On Jan 5, 2:17 pm, "axr0284" <axr0...@yahoo.com> wrote: > It seems that for the spartan3E, you cannot change the delay in the > input block. > Amish > > > > Lars wrote: > > axr0284 wrote: > > > Hi I am currently working on a RGMII interface using the SPARTAN 3E > > > FPGA. > > > > I have 1 clock pin (phy_rx_clk) feeding into a DCM and 2 DCM output > > > clk0 and clk180 being used in my design. > > > There is also an external module which I have no control over that wi= ll > > > be sending DDR data and clock with the data have a minimum setup time > > > of 1.4 ns and minimum hold time of 1.2 ns. > > > > I need to measure the setup time of the data when it reaches the first > > > flip flop of the DDR which is found in the IOB itself. > > > > So I setup the constraint to have 2 ns setup time wrt the input clock > > > called phy_rx_clk > > > Now the timing analyzer tells me that it actually needs a setup time = of > > > 3.9 ns and I am wondering why it needs such a long setup time. > > > > Wouldn't the DCM introduce some delay in the clock line wrt to the da= ta > > > line thus reducing the setup time. > > > > Is there anyway to decrease this setup time to what I need. > > > > ---------------------------------------------------------------------= ------=AD--------------------------- > > > * COMP "rgmii_rx_ctrl" OFFSET =3D IN 2 ns BEFORE COMP "phy_rx_clk" HI= GH > > > | Requested | Actual | Logic | Absolute |Number of Levels > > > | 2.000ns | 3.928ns | 0 | -1.928ns | 2 > > > ---------------------------------------------------------------------= ------=AD--------------------------- > > > > Thanks for any answer. > > > Amish > > > If your timing report states a negative value for hold time (and > > assuming that this is not needed), you can trade (at least some) if > > this time into less setup time. > > > Most likley the tools have inserted some input delay in the IO block to > > assert a negative hold time for your input. This is normally not needed > > when working with DCMs. Check IBUF_DEALY_VALUE and IFD_DELAY_VALUE in > > the constraints guide. A quick check is to open the design in > > FPGA-editor and have a look inside the IO block to see what values have > > been assigned to these parameters. > > > /Lars- Hide quoted text -- Show quoted text - Yes you can! Have a look in the Spartan-3E data sheet, page 11. The delay to the interior of the FPGA can be set to the in 250 ps increments and the delay to the IO-block register in 500 ps increments from 0 to aprox. 5.8 ns. /Lars From news@REMOVE_auto_THIS_flame_TO_REPLY.clara.co.uk Tue Jan 09 09:17:49 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!news.glorb.com!news.cs.univ-paris8.fr!proxad.net!proxad.net!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!iris.uk.clara.net From: "Tom Lucas" <news@REMOVE_auto_THIS_flame_TO_REPLY.clara.co.uk> Newsgroups: comp.arch.fpga Subject: Possibility of 80188 VHDL core Date: Tue, 9 Jan 2007 17:17:49 -0000 Lines: 10 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 1f78606812916e10861372702fc25004555c296a41660460606d7c4b45a3cdc1 NNTP-Posting-Date: Tue, 09 Jan 2007 17:15:45 +0000 Message-Id: <1168362945.66348.0@iris.uk.clara.net> Xref: prodigy.net comp.arch.fpga:125394 X-Received-Date: Tue, 09 Jan 2007 12:20:11 EST (newsdbm02.news.prodigy.net) I currently have several products based around the Intel 80188 microcontroller and it it soon to become obsolete. I believe another company make pick up the production but I thought I'd better have a few safety nets in case they don't. One idea I had was for a (probably VHDL) 80188 core that I could run in some suitable FPGA/CPLD. I've heard of PICs and ARMs being created as IP cores and I wondered if anyone knows of an 80188 one?Article: 114257
What's the best way to delay a signal? I want a certain control signal to appear X nano seconds after the rising edge of the clock. Also, in VHDL, if I set the signal in a process on the rising edge, does the signal get updated at the next rising edge?Article: 114258
by the way, this is on a Virtex 4 and the control signal I want to delay is internal logic.Article: 114259
"Tom Lucas" wrote: >I currently have several products based around the Intel 80188 >microcontroller and it it soon to become obsolete. >.... I've heard of PICs and ARMs being created as IP >cores and I wondered if anyone knows of an 80188 one? Go to http://www.maojet.com.tw, then "Products", (The buttons with Chinese legends will change to English when you point at them,) "IP", "32-Bit RISC CPU(ARC)", (yes, 32-bit risc...), and finally "x86 Series" They mention the 80186 + peripherals, not the '88, but they also mention "selectable 8/16 bit bus multiplexing" Hope this helps, Roberto Waltman. PS: Don't bother downloading the PDF "Product Brief", the link is broken.Article: 114260
"Tom Lucas" <news@REMOVE_auto_THIS_flame_TO_REPLY.clara.co.uk> wrote in message news:1168362945.66348.0@iris.uk.clara.net... >I currently have several products based around the Intel 80188 >microcontroller and it it soon to become obsolete. I believe another >company make pick up the production but I thought I'd better have a few >safety nets in case they don't. > > One idea I had was for a (probably VHDL) 80188 core that I could run in > some suitable FPGA/CPLD. I've heard of PICs and ARMs being created as IP > cores and I wondered if anyone knows of an 80188 one? This one might get you started, http://www.ht-lab.com/freecores/cpu8086/cpu86.html Hans www.ht-lab.com > >Article: 114261
"Xiaqing Wu" <Xiaoqing.Wu@xilinx.com> wrote in message news:engofa$2k51@cnn.xsj.xilinx.com... > You can change the radix of a bus to display it as binary, hexadecimal, > decimal (signed or unsigned) or ASCII. > To change the radix in waveform viewer: > > 1.. Right-click the bus signal value. > > 2.. After the bus context menu displays, select Decimal (Signed), Decimal > (Unsigned), Binary, Hexadecimal or ASCII. > > In ISE 9.1i release, you can type the following command in ISE simulator > command console: > > isim set radix hex > > Below is the link to ISE 8.2i help file: > > http://toolbox.xilinx.com/docsan/xilinx82/help/iseguide/iseguide.htm > > Xiaoqing Wu > A rather belated thanks for your reply. I can change the radix as you say but if I carry out another simulation it forgets and reverts back to decimal. It looks as an upgrade to 9.1 is required. I just hope it hasn't got too many bugs added over 8.2!Article: 114262
"Duth" <premduth@gmail.com> wrote in message news:1168047507.133379.152990@42g2000cwt.googlegroups.com... > Hi Fred, > > This was actually a bug in ISE Simulator in the 8.xi versions. We have > addressed this in ISE 9.1i. After doing some research we found out that > a majority of users like to see the values in HEX rather than decimal. > This is why in ISE 9.1i, ISE Simulator will always default to HEX in > the waveforms. > > Also another feature we have added is to save the settings such as the > radix and the order of the signals once you have changed it. This is > now saved on a per project basis, so the next time you reopen the > simulation, if you had right clicked and selected that you wanted the > bus to be in ASCII for example, then it will maintain your preference. > > > Hope that this helps > Thanks > Duth > A belated many thanks for your reply. I think a moved to 9.1 is on the cards.Article: 114263
I need to simulate a PCI-E packet stream for a design with a correctly formed LCRC. I've found some DLLP examples but no TLP examples. I've Googled for too long and come up with nothing so far. Can anyone here help?Article: 114264
sheikh.m.farhan@gmail.com wrote: > Here is the problem statement. I have an FPGA board with Spartan3-1000 > on it connected with a SATA controller. The SATA controller can be > hooked up with a SATA storate device. There is A/D on the board > connected to the FPGA. THis makes my realtime, embedded data > acquisition system. I need to store the sampled data on the hard disk > and later on read it back for post analysis. For that, I need to > implement a FAT file system inside FPGA. Can anyone guide me how to > implement this on FPGA? I dont need complex FATs like FAT32/FAT16 etc, > I am ok with a simple one like one used in digital cameras where the > files are automatically named. I have been exploring microblaze and > ucLinux for this but still haven't got a grip on it. Can anyone suggest > how to get going with it quickly? Do you have enough FPGA resources for a processor? If so, I had success with FatFS <http://elm-chan.org/fsw/ff/00index_e.html>... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 114265
Jon Beniston wrote: > > > Our main problem is when we connect the CF Card to the Board the > > > SYSTEM ACE ERROR light illuminates. We have checked to make sure that > > > it is formatted correcly using mkdosfs, as recommended by Xilinx. The > > > only thing loaded on the card is our .bin file. > > > > > > Does anyone know what else could cause this? > > > > > You have been given the answer already! > > Cheers, > Jon Actually, I had posted a reply to his "answer"! You can use the Compact Flash port in different ways. Do you still need a .ace file when you are not programming the board through the CF port? If you do need a .ace file, what do I need to do to create the specific file for my project? I have tried to create a .ace file and loaded it onto the CF Card, but I still got the error light. So if someone could enlighten me as to what I am doing wrong, that would be great. Thanks.Article: 114266
I have a piece of custom IP that recovers data from an external part. The data comes in at 312 MHz and is deserialized at 312/8. So bytes come out of the IP at 39 MHz. There is a 'data_valid' signal that is asserted while useful data is being output. I need to get this data processed as fast as possible at the MicroBlaze side. I looked at implementing a FIFO that could be read from on the OPB. However, the number of clocks needed to get data out is rather large. It appears that the FSL could be used in this situation. Is it possible to interupt the processor using an FSL signal such as the FSL_Has_Data? Then the MicroBlaze could 'get' data while there is useful data in the FSL 'FIFO'. I haven't used the FSL before and so I played with it a bit today. I am pretty sure I haven't connected everything properly, but just wondering if this sounds like a reasonable thing to do or if I am missing something blatant. The Import/Create peripheral wizard allows you to select the number of 32-bit words in the FSL. However, the parameters allow you to specify shorter bit lengths. I would like to just pass bytes up to the MicroBlaze. Anyone have any caveats or recommendations? Thanks!Article: 114267
Hi, Yes, You can connect the FSL_Has_Data to either MicroBlaze interrupt input or to the interrupt controller. It might take a few clock cycles before MicroBlaze will get to your interrupt handler code but as long as your system can handle that initial latency it would work fine. Otherwise it might be good to generate an earlier signal as the interrupt signal so that when MicroBlaze gets to your interrupt handler, the data is just valid at that time. MicroBlaze could do a blocking get so it will wait for the data becoming valid so you don't need to be exact on when to generate the interrupt signal. Göran Bilski "motty" <mottoblatto@yahoo.com> wrote in message news:1168410615.635773.178260@77g2000hsv.googlegroups.com... >I have a piece of custom IP that recovers data from an external part. > The data comes in at 312 MHz and is deserialized at 312/8. So bytes > come out of the IP at 39 MHz. There is a 'data_valid' signal that is > asserted while useful data is being output. I need to get this data > processed as fast as possible at the MicroBlaze side. I looked at > implementing a FIFO that could be read from on the OPB. However, the > number of clocks needed to get data out is rather large. It appears > that the FSL could be used in this situation. > > Is it possible to interupt the processor using an FSL signal such as > the FSL_Has_Data? Then the MicroBlaze could 'get' data while there is > useful data in the FSL 'FIFO'. I haven't used the FSL before and so I > played with it a bit today. I am pretty sure I haven't connected > everything properly, but just wondering if this sounds like a > reasonable thing to do or if I am missing something blatant. The > Import/Create peripheral wizard allows you to select the number of > 32-bit words in the FSL. However, the parameters allow you to specify > shorter bit lengths. I would like to just pass bytes up to the > MicroBlaze. Anyone have any caveats or recommendations? > > Thanks! > From news@REMOVE_auto_THIS_flame_TO_REPLY.clara.co.uk Wed Jan 10 01:41:24 2007 Path: newsdbm02.news.prodigy.net!newsdst02.news.prodigy.net!prodigy.com!newscon02.news.prodigy.net!prodigy.net!newsfeed.cw.net!cw.net!news-FFM2.ecrc.de!newsreader.cw.net!newsfeed.stueberl.de!solnet.ch!solnet.ch!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!despina.uk.clara.net From: "Tom Lucas" <news@REMOVE_auto_THIS_flame_TO_REPLY.clara.co.uk> Newsgroups: comp.arch.fpga References: <1168362945.66348.0@iris.uk.clara.net> <uoq7q29r63tmtu2joq0rmnunpdsb6rkf7a@4ax.com> Subject: Re: Possibility of 80188 VHDL core Date: Wed, 10 Jan 2007 09:41:24 -0000 Lines: 27 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 006007541651648464611261ff09677901d80c6012da251945526ac045a4b447 NNTP-Posting-Date: Wed, 10 Jan 2007 09:39:19 +0000 Message-Id: <1168421959.32614.0@despina.uk.clara.net> Xref: prodigy.net comp.arch.fpga:125433 X-Received-Date: Wed, 10 Jan 2007 04:40:11 EST (newsdbm02.news.prodigy.net) "Roberto Waltman" <usenet@rwaltman.com> wrote in message news:uoq7q29r63tmtu2joq0rmnunpdsb6rkf7a@4ax.com... > "Tom Lucas" wrote: >>I currently have several products based around the Intel 80188 >>microcontroller and it it soon to become obsolete. >>.... I've heard of PICs and ARMs being created as IP >>cores and I wondered if anyone knows of an 80188 one? > > Go to http://www.maojet.com.tw, then "Products", (The buttons with > Chinese legends will change to English when you point at them,) "IP", > "32-Bit RISC CPU(ARC)", (yes, 32-bit risc...), and finally "x86 > Series" > > They mention the 80186 + peripherals, not the '88, but they also > mention "selectable 8/16 bit bus multiplexing" Well they do say it is software compatible with the 80188 which is quite promising. Even if it is purely 80186 then altering the existing code to work on that is going to be much much less work than porting it all to an ARM or similar. It also mentions that it can be used with the Paradigm debugger which is also appealing. Plus I imagine I can throw all the UARTs, buffers and address decoding latches into the same device and save myself a large amount of board space.Article: 114268
Hi, John schrieb: > What's the best way to delay a signal? I want a certain control signal to appear X nano seconds after the rising edge of the clock. This is impossible for a fixed and guaranteed value of X. The only way you have is to use a flexible value for x. The output of a register will allways be visible a few ns after the rising edge of clk. If you need a signal to be within a given delay range, you could use gates with known delay (eg inverters) to introduce delay. But these delays are only tuneable to a certain degree due to gate and routing delays and you will only know a min and max delay for this path. This delay will vary over temperature, voltage, age and process. You need to verify, that synthesis didn't remove your delay gates, as they are typically without functionality. > Also, in VHDL, if I set the signal in a process on the rising edge, does the signal get updated at the next rising edge? if rising_edge(clk) then B <= A; C <= B; end if lead to the following wave with time wandering from left to right after each rising edge: A 0100111 B 0010011 C 0001001 bye ThomasArticle: 114269
Hi, I am getting problem due to different ise versions, in the created netlist. The parameter value for SIM_CLKIN_CYCLE_JITTER is different in 8.1 = 120 and for 8.2 = 0. Same is the case for SIM_CLKIN_PERIOD_JITTER 8.1 it is 800 8.2 it is 0. Does anybody here know why there is such a difference? Due to this my netlist simulation does not work. Is there any solution to this problem? thanks, RajendraArticle: 114270
Hi, Is there someone have the experience with using flash s29gl-n from spansion? Is it possible to enter the "Write Buffer Programming" mode when WP#/ACC = HIGH? Thanks ZhongqiangArticle: 114271
Hi all, I have to transfert signals from a clock domain to another. First clock domain is fixed, but the second can be faster or slower than the first one. Does somebody can give me some help. Thanks MatthieuArticle: 114272
Hi, I just buy a P160 analog module from Memec Design and I'd like to know the type of the 7 analog connectors. Because I've never seen this kind of connectors. Thanks. MatthieuArticle: 114273
How often does the signal change relative to the two clocks? "Matthieu Cattin" <matthieu.cattin@cern.ch> wrote in message news:eo30bh$c3j$1@cernne03.cern.ch... > Hi all, > > I have to transfert signals from a clock domain to another. > First clock domain is fixed, but the second can be faster or slower than > the first one. > > Does somebody can give me some help. > > Thanks > MatthieuArticle: 114274
Anybody allready designed a VHDL model of a stepper motor to simulate in modelsim ?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z