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Al wrote: > Hi everyone, it happened to me that by chance I interrupted ModelSim not > properly (to be honest I cannot say what happened) and on the next start > it showed me this message: > > Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use > > I tried to remove the file, thinking (uncorrectly I suppose) that the > program would have generate a new one, but it didn't work. I found on > some forums that is a problem of license but I have a Libero web > license, so if it was so I would have had problems with Libero and > Synplify as well (they are all under the same license). > Could you please explain me what happened? > Thanks a lot > > Al > > Just to add more info, I made a new project with Libero, starting everything from the scratch and only importing the source file. Now it hangs in a different way and on the bottom raw it shows: sim:/fe_pinout_tb - Limited Visibility Region where fe_pinout_tb is my testbench entity name. Any idea? Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 114476
Al wrote: > Al wrote: > >> Hi everyone, it happened to me that by chance I interrupted ModelSim >> not properly (to be honest I cannot say what happened) and on the next >> start it showed me this message: >> >> Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use >> >> I tried to remove the file, thinking (uncorrectly I suppose) that the >> program would have generate a new one, but it didn't work. I found on >> some forums that is a problem of license but I have a Libero web >> license, so if it was so I would have had problems with Libero and >> Synplify as well (they are all under the same license). >> Could you please explain me what happened? >> Thanks a lot >> >> Al >> >> > Just to add more info, I made a new project with Libero, starting > everything from the scratch and only importing the source file. Now it > hangs in a different way and on the bottom raw it shows: > > sim:/fe_pinout_tb - Limited Visibility Region > > where fe_pinout_tb is my testbench entity name. > Any idea? > > Al > Sorry again, apparently this last problem was a matter of the order in which testbench files where compiled. Fixing this latter it turned back the first one. The warning message is always the same: Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use Sorry for all these, I'm a bit in a hurry... Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 114477
I've had success using a Weller Pyropen for mounting and removing a variety of smt packages. Have a look at nibbleengineering.com if you're interested. The pyropen really comes into its element for removing a package. smount wrote: > Does anyone know what is needed to work with surface mount > ic's, what sort of starting price tag are we talking about? > (Assuming I have ready made boards, i.e. only the soldering > phase is required)Article: 114478
> Sorry again, apparently this last problem was a matter of the order in > which testbench files where compiled. Fixing this latter it turned back > the first one. > The warning message is always the same: > > Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use > > Sorry for all these, I'm a bit in a hurry... Deleting that file (vsim.wlf) works for me. You can ignore the warning anyway, it will just use another file. Also you can use vsim -wlf filename to specify another file to use. Cheers, JonArticle: 114479
Jon Beniston wrote: >>Sorry again, apparently this last problem was a matter of the order in >>which testbench files where compiled. Fixing this latter it turned back >>the first one. >>The warning message is always the same: >> >>Warning: (vsim-WLF-5000) Log file vsim.wlf currently in use >> >>Sorry for all these, I'm a bit in a hurry... > > > Deleting that file (vsim.wlf) works for me. You can ignore the warning > anyway, it will just use another file. > > Also you can use vsim -wlf filename to specify another file to use. > > Cheers, > Jon > I'm very sorry to all of you guys, it has been just a newbie error! I had a process in the testbench with no wait state and it was hanging there forever... Sorry to everyone. Al p.s.: nevertheless it keeps giving be that warning, wonder what is that for! -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 114480
That would be wonderful........ucLinux for PPC thanks for clarifying about EDk8.2........... Any ideas on porting Linux 2.6.18 on PPC for Virtex 4? Farhan Guru wrote: > Farhan, > > PLB_DDR in EDK 8.2 supports x16 DDR. I have tried it in Virtex4 Mini > Module and it works OK. > If you need a uCLinux made for PPC let me know. > > Cheers, > > Guru > > > > sheikh.m.farhan@gmail.com wrote: > > Hi, > > I need to know is it possible to have a 16-bit PLB DDR memory > > controller in EDK 8.x for a custom made board. So far what I have seen > > is EDK supports 32 and 64-bits PLB DDR controller for third party base > > systems. > > Has anyone tried to port Linux 2.4.x successfully on PPC running on > > Virtex 4? Any issues....... > > > > FarhanArticle: 114481
Is it possible to interface the Ethernet directly to the FPGA instead of the doing it through the Power PC processor or any other Processor? If yes, kindly throw some light on the same. thanks in advance.Article: 114482
Surya <aswingopalan@gmail.com> wrote: > Is it possible to interface the Ethernet directly to the FPGA instead > of the doing it through the Power PC processor or any other Processor? > If yes, kindly throw some light on the same. Did you do some basic googling befor asking? Start e.g. at http://www.fpga4fun.com/ -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 114483
Hi, I am looking for a PCI card with an FPGA on it with reasonable capacity of gates (15 million gates). I need to use this board as a hardware accelerator in a PC environment. My exact requirements for the PCI card are: 1. should have a PCI controller/ bridge on it so that I dont have to put PCI core on the FPGA. 2. the FPGA should be configurable through PCI (that means the programming pins of the FPGA should be routed to the PCI). 3. seperate IO and data bus are preferred from/to the FPGA. I will be using this hardware accelerator for speeding up DSP algorithms. The application running on windows will have several such DSP bitstreams and the user will be selecting the DSP bitstreams and downloading it on the FPGA through PCI. Data will be pumped into the FPGA through PCI using the data bus for processing while the status and command operations will be managed through the IO pins. Once the processing is done, the data will be read back by the application using the same data bus. ANYONE KNOWS ANY SUCH BOARD FULFILLING MY REQUIREMENTS? Boards I have explored are: 1. PCIS3BASE from cesys.com (supports only data bus) 2. PCI Proto Board from techniprise.com (smaller FPGA) regards FahanArticle: 114484
Thanks to both. No, the motor model cannot be trivial. (low load etc.) I really need to model the inductance-angle behaviour in order to obtain a realistic current. I am going to create a mechanism to detect the losses of steps and want to created certain extreme cases of operation. For the simutation I do not need realy the physical angle of course but the resulting PWM controlling the inductance / motor current, so I though a digital model would do. One idea was to emulate the inductance's behaviour with a circuit decribing the I according to the incoming U (done by a serial DAC). So the chain was: serial stream -> parallel -> voltage as integer -> create di/dt -> add di/dt to I , calculate accelleration, and so on thus finally obtain a virtual axis postion. Magnetism is the next. But if you say there are existing VHDL-AMS models I'll have a look at this.Article: 114485
Try www.edt-inc.com -Clark <sheikh.m.farhan@gmail.com> wrote in message news:1169036835.705100.143430@a75g2000cwd.googlegroups.com... > Hi, > I am looking for a PCI card with an FPGA on it with reasonable capacity > of gates (15 million gates). I need to use this board as a hardware > accelerator in a PC environment. My exact requirements for the PCI card > are: > 1. should have a PCI controller/ bridge on it so that I dont have to > put PCI core on the FPGA. > 2. the FPGA should be configurable through PCI (that means the > programming pins of the FPGA should be routed to the PCI). > 3. seperate IO and data bus are preferred from/to the FPGA. > > > I will be using this hardware accelerator for speeding up DSP > algorithms. The application running on windows will have several such > DSP bitstreams and the user will be selecting the DSP bitstreams and > downloading it on the FPGA through PCI. Data will be pumped into the > FPGA through PCI using the data bus for processing while the status and > command operations will be managed through the IO pins. Once the > processing is done, the data will be read back by the application using > the same data bus. > > ANYONE KNOWS ANY SUCH BOARD FULFILLING MY REQUIREMENTS? > > Boards I have explored are: > 1. PCIS3BASE from cesys.com (supports only data bus) > 2. PCI Proto Board from techniprise.com (smaller FPGA) > > > regards > Fahan >Article: 114486
Austin Lesea schrieb: > Simplest method is to use resistors to scale the voltage to the correct > levels. Austin: Let me quote the original poster: "I have a 3.3V (differential, LVPECL) clock for my MGTCLK. Are they 3.3V tolerant?" So the question remains: What are the correct levels for MGTCLK? The Virtex-4 Datasheet only specifies Peak-to-Peak Differential Input Voltage. > For a clock signal, Yes, MGTCLK is a clock signal. > you may also use capacitive coupling, The UG076 uses different wording. Accordingly capacitive coupling "must be used" (Page 191). > but you still > need to terminate the receive, No, you do not. UG076, Figure 6-7. > and then set the correct common mode level at the receiver. There is no common mode level specified anywhere that I can see it. Figure 6-7 suggests a circuit without external common mode setting. Maybe this is done internally, but who knows. Please supplement the datasheet with the missing information. Kolja SulimmaArticle: 114487
http://www.fpga-faq.org/FPGA_Boards.shtmlArticle: 114488
skyworld wrote: > well, the 312MHz clock is a input to FPGA. I do need four phases to > sample the data so that data jitter could be reduce. It is very > interesting that DCM could not output clk90 and clk270 when set it to > high speed mode -- i got this information from Xilinx FAE and simulated > this with ModelSim, but their datasheet and user guide doesn't mention > this. My design has based on these four pahse clock and DCM > performance and my PCB is ready for this. I have to find a way to solve > this. > > by the way, what do you mean by that "IDELAY"? thanks. > The DCM's limitations are explained in the Virtex 4 Switching Characteristics data sheet which is found on their website. I've found that you have to dig deeper on all technology to find real world behavior. The User Guide is not the definitive answer. It really only glosses over all the available features -- which are a lot! More detail is found in other documentation and application notes. I would never build a PCB based on just the user guide. Sorry. The Virtex 4 development boards are a VERY good investment. You can try out all the features and figure out what you need. You can read about IDELAY is the User Guide to begin with. Then you'd have to investigate the Switching Characteristics of IDELAY. And their is also a ChipSync User Guide that REALLY goes in to detail about the IDELAY.Article: 114489
Kolja, see below -snip- Sulimma wrote: > Austin: Let me quote the original poster: > "I have a 3.3V (differential, LVPECL) clock for my MGTCLK. Are they > 3.3V tolerant?" No. The IO pins are tied to the a supply through diodes, so applying any signal that exceeds that supply will forward bias the clamp diode. The common mode voltage also wants to be about 1/2 of the supply (typically, but not always, as we see below). -snip- > > There is no common mode level specified anywhere that I can see it. > Figure 6-7 suggests a circuit without external common mode setting. > Maybe this is done internally, but who knows. > > Please supplement the (V4) datasheet with the missing information. Table 12, http://direct.xilinx.com/bvdocs/publications/ds302.pdf has no common mode specifically stated for the MGT clock reference inputs. It appears that V4 FX wants to set its own common mode, hence the reason why capacitive coupling is required. And since it has an internal termination, it makes the only specification required, the peak to peak swing (everything else is automatically taken care of).Article: 114490
What are some of the considerations while migrating from a pure SW based bio-medical simulation to a HW based simulation/acceleration solution? Insights on both the business & technical considerations would be appreciated Thanks AnandArticle: 114491
In vhdl is it possible to run a process on both edges of a clock? I tried running one if-statement on the rising edge, and one on the negative but get an timing error.Article: 114492
<Jalen.Ong@gmail.com> wrote in message news:1168972993.972454.301270@v45g2000cwv.googlegroups.com... > Dear all, > > I am new to both FPGA and CPU design. I am supposed to implement a CPU > on FPGA. The CPU is described in www.homebrewcpu.com. It needs to be > exactly the same. Currently I am working on translating the microcodes > into verilog. It just seems too complex currently and I do not know > where I can seek for more information on how to do this. Any advice or > guidance will be much appreciated. Thanks! > > CHeers, > Jalen > Jalen, There is more than one way to implement Magic-1 in an FPGA. Xilinx FPGAs have internal memories called BRAM which can be pre-loaded when the FPGA is configured. You could simply load these with the same binary data as Bill Buzbee programmed into his microcode PROMs. Your CPU logic could then be functionally identical to Bill's, down to gate and flip-flop level; however, there might be an easier way to do it: do you need to use microcode? Why not just write verilog to implement the same instruction set and be compatible at opcode level? Rgds Andrew.Article: 114493
I'm trying to understand the behavior of the REV pin works on Virtex2 flops. The Virtex2 Pro/Pro-X data sheet (ds083.pdf, Module 2, Functional Description, Logic Resources -- page 36 in v4.5) states the following: "When SR is used, a second input (REV) forces the storage element into the opposite state. The reset condition predominates over the set condition." I'm not sure that I understand what that's trying to tell me. Is the following correct, or does "the reset condition predominates" mean something else? Synchronous Mode: 1. Asserting SR forces state to the selected SRHIGH/SRLOW on appropriate clock edge. 2. Asserting SR and REV forces state to inverse of SRHIGH/SRLOW on appropriate clock edge. Asynchronous Mode: 3. Asserting SR forces state to SRHIGH/SRLOW immediately. 4. Asserting SR and REV forces state to inverse of SRHIGH/SRLOW immediately. For 4, is there some required timing relationship between SR and REV? Since REV apparently does nothing on its own, does it just need to remain asserted until SR gets deasserted?Article: 114494
John schrieb: > In vhdl is it possible to run a process on both edges of a clock? For simulation it is possible. For synthesis it strongly depends on the synthesis tool. There a few (!) synthesis toots, that support this, but most of them don't. Using both edges of the clock is nothing else than a dual-edge flipflop. Such elements exist but they are very uncommon in standard cell libraries and FPGAs. If you really need dual-edge behavior for synthesis (think twice about it!) you can use a pseudo dual-edge flipflop: <http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf>. RalfArticle: 114495
What are you doing?Article: 114496
Hello rbal, What I did when creating a new application was to also copy the linker script from "TestApp_Memory" and then configure that as my linker script. That used the BRAM. Then I used "Generate Link Script" and the size of the boot section was 0x00000010. Then I just used the combo box to select SRAM. So make sure that you create TestApp_Memory when you use BSB to set up your system. Later, after you successfully load your code with GDB, it seems to make a difference between clicking on the Run icon (small pic of running man) and using the drop- down menu Run command. If you don't click on the icon, but click on the menu Run command, it seems to work and stop on the breakpoint at the beginning of main, otherwise the GDB window goes blank and the message at the bottom of the window frame says "stopped". Regards, -James rbal wrote: > >Jhlw wrote: > > Hello All, > > > > I figured out how to run an application from external memory in Xilinx. > > I have EDK ver 8.2.01i and an ML403 board. > > What you do is "Mark to init BRAMs" on the default bootloop app in > > the Applications window pane, update your bitstream and then load > > it into the board using iMPACT. > > Change your linker script using "Generate Link Script" for your > > large application and set the .text section to SRAM. Rebuild your > > app. > > > > I have done upto this in ML402 board.But I am not able to run program > from external memory. > > > You also have to set the .boot section (0x00000010) to SRAM. > > How to set the .boot section? Have I to create a new section and > select memory as SRAM.But it shows "0 bytes" and I couldn't select the > address - 0x00000010.And I am not able to run application from external > memory.Pls.advice me.Thanks > > Regards, > R.BalArticle: 114497
Jalen.Ong@gmail.com wrote: > Dear all, > > I am new to both FPGA and CPU design. I am supposed to implement a CPU > on FPGA. The CPU is described in www.homebrewcpu.com. It needs to be > exactly the same. Currently I am working on translating the microcodes > into verilog. It just seems too complex currently and I do not know > where I can seek for more information on how to do this. Any advice or > guidance will be much appreciated. Thanks! > > CHeers, > Jalen > Is the result supposed to be identical *in function* or specifically identical? If identical in function (quite possible) then simply code up the instruction set in HDL (whichever your prof. has specified, I suppose) so it matches what the microcode did. Cheers PeteSArticle: 114498
Phil Hays wrote about a one's complement adder, which uses end-around
carry:
> It looks to me like there is a chance of a pulse running around the
> carry loop for a multiple times, perhaps even forever.
I wrote:
> There is no way that can happen if the inputs are stable. For an n-bit
> one's complement adder, there can't be a carry propogation wider than n
> bits. <Snip> please give an example of operands for which it could
> occur.
Phil Hays wrote:
> Let me give an example. Note that the two inputs can be anything that are
> inverses of each other. The first two cases are stable.
>
> 1111
> +0000
> +0 Carry in
> ======
> 1111 carry out 0
>
> Note that the carry bits are 0000
A one's complement adder does not have a "carry-in" input, because
there isn't s a simple one's complement "full adder" cell with
three inputs. A one's complement adder consists of a chain of
binary full adders with the carry-out from the MSB routed to the
carry-in of the LSB; no individual piece of that structure can
stand on its own as a one's complement adder. In particular, there
is no simple way to daisy-chain two one's complement adders into
a longer one's complement adder.
If you need to add two n-bit one's complement numbers and an unsigned
one-bit carry-in, you need a three-input n-bit one's complement adder,
which is composed of *two* n-bit two-input one's complement adders:
n ---------
A ---/---> | 1's | n ---------
| comp | ---/------> | 1's | n
B ---/---> | adder | | comp | ----/---> result
n --------- ----> | adder |
| ---------
n-1 |
zeros -----/-------------------|
|
carry_in -----/--------------------
1
The internal structure of each 1's complement adder as shown is
an n-bit binary full adder with end-around carry.
The logic of the second adder can be simplified slightly due to n-1
of its inputs being hardwired to zero, but it still has to be the full
n bits wide.
If you don't build it this way, you don't get the correct result. If
you do build it this way, there isn't any way for the circuit to be
unstable (oscillate), though it is of course possible to get an
arithmetic overflow.
Eric
Article: 114499DEAR ALL, As I am a beginner in ARM AHBA bus protocol. I cant understand why AHBA bus need to limit 1Kbyte boundary? (As 1KByte (256 word) boundary crossing within a burst is Illegal.) If there is a incremental burst 20 word to transmit by a AHB Master and the Start Address is 250 word, Should I divide these into two request like, first request : Start Address 250 word, burst 6 word second request : Start Address 256 word, burst 14 word. Thanks a lot, BRs beginner.
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