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On Thu, 11 Jan 2007 12:04:50 -0700, Kevin Neilson
<kevin_neilson@removethiscomcast.net> wrote:
[Jonathan]
>> If you want transport delay in your own Verilog model, use
>> intra-assignment nonblocking delays - try tnis...
>> always @(sig_in) sig_out <= #4 sig_in;
>That is wonderful. It totally works. I wish I'd known this before.
Lots of people say that when we tell them :-)
It can do other magic too. The #N transport delay can be replaced
with an event control:
sig_out <= @(posedge clk) sig_in;
in other words, evaluate sig_in right now, and schedule it for
assignment to sig_out on the next posedge; and, even more
fun,
sig_out <= repeat (4) @(posedge clk) sig_in;
which makes a very efficient, very compact model of a
4-stage pipeline delay. Note that the assignment is nonblocking
so therefore the statement itself executes in zero time - execution
proceeds immediately - even though the assignment takes place
some considerable time later.
> I would like to
>be able to adjust the delay on-the-fly, in order to model pad/trace
>delays that change over time, but I don't think that's possible.
It's panto time... Oh yes it is!!!!
The numeric value in the delay expression is evaluated each time the
statement executes; it can be any run-time expression, unlike the
delay in a continuous assign which must be an elaboration-time
constant. The only thing to note is that any expression needs to
be enclosed in parentheses. So...
sig_out <= #(base_delay + fudge_factor * temperature) sig_in;
Take care, though. This means that later assignments can overtake
earlier assignments, if the time delay is sufficiently different:
consider this...
initial begin
S <= #10 expr1; // will update S at time=10
#5 // delay until time=5
S <= #2 expr2; // will update S at time=7
so you get the somewhat counterintuitive result that S takes on
the value expr2 at time 7, and then expr1 at time 10.
There's one piece of really bad news about this, though.
I am not aware of *any* reliable way, in Verilog, of revoking
a future nonblocking assignment once you've committed it.
Disabling the code block that did the assignment *may*
revoke its pending nonblocking assignments - some simulators
do that - but it's explicitly left undefined in the LRM.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 114326Ok, it's been a while (a few versions) since I've had to use the Xilinx Floorplanner. But I don't recall this happening before. Virtex 5, after place and route I'm in the FPGA Editor and I switch the filter to 'Unplaced Components.' None there! I load the same design in Floorplanner and execute 'Replace All with Placement.' Some symbols do get placed, but not all of them. I'm seeing some symbols including FG's left over in the Design Hierarchy window. What gives??? Is there an optimization step between .ngd/.ncd and final place/route where these rogues are taken out? - CraigArticle: 114327
You could use a pulse-extender and then re-sync to the new clock domain. Here's an example: --------------------------------------------------------------------------------- -- The LD control signals need to be pulse-extended and re-registered for the -- ld_bus_clk to accept them. --------------------------------------------------------------------------------- process(global_reset,global_clock) begin if (global_reset='1') then Ld_bus_read_en_q <= '0'; Ld_bus_read_en_qq <= '0'; Ld_bus_read_en_qqq <= '0'; Ld_bus_write_en_q <= '0'; Ld_bus_write_en_qq <= '0'; Ld_bus_write_en_qqq <= '0'; elsif (global_clock'event and global_clock='1') then Ld_bus_read_en_q <= (Ld_bus_read_en or Ld_bus_read_en_q or Ld_bus_read_en_qq) and not(Ld_bus_read_en_qqq and not(Ld_bus_read_en)); Ld_bus_read_en_qq <= Ld_bus_read_en_q; Ld_bus_read_en_qqq <= Ld_bus_read_en_qq; Ld_bus_write_en_q <= (Ld_bus_write_en or Ld_bus_write_en_q or Ld_bus_write_en_qq) and not(Ld_bus_write_en_qqq and not(Ld_bus_write_en)); Ld_bus_write_en_qq <= Ld_bus_write_en_q; Ld_bus_write_en_qqq <= Ld_bus_write_en_qq; end if; end process; process(global_reset,ld_bus_clk) begin if (global_reset='1') then Ld_bus_read_meta1 <= '0'; Ld_bus_read_meta2 <= '0'; Ld_bus_read_edge <= '0'; Ld_bus_write_meta1 <= '0'; Ld_bus_write_meta2 <= '0'; Ld_bus_write_edge <= '0'; elsif (ld_bus_clk'event and ld_bus_clk='1') then Ld_bus_read_meta1 <= Ld_bus_read_en_q; Ld_bus_read_meta2 <= Ld_bus_read_meta1; Ld_bus_read_edge <= Ld_bus_read_meta1 and not(Ld_bus_read_meta2); Ld_bus_write_meta1 <= Ld_bus_write_en_q; Ld_bus_write_meta2 <= Ld_bus_write_meta1; Ld_bus_write_edge <= Ld_bus_write_meta1 and not(Ld_bus_write_meta2); end if; end process; - Craig Matthieu Cattin wrote: > Signal can change on each rising edge or less often. > > "John_H" <newsgroup@johnhandwork.com> wrote in message > news:12qa3g2otrg95e1@corp.supernews.com... > > How often does the signal change relative to the two clocks? > > > > > > "Matthieu Cattin" <matthieu.cattin@cern.ch> wrote in message > > news:eo30bh$c3j$1@cernne03.cern.ch... > >> Hi all, > >> > >> I have to transfert signals from a clock domain to another. > >> First clock domain is fixed, but the second can be faster or slower than > >> the first one. > >> > >> Does somebody can give me some help. > >> > >> Thanks > >> Matthieu > > > >Article: 114328
Hi I need to code an arbitrator for an sdram controller so that two ip blocks can share access to it. Does anyone know of any good info on the subject? CheersArticle: 114329
I use VHDL and altera FPGAs. But the FPGA vendor shouldnt really matter much. I have VGA video stream coming into the system at just over 25Mhz at 60FPS at 640 x 480 valid pixels. Currently I am sending output to a frame grabber via camera link style output. It would be nice if there was some code out there that was video format agnostic - it wouldnt care about the video timing to be able to insert a white (or black) pixel here and there to form the letters of ascii text I am trying to achieve. Brad Smallridge wrote: > > Really > > what I want is a function that would > > convert the value of a register into say, hex or base 10 ascii text, > > and then count the number of > > rows/columns of video coming in, and insert black or white pixels into > > the video stream as appropriate to make those characters appear > > (superimposed) on the output video stream. > > Yeah. I might be able to help although I don't know what you are > using. Xilinx? Spartans? Virtex? VHDL? Verilog? > > Can we assume that you already have a VGA display that is outputting? > And so can we assume that you have row and column registers in your > design? > > Brad Smallridge > AiVision dot comArticle: 114330
"quad" <fyp.quadruples@gmail.com> writes:
> As I'd mentioned in one of my previous mails, I'm working on intrinsic
> evolution. I'd like to know if its possible to generate netlists in
> EDIF format from C itself for circuits, or will it be too complicated?
> Regards
It's pretty easy to generate EDIF if you already have a netlist
data-structure suitable for your target in your program. However, if
you are talking about synthesis of C code into a netlist it can be a
very complicated task depending upon what subset of C you allow in
your circuit description.
Petter
#include <stdio.h>
int main(int argc,char* argv[]) {
printf("(edif gate (edifVersion 2 0 0) (edifLevel 0)\n");
printf(" (keywordMap (keywordLevel 0))\n");
printf(" (status");
printf(" (written (timeStamp %d %d %d %d %d %d)\n",2007,1,11,23,17,18);
printf(" (program \"%s\" (Version \"%4d.%02d\"))\n",argv[0],2007,1);
printf(" (dataOrigin \"%s\") (author \"%s\")\n","comp.arch.fpga","Petter Gustad");
printf(" )\n");
printf(" )\n");
printf(")\n");
return 0;
}
--
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?
Article: 114331On 10 Jan 2007 09:28:03 -0800, the renowned "wallge" <wallge@gmail.com> wrote: >I would like to superimpose some text into a video stream coming from a >camera into my fpga. >Lets say I would like to print the values of several registers to the >screen as simple ascii text. This text would be superimposed over the >incoming video stream. Does anyone know if there exists a core, or some >free vhdl floating around somewhere to do this kind of thing? >I have seen some cores that do VGA timing generation, then insert pixel >values values from a look up table (but these dont do text from what I >can tell, and must be controlled by a microprocessor). > >The problem with these is that they dont really do what I want. Really >what I want is a function that would >convert the value of a register into say, hex or base 10 ascii text, >and then count the number of >rows/columns of video coming in, and insert black or white pixels into >the video stream as appropriate to make those characters appear >(superimposed) on the output video stream. > >Anyone have any ideas or thoughts? > >thanks. You might get some hints by looking at the data sheet for the STV5730A OSD chip. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 114332
Well this is Xilinx specific but
take a look at the three modules below:
overlay,vga_dump_ram
What I remember is that the row and column
registers point to both the dump RAM and
the font ROM at the same time. With the lower
bits going to the font ROM. Your idea of using
8 by 8 fonts is a good one, even if you don't
use all the rows or columns of the font.
These modules create a one bit output that
must be anded into your video stream.
Sorry I wrote these before I was inferring
RAMs and ROMs but I think the Altera switch
should be straight forward.
You also mentioned that you want to spit out
the values of a register which will take some
doing because you will need to mux the nibbles
somehow.
Good Luck,
Brad Smallridge
AiVision
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity overlay is
port(
vga_clk : in std_logic;
vga_reset : in std_logic;
vga_row : in std_logic_vector( 8 downto 0);
vga_col : in std_logic_vector(11 downto 0);
q : out std_logic;
wr_clk : in std_logic;
wr_reset : in std_logic;
wr_en : in std_logic;
wr_stop : in std_logic;
wr_addr : in std_logic_vector(11 downto 0);
wr_data : in std_logic_vector( 7 downto 0) );
end overlay;
architecture behave of overlay is
component vga_dump_ram is
port (
rst : in std_logic;
clk_a : in std_logic;
wr_a : in std_logic;
data_a : in std_logic_vector(7 downto 0);
addr_a : in std_logic_vector(11 downto 0);
clk_b : in std_logic;
addr_b : in std_logic_vector(11 downto 0);
high_b : in std_logic; -- high nibble
dout_b : out std_logic_vector(3 downto 0) );
end component;
signal vga_nibble_addr : std_logic_vector(11 downto 0);
signal vga_nibble_high : std_logic;
signal vga_nibble : std_logic_vector( 3 downto 0);
component vga_font is
port (
clk : in std_logic;
rst : in std_logic;
addr : in std_logic_vector(14 downto 0);
q : out std_logic );
end component;
signal vga_font_addr : std_logic_vector(14 downto 0);
signal vga_font_row_1 : std_logic_vector( 2 downto 0);
signal vga_font_row_2 : std_logic_vector( 2 downto 0);
signal vga_font_col_1 : std_logic_vector( 2 downto 0);
signal vga_font_col_2 : std_logic_vector( 2 downto 0);
signal vga_font_bit : std_logic;
signal vga_font_bit_1 : std_logic;
signal vga_font_bit_2 : std_logic;
signal vga_font_bit_3 : std_logic;
signal vga_font_bit_4 : std_logic;
-- added for wr_stop timing
signal wr_data_1 : std_logic_vector( 7 downto 0);
signal wr_data_2 : std_logic_vector( 7 downto 0);
signal wr_addr_1 : std_logic_vector(11 downto 0);
signal wr_addr_2 : std_logic_vector(11 downto 0);
signal wr_en_1 : std_logic;
signal wr_en_2 : std_logic;
begin
-- This process adds two clock delays to the
-- address font look-up-table and compensates
-- for the character nibble look-up-table delay
vga_font_addr_process: process(vga_clk)
begin
if(vga_clk'event and vga_clk='1') then
vga_font_row_1 <= vga_row(2 downto 0);
vga_font_col_1 <= vga_col(2 downto 0);
vga_font_row_2 <= vga_font_row_1;
vga_font_col_2 <= vga_font_col_1;
vga_font_addr <= "00000" & vga_nibble & vga_font_row_2 & vga_font_col_2;
end if;
end process;
vga_font_inst: vga_font
port map(
clk => vga_clk,
rst => vga_reset,
addr => vga_font_addr, -- in 15 bit
q => vga_font_bit ); -- out 1 bit
vga_font_bit_delay_process: process(vga_clk)
begin
if(vga_clk'event and vga_clk='1') then
vga_font_bit_1 <= vga_font_bit;
vga_font_bit_2 <= vga_font_bit_1;
vga_font_bit_3 <= vga_font_bit_2;
vga_font_bit_4 <= vga_font_bit_3;
end if;
end process;
q <= vga_font_bit_4;
vga_nibble_addr <= vga_row(8 downto 3) & vga_col(9 downto 4);
vga_nibble_high <= not vga_col(3);
vga_nibble_inst:vga_dump_ram
port map(
rst => wr_reset, -- in 1
clk_a => wr_clk, -- in 1
wr_a => wr_en_2, -- in 1
data_a => wr_data_2, -- in 8
addr_a => wr_addr_2, -- in 12
clk_b => vga_clk, -- in 1
addr_b => vga_nibble_addr, -- in 12
high_b => vga_nibble_high, -- in 1
dout_b => vga_nibble ); -- out 4
-- This process added for wr_stop pushbutton
-- or a signal like 1Hz.
-- Wr_stop kills the wr_en signal
-- after a full line has been written.
wr_stop_timing_process: process (vga_clk)
begin
if(vga_clk'event and vga_clk='1') then
wr_data_1 <= wr_data;
wr_addr_1 <= wr_addr;
wr_en_1 <= wr_en;
wr_data_2 <= wr_data_1;
wr_addr_2 <= wr_addr_1;
if(wr_stop='1') then
if( wr_en_1='1' and wr_en='0' ) then -- on falling edge
wr_en_2 <= '0'; -- kill
end if;
else
wr_en_2 <= wr_en_1;
end if;
end if;
end process;
end behave;
-- Store 8 bit data
-- Read 4 bit nibbles
-- Brad Smallridge
-- Ai Vision
-- Xilinx ISE 7.1.04i
-- ModelSimXE III 6.0d
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity vga_dump_ram is
port (
rst : in std_logic;
clk_a : in std_logic;
wr_a : in std_logic;
data_a : in std_logic_vector(7 downto 0);
addr_a : in std_logic_vector(11 downto 0);
clk_b : in std_logic;
addr_b : in std_logic_vector(11 downto 0);
high_b : in std_logic; -- high nibble
dout_b : out std_logic_vector(3 downto 0) );
end vga_dump_ram;
-- Addr_b and high_b will probably tied to a 13 bit counter
-- with high_b connected to the lowest bit of that counter.
-- If you want the highest nibble to output first,
-- as you might in a screen dump,
-- you want to invert this lowest bit.
architecture behavioral of vga_dump_ram is
signal addra : std_logic_vector(14 downto 0);
signal addrb : std_logic_vector(14 downto 0);
signal dob : std_logic_vector(31 downto 0);
signal dia : std_logic_vector(31 downto 0);
signal wea : std_logic_vector(3 downto 0);
begin
-- Offset the address by n bits,
-- 1
-- 2 '0'
-- 4 "00"
-- 9 "000"
-- 18 "0000"
-- 36 "00000"
addra <= addr_a & "000";
addrb <= addr_b & high_b & "00"; -- outputs the high nibble
first
dia(7 downto 0) <= data_a;
dia(31 downto 8) <= (others=>'1');
wea(3) <= wr_a;
wea(2) <= wr_a;
wea(1) <= wr_a;
wea(0) <= wr_a;
RAMB16_1 : RAMB16
generic map (
DOA_REG => 0, -- output registers on the A port (0 or 1)
DOB_REG => 1, -- output registers on the B port (0 or 1)
INIT_A => X"000000000", -- Initial values on A output port
INIT_B => X"000000000", -- Initial values on B output port
INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers
INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers
RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
READ_WIDTH_B => 4, -- Valid values are 1,2,4,9,18 or 36
SIM_COLLISION_CHECK => "ALL", -- "ALL", "WARNING_ONLY", "GENERATE_X_ONLY"
or "NONE"
SRVAL_A => X"000000000", -- Port A ouput value upon SSR assertion
SRVAL_B => X"000000000", -- Port B ouput value upon SSR assertion
WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
WRITE_WIDTH_B => 9) -- Valid values are 1,2,4,9,18 or 36
port map (
CASCADEOUTA => open, -- 1-bit cascade output
CASCADEOUTB => open, -- 1-bit cascade output
DOA => open, -- 32-bit A port Data Output
DOB => dob, -- 32-bit B port Data Output
DOPA => open, -- 4-bit A port Parity Output
DOPB => open, -- 4-bit B port Parity Output
ADDRA => addra, -- 15-bit A port Address Input
ADDRB => addrb, -- 15-bit B port Address Input
CASCADEINA => '0', -- 1-bit cascade A input
CASCADEINB => '0', -- 1-bit cascade B input
CLKA => clk_a, -- Port A Clock
CLKB => clk_b, -- Port B Clock
DIA => dia, -- 32-bit A port Data Input
DIB => (others=>'1'), -- 32-bit B port Data Input
DIPA => (others=>'1'), -- 4-bit A port parity Input
DIPB => (others=>'1'), -- 4-bit B port parity Input
ENA => '1', -- 1-bit A port Enable Input
ENB => '1', -- 1-bit B port Enable Input
REGCEA => '1', -- 1-bit A port register enable input
REGCEB => '1', -- 1-bit B port register enable input
SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input
SSRB => '0', -- 1-bit B port Synchronous Set/Reset Input
WEA => wea, -- 4-bit A port Write Enable Input
WEB => (others=>'0') ); -- 4-bit B port Write Enable Input
dout_b <= dob(3 downto 0);
end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity vga_font is
port (
clk : in std_logic;
rst : in std_logic;
addr : in std_logic_vector(14 downto 0);
q : out std_logic );
end vga_font;
architecture behavioral of vga_font is
type init_array_type is array(natural range <>) of bit_vector(7 downto 0);
constant vga_font_data : init_array_type :=(
"00000000",
"00111000",
"01111100",
"11000110",
"11000110",
"11000110",
"01111100",
"00111000",
"00000000",
"00011000",
"00111000",
"00011000",
"00011000",
"00011000",
"00011000",
"00111100",
"00000000",
"01111000",
"11001100",
"00011000",
"00110000",
"01100000",
"11000000",
"11111110",
"00000000",
"01111100",
"00000110",
"00000110",
"00011100",
"00000110",
"00000110",
"01111100",
"00000000",
"11001100",
"11001100",
"11001100",
"01111110",
"00001100",
"00001100",
"00001100",
"00000000",
"11111110",
"11000000",
"11000000",
"01111000",
"00011100",
"00001110",
"11111100",
"00000000",
"00001100",
"00011000",
"00110000",
"01111100",
"11000110",
"01100110",
"00111000",
"00000000",
"11111110",
"00000110",
"00001100",
"00011000",
"00110000",
"01100000",
"11000000",
"00000000",
"00111000",
"11000110",
"11000110",
"01111100",
"11000110",
"11000110",
"00111000",
"00000000",
"00111000",
"11000110",
"11000110",
"00111100",
"00011000",
"00110000",
"01100000",
"00000000",
"00111000",
"01101100",
"01101100",
"01111100",
"11000110",
"11000110",
"11000110",
"00000000",
"11111100",
"11000110",
"11000110",
"11111100",
"11000110",
"11000110",
"11111100",
"00000000",
"00111100",
"11000110",
"11000000",
"11000000",
"11000000",
"11000110",
"00111100",
"00000000",
"11111000",
"11001100",
"11000110",
"11000110",
"11000110",
"11001100",
"11111000",
"00000000",
"11111110",
"11000000",
"11000000",
"11110000",
"11000000",
"11000000",
"11111110",
"00000000",
"11111110",
"11000000",
"11000000",
"11111000",
"11000000",
"11000000",
"11000000",
X"00",X"FF"
);
function stuff_it
(
init_array : init_array_type;
init_xx : integer
) return bit_vector is
variable result : bit_vector(255 downto 0);
variable i : integer ;
variable j : integer ;
variable temp : bit_vector(7 downto 0);
begin
result :=
X"0000000000000000000000000000000000000000000000000000000000000000";
i := 0 ;
j := 32*init_xx ;
while( (j < init_array'length) and (i<256) )
loop
-- result( (i+7) downto (i) ) := init_array(j) ;
temp := init_array(j);
-- mirror bit vector
result(i+7) := temp(0);
result(i+6) := temp(1);
result(i+5) := temp(2);
result(i+4) := temp(3);
result(i+3) := temp(4);
result(i+2) := temp(5);
result(i+1) := temp(6);
result(i) := temp(7);
i := i + 8 ;
j := j + 1 ;
end loop;
return result;
end function stuff_it;
signal dob : std_logic_vector(31 downto 0);
begin
RAMB16_1 : RAMB16
generic map (
DOA_REG => 0, -- Optional output registers on the A port (0 or 1)
DOB_REG => 1, -- Optional output registers on the B port (0 or 1)
INIT_A => X"000000000", -- Initial values on A output port
INIT_B => X"000000000", -- Initial values on B output port
INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers
(TRUE or FALSE)
INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers
(TRUE or FALSE)
RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
READ_WIDTH_B => 1, -- Valid values are 1,2,4,9,18 or 36
SIM_COLLISION_CHECK => "ALL", -- "ALL", "WARNING_ONLY", "GENERATE_X_ONLY"
or "NONE"
SRVAL_A => X"000000000", -- Port A ouput value upon SSR assertion
SRVAL_B => X"000000000", -- Port B ouput value upon SSR assertion
WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
WRITE_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
WRITE_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
INIT_00 => stuff_it(vga_font_data,16#00#),
INIT_01 => stuff_it(vga_font_data,16#01#),
INIT_02 => stuff_it(vga_font_data,16#02#),
INIT_03 => stuff_it(vga_font_data,16#03#),
INIT_04 => stuff_it(vga_font_data,16#04#),
INIT_05 => stuff_it(vga_font_data,16#05#),
INIT_06 => stuff_it(vga_font_data,16#06#),
INIT_07 => stuff_it(vga_font_data,16#07#),
INIT_08 => stuff_it(vga_font_data,16#08#),
INIT_09 => stuff_it(vga_font_data,16#09#),
INIT_0A => stuff_it(vga_font_data,16#0A#),
INIT_0B => stuff_it(vga_font_data,16#0B#),
INIT_0C => stuff_it(vga_font_data,16#0C#),
INIT_0D => stuff_it(vga_font_data,16#0D#),
INIT_0E => stuff_it(vga_font_data,16#0E#),
INIT_0F => stuff_it(vga_font_data,16#0F#),
INIT_10 => stuff_it(vga_font_data,16#10#),
INIT_11 => stuff_it(vga_font_data,16#11#),
INIT_12 => stuff_it(vga_font_data,16#12#),
INIT_13 => stuff_it(vga_font_data,16#13#),
INIT_14 => stuff_it(vga_font_data,16#14#),
INIT_15 => stuff_it(vga_font_data,16#15#),
INIT_16 => stuff_it(vga_font_data,16#16#),
INIT_17 => stuff_it(vga_font_data,16#17#),
INIT_18 => stuff_it(vga_font_data,16#18#),
INIT_19 => stuff_it(vga_font_data,16#19#),
INIT_1A => stuff_it(vga_font_data,16#1A#),
INIT_1B => stuff_it(vga_font_data,16#1B#),
INIT_1C => stuff_it(vga_font_data,16#1C#),
INIT_1D => stuff_it(vga_font_data,16#1D#),
INIT_1E => stuff_it(vga_font_data,16#1E#),
INIT_1F => stuff_it(vga_font_data,16#1F#),
INIT_20 => stuff_it(vga_font_data,16#20#),
INIT_21 => stuff_it(vga_font_data,16#21#),
INIT_22 => stuff_it(vga_font_data,16#22#),
INIT_23 => stuff_it(vga_font_data,16#23#),
INIT_24 => stuff_it(vga_font_data,16#24#),
INIT_25 => stuff_it(vga_font_data,16#25#),
INIT_26 => stuff_it(vga_font_data,16#26#),
INIT_27 => stuff_it(vga_font_data,16#27#),
INIT_28 => stuff_it(vga_font_data,16#28#),
INIT_29 => stuff_it(vga_font_data,16#29#),
INIT_2A => stuff_it(vga_font_data,16#2A#),
INIT_2B => stuff_it(vga_font_data,16#2B#),
INIT_2C => stuff_it(vga_font_data,16#2C#),
INIT_2D => stuff_it(vga_font_data,16#2D#),
INIT_2E => stuff_it(vga_font_data,16#2E#),
INIT_2F => stuff_it(vga_font_data,16#2F#),
INIT_30 => stuff_it(vga_font_data,16#30#),
INIT_31 => stuff_it(vga_font_data,16#31#),
INIT_32 => stuff_it(vga_font_data,16#32#),
INIT_33 => stuff_it(vga_font_data,16#33#),
INIT_34 => stuff_it(vga_font_data,16#34#),
INIT_35 => stuff_it(vga_font_data,16#35#),
INIT_36 => stuff_it(vga_font_data,16#36#),
INIT_37 => stuff_it(vga_font_data,16#37#),
INIT_38 => stuff_it(vga_font_data,16#38#),
INIT_39 => stuff_it(vga_font_data,16#39#),
INIT_3A => stuff_it(vga_font_data,16#3A#),
INIT_3B => stuff_it(vga_font_data,16#3B#),
INIT_3C => stuff_it(vga_font_data,16#3C#),
INIT_3D => stuff_it(vga_font_data,16#3D#),
INIT_3E => stuff_it(vga_font_data,16#3E#),
INIT_3F => stuff_it(vga_font_data,16#3F#),
INITP_00 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 =>
X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 =>
X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
CASCADEOUTA => open, -- 1-bit cascade output
CASCADEOUTB => open, -- 1-bit cascade output
DOA => open, -- 32-bit A port Data Output
DOB => dob, -- 32-bit B port Data Output
DOPA => open, -- 4-bit A port Parity Output
DOPB => open, -- 4-bit B port Parity Output
ADDRA => (others=>'1'), -- 15-bit A port Address Input
ADDRB => addr, -- 15-bit B port Address Input
CASCADEINA => '0', -- 1-bit cascade A input
CASCADEINB => '0', -- 1-bit cascade B input
CLKA => '0', -- Port A Clock
CLKB => clk, -- Port B Clock
DIA => (others=>'1'), -- 32-bit A port Data Input
DIB => (others=>'1'), -- 32-bit B port Data Input
DIPA => (others=>'1'), -- 4-bit A port parity Input
DIPB => (others=>'1'), -- 4-bit B port parity Input
ENA => '0', -- 1-bit A port Enable Input
ENB => '1', -- 1-bit B port Enable Input
REGCEA => '0', -- 1-bit A port register enable input
REGCEB => '1', -- 1-bit B port register enable input
SSRA => '0', -- 1-bit A port Synchronous Set/Reset
Input
SSRB => '0', -- 1-bit B port Synchronous Set/Reset
Input
WEA => (others=>'0'), -- 4-bit A port Write Enable Input
WEB => (others=>'0') ); -- 4-bit B port Write Enable Input
q <= dob(0);
end behavioral;
Article: 114333John McCaskill wrote: > I used the bus functional models from the IBM CoreConnect toolkit with > EDK 7.1. EDK generated all the scripts to compile and run the test > bench for me, but I did not run ModelSim from within EDK. Having EDK > generate the scripts was nice, but is something that you can do > yourself. > > The BFMs did not have any Swift models in them, so you do not need that > feature. If I remember correctly, both VHDL and Verilog BFMs are > provided, so as long as your code is all one or the other you do not > need the mixed language feature. > > Some of the files are large, over 50K lines I think, so if there is a > line limit on the MXE version that might be a problem. > > Regards, > > John McCaskill > www.fastertechnology.com > Thanks, John. I was actually able to make this work in 8.2 as you describe. The "Generate simulation HDL files" command built the scripts and a starting point for a top level simulation file, then it was a matter of providing a clock and reset and fiddling with the BFL compiler. MXE is able to simulate it without complaining about any statement count exceeded, though it is not exactly fast. About 1 sec per microsecond for a setup with two 64 bit masters, one slave and a bus monitor (plus xilinx's PLB logic) on a 1.6 Ghz laptop. -JeffArticle: 114334
wallge wrote: > I use VHDL and altera FPGAs. > But the FPGA vendor shouldnt really matter much. > I have VGA video stream coming into the system > at just over 25Mhz at 60FPS at 640 x 480 valid pixels. > Currently I am sending output to a frame grabber via > camera link style output. > It would be nice if there was some code out there that was > video format agnostic - it wouldnt care about the video timing > to be able to insert a white (or black) pixel here and there to form > the letters > of ascii text I am trying to achieve. You wont be able to be video-format-agnostic for a number of reasons : To properly CHAR insert you need to phase-lock to the incomming Line Sync (often called GenLock) - if you do not do this, the chars jitter about as you have two clock domains. You also need to Sync to Frame, and count lines, to decide when to start the CHAR insert-stream. Some of the better designs insert CHARs with a drop-shadow, so they are readable over a wider range of backgrounds. Teletext chipsets, and OnScreenDisplay chips, as others have mentioned, are a good design referance for the sync-side of things -jg.Article: 114335
>From the little bit of information you provided, at XESS' website you can find design examples: http://www.xess.com/ho03000.html There is an example of a dual port sdram controller: http://www.xess.com/appnotes/an-071205-dualport.html http://www.xess.com/appnotes/an-071205-dualport.pdf http://www.xess.com/projects/dualporttst-1_0.zip You might need the sdram example too to build the project. The files are designed to be built with Xilinx ISE but it is mostly generic VHDL and it is nicely written. derek maxascent wrote: > Hi > > I need to code an arbitrator for an sdram controller so that two ip blocks > can share access to it. Does anyone know of any good info on the subject? > > CheersArticle: 114336
axr0284 wrote: > I think the issue might be in my code. I'll have to debug it. > Amish You could try an intermediate freq, just in case your total system has hit a speed ceiling :) Also, check the bit timing with a scope to confirm you have the numbers right. Some of the better UARTS support fractional baud define, where they do not always use 16 clks per bit, but can rate-multiply between 15 or 16, over the Rx bits. That gives you more Xtal freedom, and you can get closer to the precise baud rate, or higher baudrates. -jgArticle: 114337
fpgauser schrieb: > Anybody allready designed a VHDL model of a stepper motor to simulate > in modelsim ? > Hi, for a physical model you need a VHDL-AMS Model. Modelsim does not support VHDL-AMS (yet? :-) ). Everything else has been answered by Jonathan Bromleys posting before. Have a nice simulation EilertArticle: 114338
Hello, Is there anyone doing partial reconfiguration in Virtex 4? I currently suffer from errors in the "active module" phase. I made bus macros connecting two slices(for example: x0y2 and x2y2), and manually inserted the LOC constaint in ucf file like this: INST "bm16/bus4" LOC = "SLICE_X34Y6" ; INST "bm16/bus3" LOC = "SLICE_X34Y4" ; INST "bm16/bus2" LOC = "SLICE_X34Y2" ; INST "bm16/bus1" LOC = "SLICE_X34Y0" ; when i activated reconfigurable module using command "ngdbuild -modular module -active [moduleName] ..\top\top.ngc", errors appeared: ERROR:NgdBuild:630 - module 'bm16/bus1' is missing an AREA_GROUP property. WARNING:NgdBuild:885 - logical block 'bm16/bus1' with type 'bm_2b_v4_eastwest' is unexpanded and will be presumed to be a module. ERROR:NgdBuild:630 - module 'bm16/bus2' is missing an AREA_GROUP property. WARNING:NgdBuild:885 - logical block 'bm16/bus2' with type 'bm_2b_v4_eastwest' is unexpanded and will be presumed to be a module. ERROR:NgdBuild:630 - module 'bm16/bus3' is missing an AREA_GROUP property. WARNING:NgdBuild:885 - logical block 'bm16/bus3' with type 'bm_2b_v4_eastwest' is unexpanded and will be presumed to be a module. ERROR:NgdBuild:630 - module 'bm16/bus4' is missing an AREA_GROUP property. WARNING:NgdBuild:885 - logical block 'bm16/bus4' with type 'bm_2b_v4_eastwest' is unexpanded and will be presumed to be a module. is there anything wrong with my constaint? I refered several partial reconfiguration guides, in which bus macros had no AREA_GROUP property but INST properties. however, these guides are focused on vitex2 series. if anyone have virtex 4 partial reconfig tutorials, please let me know :-) PerryArticle: 114339
Jon Beniston wrote: > Pablo wrote: > > Has anybody any LWIP example?. I try to connect PC and Board. I try to > > send some package with tcp_write but I have errors because I can't get > > it. I don't want to implement a webserver, I only want a little code to > > transmit ethernet data. > > If you only want to transmit Ethernet frames, then you don't need LWIP. > > Cheers, > Jon Do you have any idea about what can I do??. I don't want to use LWIP neither XILNET but I need a fast port to comunication between PC and FPGA and RS232 is too slow. I have a Spartan 3e. Best Regards, PabloArticle: 114340
Pablo wrote: > Jon Beniston wrote: >> Pablo wrote: >>> Has anybody any LWIP example?. I try to connect PC and Board. I try to >>> send some package with tcp_write but I have errors because I can't get >>> it. I don't want to implement a webserver, I only want a little code to >>> transmit ethernet data. >> If you only want to transmit Ethernet frames, then you don't need LWIP. >> >> Cheers, >> Jon > > Do you have any idea about what can I do??. I don't want to use LWIP > neither XILNET but I need a fast port to comunication between PC and > FPGA and RS232 is too slow. I have a Spartan 3e. > How about USB? There are designs on freecores, etc.Article: 114341
Hi everybody, it may seem a little off topic, but during a discussion with my colleague about state machines we came across this name, and wondered when he lived and worked on his state machine theory. First thing was to search the net, but besides politics and genetics etc. there was not even his first name mentioned, not to speak of when or where he lived and worked. Anyone has an idea/reference? Thank you in advance EilertArticle: 114342
Hi, I need to know is it possible to have a 16-bit PLB DDR memory controller in EDK 8.x for a custom made board. So far what I have seen is EDK supports 32 and 64-bits PLB DDR controller for third party base systems. Has anyone tried to port Linux 2.4.x successfully on PPC running on Virtex 4? Any issues....... FarhanArticle: 114343
Phil Hays wrote: (snip regarding carry and ones complement adders) > The case of interest is a calculation that should result in an answer of > zero. Note that there are two representations of zero in one's complement > notation, all '1's and all '0's, often called negative zero and positive > zero. > If there is a carry, the answer is all '0's, or positive zero. If there is > no carry, the answer will be all '1's, or negative zero. If this were really a problem I don't believe Cray would have built ones complement machines when he was trying to build them as fast as possible. As far as I know (never having actually tried to build a ones complement machine) it is more usual to use a subtractor than adder. The reason I always thought it was done was to reduce the negative zero results. Does a subtractor still have this effect? Also, a Xilinx implementation will have the wraparound carry much slower than the others. Is real logic symmetric in propagation time for zero and one? -- glenArticle: 114344
(comp.dcom.lans.ethernet added) axr0284 wrote: > Thanks for the answer. This is strange. I guess i am confused with the > results from software programs I used such as the one on this website > http://www.zorc.breitbandkatze.de/crc.html > and what I get in hardware. I would expect it to the same but i am not > sure that it is. I am trying to implement a MAC in an FPGA and I need > to be sure that what I am sending to the PHY and out on the wire will > be understood by the receiving MAC from a NIC card for example. I am pretty sure that the design allows a simple LFSR with the transmitted bits as input, and then shifted out at the appropriate time. I believe, but am slightly less sure, that it also works such that a properly received frame will generate a constant value in the same LFSR when run through the data and FCS of the incoming frame. Ethernet was designed in the days when logic was much more expensive than today. Simplifying the required logic was important. (snip) > Now it clearly states in the 802.3 specs that "The bit sequence is > complemented and the result is the CRC" (snip) > "The 32 bits of the CRC value are placed in the frame check sequence > field so that the x31 term is the leftmost bit of the first octet, > and the x0 term is the right most bit of the last octet. > (The bits of the CRC are thus """transmitted""" in the order x31, > x30..., x1, x0.)" (snip) -- glenArticle: 114345
Colin Hankins wrote: (snip) > The FCS of the ethernet packet is the only portion that is sent most > significant bit first. Thus there is no need to "switch" it. That isn't quite true, as an FCS isn't a number, it is a bit string. That is, it doesn't have place values. All bits are equally significant in the result. (Being only tested for equality.) Mathematically each bit is a coefficient of a term in a polynomial, but they are separate terms. Now, you might associate the bit with the higher power with the MSB, but if you consider it in terms of an LFSR even that doesn't matter. -- glenArticle: 114346
axr0284 wrote: > When computing the packet for sending, it gives me the proper answer. > It's when receiving that i am having an issue since I do not see the > "magic number as the output of the CRC module. I think i might be > feeding in the original CRC at the end of the packet the wrong way or > something. That wouldn't make sense, because, as the bits come in you don't know when the CRC starts until after it is done. Consider doing it with an LFSR with the bit stream as input. -- glenArticle: 114347
glen herrmannsfeldt wrote: > axr0284 wrote: > >> When computing the packet for sending, it gives me the proper answer. >> It's when receiving that i am having an issue since I do not see the >> "magic number as the output of the CRC module. I think i might be >> feeding in the original CRC at the end of the packet the wrong way or >> something. > > That wouldn't make sense, because, as the bits come in you don't know > when the CRC starts until after it is done. Consider doing it with > an LFSR with the bit stream as input. The packet start and end are available from the physical layer (for example in 8b/10b coding the S and T sets). Add few pipeline stages and the crc can be easily extracted from the packet. I think the single bit LFSR solution is the worst one with current technology. With gigabit Ethernet the LFSR must run at 1GHz frequency, that is hard even with ASICs and consumes power. With 32b parallel crc calculation the frequency is just ~30MHz which is easy to handle, and with 32 bits the parallel implementation does not have so many layers of logic. The pseudocode I sent earlier is from working ethernet mac chip, it does not use the magic number, but recalculates the crc and compares the two crc values. --KimArticle: 114348
Hooray! I have finally transfered my projects to ISE/EDK 8.2, with success. *BUT* Everithing works fine, except that I can't debug woth XMD and mb-gdb of version 8.2.02. When downloading the code it will always stop with the message: "Program Download failed trying to reset the Processor.." But if I use XMD /mb-gdb from 8.1.03 and the code generated by EDK 8.2.02, I can work perfectly. But now I am forced to use microblaze 4.00.a, as XMD 8.1.03 ddoes not understand microblaze 4.00.b. And I am limited in my possibilities to change firmware, as I should be forced to change both in 8.1 and 8.2 (and it may be impossiible) Does anyonme know a solution or workaround to this problem? Or do I directly file a support case with Xilinx? Best regards, ZaraArticle: 114349
Hi, It's been over two years since I released xc3sprog. Since then Xilinx has released ISEWebPack for GNU/Linux. Many people have sent me modifications for various additions to xc3sprog. A lot has happenned to me in two years. I moved house (the Xilinx kit is still in the loft). Have completeted my Ph.D. except the thesis which seems to take for ever. What I would like to do is to incorporate the many suggestions and patches into the next release of xc3sprog if people are still using it. I would be particularly interested in modifications to xc3sprog for USB programmers. My laptop does not have a parallel port:( Regards Andrew Rogers -- Spartan3 configuration JTAG download tool for GNU/Linux available from http://www.rogerstech.co.uk/xc3sprog/
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