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On 27 Dec 2006 04:51:57 -0800, jetmarc@hotmail.com wrote: >> Just read the OPB specification (take a look at OPB bus pdf inside >> SDK), it is really easy to write an OPB bus master > >How easy is it to make the OPB master co-exist in EDK with other OPB >peripherials? I guess one has to make at least a "signal exposer" stub >with the EDK tools, so that it integrates well. Is that right? > >Regards, >Marc Yes, of course, you need an MPD file that exposes the signal for the EDK. Just copy and paste the relevant parts form opb_ipif, it is fast and safe. Regards, ZaraArticle: 113876
Vitaliy wrote: > Hello, > > I have seen this question many times in the newsgroups but I did not > see a clear answer. > I have to perform various operations on arrays of data (such as > multiplication, addition, finding mean, etc.). I have code written in > Matlab and would like to translate it to vhdl. I understand that such > subroutines as imagesc, imwrite, etc. might not be possible to > translate to vhdl and will need to be written (or similar functions > might be already implemented in vhdl). Is there anyway of directly > translating Matlab code directly to vhdl? Can this be done using > Simulink (Xilinx System Generator)? I don't have System Generator at > home and Xilinx doesn't seem to have evaluation version (asking for > Product Serial Number). Or maybe my question should be: can this be > done in Simulink to start with? > I have Xilinx FPGA/ISE. And if this can not be done using System > Generator, is there anything else that can be used? > > Please let me know if my requirements are not very clear. At the moment there is no such thing. There are several Simulink based tools out there which help you get to hardware. You have to pay for these though, and you will really have no "golden" code if you go this route. I have written VHDL packages: http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/files.html Which follows the rules in Matlab, so creating this program should be possible.Article: 113877
ADEPT may be helpful on this. It can downloaded free at http://home.comcast.net/~jimwu88/tools/adept/ Cheers, Jim axalay wrote: > Where I may assigned a special pins: Rocket IO Rx and Tx ?Article: 113878
Please look at the AccelDSP tool from Xilinx.. It is based on Matlab language to HDL conversion for Xilinx devices. http://www.xilinx.com/ise/dsp_design_prod/acceldsp/index.htm System Generator is based on Simulink based design environment to HDL conversion for Xilinx devices. http://www.xilinx.com/ise/optional_prod/system_generator.htm Regards Hemang "Vitaliy" <m.vitaliy@gmail.com> wrote in message news:1166942505.539462.226650@48g2000cwx.googlegroups.com... > Hello, > > I have seen this question many times in the newsgroups but I did not > see a clear answer. > I have to perform various operations on arrays of data (such as > multiplication, addition, finding mean, etc.). I have code written in > Matlab and would like to translate it to vhdl. I understand that such > subroutines as imagesc, imwrite, etc. might not be possible to > translate to vhdl and will need to be written (or similar functions > might be already implemented in vhdl). Is there anyway of directly > translating Matlab code directly to vhdl? Can this be done using > Simulink (Xilinx System Generator)? I don't have System Generator at > home and Xilinx doesn't seem to have evaluation version (asking for > Product Serial Number). Or maybe my question should be: can this be > done in Simulink to start with? > I have Xilinx FPGA/ISE. And if this can not be done using System > Generator, is there anything else that can be used? > > Please let me know if my requirements are not very clear. > > Thanks, > Vitaliy >Article: 113879
Hello, I've been using AHDL for a while and the people in my shop have been using it since it was developed. I think it was an HDL that was designed by hardware engineers and for hardware engineers. AHDL is so much easier to learn and use but I'm confused why their isn't a huge following of people using it. I hope that the next big HDL to catch on will be as easy as AHDL. I've looked at SystemVerilog and it seems to be at a highler level that AHDL, maybe that will decrease development time, I don't know. I've also heard that SystemC could be the next HDL. But I believe as well as my co-workers that AHDL will die and be replaced, the question is, with what? Any thoughts on the topic? thanks, joeArticle: 113880
Hi,
I have been fighting with this for some time now and I cannot figure
it out. I have read the 802.3 information and I have read a lot of
forums and they all have some kind of general answer.
I am trying to create a very simple MAC module that will send data to a
PHY for transmission. I am currently using the aesic crc VHDL function
to perform my CRC checks.
Let's say I want to send the following packet (I know this is not a
correct ethernet packet. Bear with me):
00 00 12 33 FF FF (in bytes) The bytes will be sent with the left most
byte first.
0000 0000 0000 0000 0001 0010 0011 0011 1111 1111 (in bits)
I would first switch the bits in each byte individually and then feed
it to the CRC module which has been initialized with all 1s.
Therefore
0000 0000 0000 0000 1000 0100 1100 1100 1111 1111
is fed into the CRC module starting with the byte on the left most
side.
Hopefully this is correct so far.
After the last byte is fed through, I will grab the output of the CRC
module, Invert it and shift it's bits.
The output from the CRC is
7E 11 64 34 ( in bytes)
0111 1110 0001 0001 0110 0100 0011 0100 ( in bits)
After inverting
1000 0001 1110 1110 1001 1011 1100 1011 ( in bits)
After switching
1101 0011 1101 1001 0111 0111 1000 0001 ( in bits)
D3 D9 77 81 ( in bytes)
This means that my packet that I will send to the PHY will be start
with the left most byte
00 00 12 33 FF FF D3 D9 77 81 ( in bytes)
This value seems to agree with some CRC32 software I found on the net.
**************************************************
NOW lets say i am receiving this data from the PHY.
00 00 12 33 FF FF D3 D9 77 81 ( in bytes)
I do the same as for sending, I switch the bits in each byte (including
the FCS) and feed it to the CRC module which has been initialized to
all 1. After sending the right most byte, I should get the magic number
C7 04 DD 7B out which says that it is working but i don't. Below is the
exact sequence of CRC output:
Previous CRC Value | Input | Next CRC Value | Next FCS Value
FFFFFF | 00 | 4E08BFB4 |
D202EF8D
4E08BFB4 | 00 | 00B7647D |
41D912FF
00B7647D | 12 | A5EAE0CF |
0CF8A85A
A5EAE0CF | 33 | 648CF998 |
E660CED9
648CF998 | FF | 82AF68FF |
00E90ABE
82AF68FF | FF | 7E116434 |
D3D97781
7E116434 | D3 | BB9FD215 |
57B40622
BB9FD215 | D9 | 07F1A3E0 |
F83A701F
07F1A3E0 | 77 | 16C33676 |
91933c97
16C33676 | 81 | F86C1D9B |
2647C9E0
The VHDL code I used is below:
process(clk)
begin
if(clk'event and clk = '1') then
crc_32_out <= nextCRC32_D8(input0(0) & input0(1) & input0(2) &
input0(3) & input0(4) & input0(5) & input0(6) & input0(7), input1);
for i in 31 downto 0 loop
crc_32_final(i) <= NOT crc_32_out(31-i);
end loop;
end if;
end process;
I am at a lost here. I know this is a lot of information but i hope
somebody can help me out. I guess this will also help anybody that
researches this topic after me. Thanks a lot,
Amish
Article: 113881<jjlindula@hotmail.com> wrote in message news:1167259074.129278.26670@n51g2000cwc.googlegroups.com... > Hello, I've been using AHDL for a while and the people in my shop have > been using it since it was developed. I think it was an HDL that was > designed by hardware engineers and for hardware engineers. AHDL is so > much easier to learn and use but I'm confused why their isn't a huge > following of people using it. I hope that the next big HDL to catch on > will be as easy as AHDL. I've looked at SystemVerilog and it seems to > be at a highler level that AHDL, maybe that will decrease development > time, I don't know. I've also heard that SystemC could be the next HDL. > But I believe as well as my co-workers that AHDL will die and be > replaced, the question is, with what? > Closed proprietary languages tend to either survive in a small niche where they may offer some distinct advantage over the mainstream languages....or they die due to lack of a following and lack of an investment in keeping the language relevant as technology marches on. If your place is productive in AHDL then don't fight it; your increased productivity may give you an advantage over your competitors if you're correct. If you sense that AHDL will die and leave you with no support though....well, best to jump ship before it goes down completely. KJArticle: 113882
I thought SystemC is for verification and not for design? :) Norbert Stuhrmann wrote: > Hello, > > jjlindula@hotmail.com schrieb: > > What is the next big HDL > > that will catch on and grab people from these different HDL > > backgrounds? Will VHDL, Verilog, AHLD, or SystemVerilog be replaced by > > something better? If so, what do you think it will be? > > Maybe SystemC for it's ability do to software/hardware co-design? > > Regards, > > NorbertArticle: 113883
10 years from now, I will say SystemVerilog. 20 years from now, I will say Microsoft will get involved in our world. Something like a .NET framework will be introduced for all the launguages (SW and HDL). With the framework, you can choose whatever languages as you like even if software language (e.g. Java, C#, C++, VB and etc.). Having say that, 30 years from now, we no longer need to "place & route" your RTL to the hardware. Write RTL code and the interpreter will translate it the post-P&R netlist.Save compilation times by X100. It is just my prediction. Make sense? hahahhahah... jjlindula@hotmail.com wrote: > Hello, I''ve been talking with a co-worker about the HDL languages that > are availabile these days, such as VHDL, Verilog, SystemVerilog, and > AHDL. In g, AHLD, or SystemVerilog be replaced by > something better? If so, what do you think it will be? > > thanks, > joeArticle: 113884
axr0284@yahoo.com wrote: > is fed into the CRC module starting with the byte on the left most > side. > > Hopefully this is correct so far. Did you remeber to initialize the CRC funtion to all 1 at the beginning. Rough code from my old working Ethernet CRC calculator is following (there might be some twists in the code that i don't remember anymore). The CRC function seems to be the same that easics tool give, altough it's done by other tools. Pseudocode: data_input,incoming_data,crc_tmp,final_crc : std_logic_vector(7 downto 0) for_all_bytes: for i in 0 to 7 loop data_input(i) <= incoming_data(7-i); end loop for_all_bytes: if start_of_packet crc_tmp=crc_32_8(data_input,others=>'1') else crc_tmp=crc_32_8(data_input,crc_tmp) finish_calc: final_crc=NOT(crc_tmp) --KimArticle: 113885
jjlindula@hotmail.com wrote: > Hello, I've been using AHDL for a while and the people in my shop have > been using it since it was developed. I think it was an HDL that was > designed by hardware engineers and for hardware engineers. AHDL is so > much easier to learn and use but I'm confused why their isn't a huge > following of people using it. I hope that the next big HDL to catch on > will be as easy as AHDL. I've looked at SystemVerilog and it seems to > be at a highler level that AHDL, maybe that will decrease development > time, I don't know. I've also heard that SystemC could be the next HDL. > But I believe as well as my co-workers that AHDL will die and be > replaced, the question is, with what? > > Any thoughts on the topic? > > thanks, > joe AHDL's purpose was synthesis. Without simulation support, the more complex designs leave a bit to be desired. Verilog and VHDL brought simulation and synthesis together and developed over the years as AHDL sat, doing a fine little synthesis job. But could it do anything complex? Proprietary languages are tough. I couldn't see the "Altera Hardware Description Language" catching on at Xilinx or LSI, for instance.Article: 113886
"ChampDog" <ChampDog@gmail.com> wrote in message news:1167276522.543236.189000@i12g2000cwa.googlegroups.com... >I thought SystemC is for verification and not for design? :) Not anymore, Bluespec and Celoxica both offer SystemC synthesis products. There is also a SystemC Synthesizable subset (still in draft?) Hans www.ht-lab.com > > Norbert Stuhrmann wrote: >> Hello, >> >> jjlindula@hotmail.com schrieb: >> > What is the next big HDL >> > that will catch on and grab people from these different HDL >> > backgrounds? Will VHDL, Verilog, AHLD, or SystemVerilog be replaced by >> > something better? If so, what do you think it will be? >> >> Maybe SystemC for it's ability do to software/hardware co-design? >> >> Regards, >> >> Norbert >Article: 113887
Kim Enkovaara wrote: > axr0284@yahoo.com wrote: > > > is fed into the CRC module starting with the byte on the left most > > side. > > > > Hopefully this is correct so far. > > Did you remeber to initialize the CRC funtion to all 1 at the beginning. > > Rough code from my old working Ethernet CRC calculator is following (there > might be some twists in the code that i don't remember anymore). The CRC > function seems to be the same that easics tool give, altough it's done by > other tools. > > Pseudocode: > > data_input,incoming_data,crc_tmp,final_crc : std_logic_vector(7 downto 0) > > for_all_bytes: > for i in 0 to 7 loop > data_input(i) <= incoming_data(7-i); > end loop > > for_all_bytes: > if start_of_packet > crc_tmp=crc_32_8(data_input,others=>'1') > else > crc_tmp=crc_32_8(data_input,crc_tmp) > > finish_calc: > final_crc=NOT(crc_tmp) > > --Kim Yes the CRC module is always initialized to all 1 for the first byte. AmishArticle: 113888
When computing the packet for sending, it gives me the proper answer. It's when receiving that i am having an issue since I do not see the "magic number as the output of the CRC module. I think i might be feeding in the original CRC at the end of the packet the wrong way or something. AmishArticle: 113889
jjlindula@hotmail.com wrote: > Hello, I've been doing some web researching on the next HDL and I've > found interest in SystemVerilog, SystemC and EVHDL, and Confluence. I would be interested why you found interest in the listed ones and not in MyHDL or JHDL? I don't want to argue about SymstemC and SystemVerilog, but why e.g. Confluence, which from my feeling is getting less and less users? Cheers, GuenterArticle: 113890
axr0284 wrote: > When computing the packet for sending, it gives me the proper answer. > It's when receiving that i am having an issue since I do not see the > "magic number as the output of the CRC module. I think i might be > feeding in the original CRC at the end of the packet the wrong way or > something. Then just why don't you calculate the CRC while receiving only for the data and compare the two CRC values. You just have to make sure that the sender works fine. I used commercial testers to make sure that the calculated CRC matches real world. --KimArticle: 113891
Hello, I'm developing a redundant design in ISE of Xilinx. When I simulate a design the tool shows the following message : Unit <csa4bits_tmr>: instances <csa1tmr>, <csa2tmr> of unit <add4csac> are equivalent, second instance is removed. I need that the tool doesn't remove the redundant logic. I want to compare for exemplo a protected block with a umprotected block. I turn off some features the tool but it did not efect. I would like to know if there is option or some thing in ISE that allows a redundant logic in a design because it is essential for me. Sorry (bad english) thank you ..Article: 113892
Guenter, Hello, I'm glad you mentioned those two examples. I wasn't aware of them and didn't come across them in the web seaching I did. I will certainly look them over. What's your opinion of these two HDL's, are they catching on with people and are they easy to use? A lot of the newer HDL's are very high level languages which tend to look very familiar to C. For me that takes a little getting used to, I'm still thinking at the gate level, but I can diffently see the advantage with these HDL's. Thanks and keep the opinions coming. joe Guenter wrote: > jjlindula@hotmail.com wrote: > > Hello, I've been doing some web researching on the next HDL and I've > > found interest in SystemVerilog, SystemC and EVHDL, and Confluence. > > I would be interested why you found interest in the listed ones and not > in MyHDL or JHDL? > > I don't want to argue about SymstemC and SystemVerilog, but why e.g. > Confluence, which from my feeling is getting less and less users? > > Cheers, > > GuenterArticle: 113893
I used to believe that ChipScope did not have any impact on the design. I used to. I have two FPGAs communicating on the PCB (LVDS). One of them (called source here) is doing some signal processing and sends the result to the destination FPGA. If I probe (with ChipScope) some internal results of the processing (FFT output) in the source, the data looks fine at the destination. However, if I remove the probe I get some interesting, but rather annoying, bit errors in the data received (and probed) at the destination. Before probing at the source I thought this was an issue of signal integrity on the PCB, but the probing proved me wrong on that point. The source is a V2000 device and without the probing about 90% of BRAM and mults are utilized. I would think that by adding a ChipScope core PAR would have more troubles meeting timing constraints, and consequently deliver a design more prone to bit errors... Maybe delivering the design with ChipScope still in it is my only choice, but it doesn't feel very good. Anyone who have had similar experiences? -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 113894
"Johan Bernspång" <xjohbex@xfoix.se> wrote in message news:en11k1$f7u$1@mercur.foi.se... >I used to believe that ChipScope did not have any impact on the design. I >used to. > > I have two FPGAs communicating on the PCB (LVDS). One of them (called > source here) is doing some signal processing and sends the result to the > destination FPGA. If I probe (with ChipScope) some internal results of the > processing (FFT output) in the source, the data looks fine at the > destination. However, if I remove the probe I get some interesting, but > rather annoying, bit errors in the data received (and probed) at the > destination. > Hi Johan, Do you register all the signals in the IOBs using the dedicated IOB FFs? Rx and Tx? Are you using global clock buffers fed from the dedicated GCLK pins to clock these FFs? If not, then any changes in the timing could bugger everything up if you've not constrained the timing between the parts properly. The Chipscope thing could be just coincidence, or maybe slowing the timing brings things back in to alignment. HTH, Syms.Article: 113895
jjlindula@hotmail.com wrote: > Guenter, > > Hello, I'm glad you mentioned those two examples. I wasn't aware of > them and didn't come across them in the web seaching I did. OK, I thought you had already ruled them out. There is actually another one, I think it is called perl HDL. > I will > certainly look them over. What's your opinion of these two HDL's, are > they catching on with people and are they easy to use? A lot of the > newer HDL's are very high level languages which tend to look very > familiar to C. For me that takes a little getting used to, I'm still > thinking at the gate level, but I can diffently see the advantage with > these HDL's. At the end I think they are used by people that know the respective language. I am not very familiar with JHDL. I like to use MyHDL, because on the verification side it provides all the nice things that Python provides. Especially in DSP applications there are rich Python modules that I can use to generate reference models or stimulus for the simulation and in connection with the unittest modul do a self checking test bench based on assertions. On the other side it is also possible to model hardware in MyHDL and convert it into synthesizable Verilog (at the moment VHDL is in production). At the end, it comes down to the designer's preference and a path to be able to finish the job. At the end of that path there are always the vendor tools. So looking at them will show you which way to go. Consider how much in the past people tooted the dead of one or the other major HDL's like Verilog or VHDL. Both are still around and you see vendors adding new features of them to their tools.Article: 113896
<axr0284@yahoo.com> wrote in message news:1167259663.414854.45200@73g2000cwn.googlegroups.com... > Hi, > I have been fighting with this for some time now and I cannot figure > it out. I have read the 802.3 information and I have read a lot of > forums and they all have some kind of general answer. > > I am trying to create a very simple MAC module that will send data to a > PHY for transmission. I am currently using the aesic crc VHDL function > to perform my CRC checks. > > Let's say I want to send the following packet (I know this is not a > correct ethernet packet. Bear with me): > 00 00 12 33 FF FF (in bytes) The bytes will be sent with the left most > byte first. > > 0000 0000 0000 0000 0001 0010 0011 0011 1111 1111 (in bits) > > I would first switch the bits in each byte individually and then feed > it to the CRC module which has been initialized with all 1s. > > Therefore > > 0000 0000 0000 0000 1000 0100 1100 1100 1111 1111 > > is fed into the CRC module starting with the byte on the left most > side. You flipped nibbles, not bytes. 0000 0000 0000 0000 0100 1000 1100 1100 1111 1111 or 00 00 48 CC FF FF hex is what you should input > > Hopefully this is correct so far. > > After the last byte is fed through, I will grab the output of the CRC > module, Invert it and shift it's bits. > > The output from the CRC is > > 7E 11 64 34 ( in bytes) > > 0111 1110 0001 0001 0110 0100 0011 0100 ( in bits) > > After inverting > > 1000 0001 1110 1110 1001 1011 1100 1011 ( in bits) > > After switching > > 1101 0011 1101 1001 0111 0111 1000 0001 ( in bits) > > D3 D9 77 81 ( in bytes) > The FCS of the ethernet packet is the only portion that is sent most significant bit first. Thus there is no need to "switch" it.Article: 113897
1) I agree with others: simulation, simulation, simulation, and .....debug Before the day of things like chipscope I used to reserved 16 ~ 32 spare pins and route them to the headers, now the logic analyzer is your best friend. I don't recall having any design with full system simulation, but with only the CMOS sensor and static RAM, it's doable 2) It depends on your time budget. By the way, I'm not familiar with CMOS sensor, what kind of interface/interactive signals you have on the CMOS? If most of them like the I2C interface then it's not worth to write a model for it. cheers, CMOS wrote: > hi all, > > im in the process of designing and implementing a digital system on a > spartan 3 FPGA. apart from the FPGA, im using two static RAM's and a > CMOS image sensor for this design. Compared with other digital systems, > this design is fairly simple. But im facing lot of trouble when it > comes > to debugging . Currently im using Chipscope pro for debugging, but the > hassle of updating the connections and lack of block RAM for signal > storage has forced me to investigate other possibilities for debugging. > Since the design involves a CMOS sensor and a RAM, i cant do a full > system simulation either. > > 1) Does any one know a better way of debugging? > 2) Is it common to write a simulation model for external > components(like CMOS sensor) so that the whole system can be simulated? > > > im guessing at least one of the above should exist, as making a real > world complex digital system with the methods im using currently will > be very time consuming and error prone. > > any help is appreciated. > > thank you.Article: 113898
The tool is smart enough to know that you're not going to use it, so it
removes the redundant blocks.
hsfranck@gmail.com wrote:
> Hello,
>
> I'm developing a redundant design in ISE of Xilinx. When I simulate a
> design the tool shows the following message :
>
> Unit <csa4bits_tmr>: instances <csa1tmr>, <csa2tmr> of unit <add4csac>
> are equivalent, second instance is removed.
>
> I need that the tool doesn't remove the redundant logic. I want to
> compare for exemplo a protected block with a umprotected block. I turn
> off some features the tool but it did not efect.
>
> I would like to know if there is option or some thing in ISE that
> allows a redundant logic in a design because it is essential for me.
>
> Sorry (bad english)
>
> thank you ..
From spampostmaster@comcast.net Thu Dec 28 14:34:52 2006
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NNTP-Posting-Date: Thu, 28 Dec 2006 16:33:07 -0600
From: Phil Hays <spampostmaster@comcast.net>
Subject: Re: Xilins ISE Re-Creating Projects
Date: Thu, 28 Dec 2006 14:34:52 -0800
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marc_ely wrote:
> Re-creating a project each time seems very laborious. Does anyone have
> any shortcuts to do this? Is there a TCL script that can be run?
You could write a Tcl script to create and recreate your project file.
Run a Tcl script like the example below rather than directly launching
ISE. This example script creates a project, runs the design, and then
launches ISE. It also uses two .ucf file, one of which might have the
timing information, and other might have the placement information.
--
Phil Hays
Example follows:
<cut here>
###############################################################################
# Created by Phil Hays, Xilinx
# Setup Xilinx environment, then run from Unix with "xtclsh dice.tcl"
#
# This Tcl script will implement a design and load it in the S3E FPGA on
# the Spartan 3E Starter Kit Board
#
# There are two ucf files, one for pins and one for timing
#
###############################################################################
# Contact : e-mail hotline@xilinx.com
# phone + 1 800 255 7778
#
# Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
# provided to you "as is". Xilinx and its licensors make and you
# receive no warranties or conditions, express, implied,
# statutory or otherwise, and Xilinx specifically disclaims any
# implied warranties of merchantability, non-infringement, or
# fitness for a particular purpose. Xilinx does not warrant that
# the functions contained in these designs will meet your
# requirements, or that the operation of these designs will be
# uninterrupted or error free, or that defects in the Designs
# will be corrected. Furthermore, Xilinx does not warrant or
# make any representations regarding use or the results of the
# use of the designs in terms of correctness, accuracy,
# reliability, or otherwise.
#
# LIMITATION OF LIABILITY. In no event will Xilinx or its
# licensors be liable for any loss of data, lost profits, cost
# or procurement of substitute goods or services, or for any
# special, incidental, consequential, or indirect damages
# arising from the use or operation of the designs or
# accompanying documentation, however caused and on any theory
# of liability. This limitation will apply even if Xilinx
# has been advised of the possibility of such damage. This
# limitation shall apply not-withstanding the failure of the
# essential purpose of any limited remedies herein.
#
# Copyright (c) 2006 Xilinx, Inc.
# All rights reserved
#
###############################################################################
# Version 1.0 - 19-Oct-2006
# Initial version
###############################################################################
###############################################################################
# MAIN
###############################################################################
# Modify the project settings for the specific design
#
# Make sure there are no files in the build directory that you may want to
# keep, as this TCL script cleans that directory by default!
###############################################################################
set PROJECT dice; # CHANGE THIS TO MATCH YOUR NAME !!!
if {[file exists [file join ".." bld]]} {
puts "Deleting All Existing Project Files"
# Perhaps ask ok here??
# Or perhaps skip project creation if project exists??
file delete -force [file join ".." bld]
}
puts "Creating New Project directory..."
file mkdir [file join ".." bld]
###############################################################################
# Put two ucf file into one.
# This could be made as complex as required, however for demonstration it is
# just a simple copy.
###############################################################################
puts "Creating New UCF file..."
set tempucf [file join ".." bld temp.ucf]
set outfile [open $tempucf "w"]
set infile [open "dice.ucf" "r"]
while {![eof $infile]} {
puts $outfile [gets $infile]
}
close $infile
set infile [open "time.ucf" "r"]
while {![eof $infile]} {
puts $outfile [gets $infile]
}
close $infile
close $outfile
#
cd ..
cd bld
project new $PROJECT.ise
project set family spartan3e
project set device xc3s500e
project set package fg320
project set speed -4
###############################################################################
# Modify the xfile add argument for the source files in the design
###############################################################################
puts "Adding Source Files..."
xfile add ../src/dice.vhd
xfile add temp.ucf
###############################################################################
# Set optional implementation options here. There is a problem with
setting # project properties that at least one source must be added to the
project # first. Therefore, the "project set" commands are after the
"xfile add" # commands.
###############################################################################
puts "Setting Project Properties..."
project set "Optimization Effort" High
project set "Cores Search Directories" ../src
project set "Read Cores" true ;# default is true, don't need to set
project set "Macro Search Path" ../src
project set "Map Effort Level" High
project set "Perform Timing-Driven Packing and Placement" 1
project set "Place & Route Effort Level (Overall)" High
# Do not generate the default post place static timing report
project set "generate post-place & route static timing report" false
###############################################################################
# Run the design.
###############################################################################
process run "Implement Design"
puts "Implement design done"
process run "Generate Programming File"
puts "Bit file ready!"
project close
puts "project closed!"
exec ise dice.ise
# exec impact -batch [file join ".." src impact_batch_commands.cmd]
# puts "Board loaded"
Article: 113899Johan Bernsp=E5ng wrote: > I used to believe that ChipScope did not have any impact on the design. > I used to. > > I have two FPGAs communicating on the PCB (LVDS). One of them (called > source here) is doing some signal processing and sends the result to the > destination FPGA. If I probe (with ChipScope) some internal results of > the processing (FFT output) in the source, the data looks fine at the > destination. However, if I remove the probe I get some interesting, but > rather annoying, bit errors in the data received (and probed) at the > destination. > > Before probing at the source I thought this was an issue of signal > integrity on the PCB, but the probing proved me wrong on that point. The > source is a V2000 device and without the probing about 90% of BRAM and > mults are utilized. I would think that by adding a ChipScope core PAR > would have more troubles meeting timing constraints, and consequently > deliver a design more prone to bit errors... > > Maybe delivering the design with ChipScope still in it is my only > choice, but it doesn't feel very good. > > Anyone who have had similar experiences? > > > -- > ----------------------------------------------- > Johan Bernsp=E5ng, xjohbex@xfoix.se > Research engineer > > Swedish Defence Research Agency - FOI > Division of Command & Control Systems > Department of Electronic Warfare Systems > > www.foi.se > > Please remove the x's in the email address if > replying to me personally. > ----------------------------------------------- Yours is not an isolated experience. The company I work for had a similar problem. The design failed, so they inserted chipscope to probe the design. The design miraculously started working - before they even had a chance to use the analyzer. They tried pulling chipscope out, and it failed again. The solution was to ship it with the analyzer in place. No one knows why it works, which is a bit freaky, but it does. I would note that this was before my time - so I don't know the particulars. I would suspect marginal timing is at fault. Inserting chipscope physically alters the P&R, and may inadvertantly improve timing, pushing marginal timing just enough to be stable.
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