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Although there are other considerations in choosing an FPGA vendor, support is one of those things to consider. Perhaps you should consider suppliers other than brand X. KJ (not representing any FPGA suppliers)Article: 110476
Correction to earlier post. The 'read_data' signal on entity
'Peripheral2' should be an 'out', not 'in'. Corrected entity is shown
below.
entity Peripheral2 is port(
.... -- Here you would have the existing Avalon interface signals to
talk to your Nios
chip_select: in std_logic;
read: in std_logic;
read_data: out std_logic_vector(7 downto 0));
end Peripheral2
KJ
Article: 110477Isaac Bosompem wrote: > Hi guys, > > I am currently in the process of looking for an internship position > that will potentially start in May and end on Sept the following yr (16 > months, but can be 12 months or 8 months). Now I am not asking you guys > to do anything at all really. I am living in the Toronto, Ontario, > Canada area and would like to stay there since I don't think I could > stomach the costs of relocating temporarily (that is if I manage to > secure a position, also its not fun living off Kraft Dinner either!). Not sure how far this is from your place, but maybe something: http://www.nortel.com/corporate/global/namerica/canada/ottawa.html Cheers, GuenterArticle: 110478
David Brown wrote: > jacko wrote: > > Henry Wong wrote: > >> jacko wrote: > >>> hi > >>> > >>> got the tester of model sim from altera, but it seem even though i set > >>> the environment var from the system control panel, it don't appear > >>> hence con not find file. this is both quartus II which has other > >>> methods so no problem, and modelsim which does not find any environment > >>> variable. > >>> > >>> don't work from command.exe either. > >>> > >>> any help would be appreciated. > >>> > >>> cheers > >>> > >> If this is on Windows, I believe the syntax is > >> > >> echo %LM_LICENSE_FILE% > >> > >> Also note that at least on my system, it's spelled "licenSe". > >> > >> Not sure if this helps. > > > > got the echo working using % but still no luck finding it even with the > > S. it's definatly there. > > > > Use "set" from a command prompt to view all the environment variables in > windows. > > Also note that if you change an environment variable in the control > panel, it only affects programs started after the change. If you open a > command prompt, then make the change, you will not see the effect in the > opened prompt - you need to open a new prompt. done it though ctl panel, must have started model sim 3 times now and it no find, and quartus II does noit either, does it need a reboot??Article: 110479
So I guessed that the announce was for today!! :-P Peter Alfke wrote: > Nobody would make a major product announcement on Friday the > thirteenth... ;-) > Peter Alfke > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > GaLaKtIkUs=99 wrote: > > Most onnounces are made by Xilinx on monday, perhaps next monday? > > > > Antti wrote: > > > Antti schrieb: > > > > > > > http://www.sierraic.com/pnresults.asp?part=3DXC5VLX50T1FF1136CES > > > > > > > > there is status "available" - and full order code as well ! > > > > > > > > surprisingly Xilinx website doesnt even list device codes for V5LX(= T) > > > > devices yet. > > > > > > > > to what I understand all T parts (LXT, SXT and FXT) have 4 TEMACs a= nd 1 > > > > PCIe MAC > > > > > > > > Antti > > > > > > !? virtex-5 LXT PCIe has passed PCISIG compliance testing as well !! > > > see here > > > > > > http://www.pcisig.com/developers/compliance_program/integrators_list/= pcie/ > > > > > > so I assume the parts are actually obtainable already? > > >=20 > > > AnttiArticle: 110480
All, I posted that quote because it actually did (but very poorly, I agree) state that after the device is configured, the pins assume their new configured standards, and states. The tech answer is slightly better written, but is goofy as to say "most" or "almost all" which is pretty useless (just poor writing). The issue is that since the BSDL file is only accurate before configuration, there is a "recommendation" NOT to use boundary scan after configuration, because you need to then create a design specific BSDL file to use any of the JTAG scan software tools out there. And, since we don't have software to do that, we just say "don't do that" rather than explain why. Peter and I will see about rewriting this so it makes better sense. In no way does my post suggest that you 'RTFM': rather, I spend a lot of time to search for information, and post where I found it. Just because I read very fast in no way suggests that I think you could have, or should have, found this information. Again, please do not put words in my mouth! I still have no idea if this is the "answer" to the "question" Colin posed originally. AustinArticle: 110481
Austin Lesea wrote: > All, > > I posted that quote because it actually did (but very poorly, I agree) > state that after the device is configured, the pins assume their new > configured standards, and states. > > The tech answer is slightly better written, but is goofy as to say > "most" or "almost all" which is pretty useless (just poor writing). > > The issue is that since the BSDL file is only accurate before > configuration, there is a "recommendation" NOT to use boundary scan > after configuration, because you need to then create a design specific > BSDL file to use any of the JTAG scan software tools out there. And, > since we don't have software to do that, we just say "don't do that" > rather than explain why. Err Austin, you do have a tool to do that, it is called BSDLANNO.exe and comes as standard with webpack. See previous posts, you give it the output of your design and the original BSDL file and it creates a bsdl that reflects your programmed CPLD. My original support question was, will pins that are functionally SSTL output only, be SSTL input during JTAG, to be told that once functionally an output then its only an output for jtag. I then disproved that by creating a pinA <= pin B design and looked at the new BSDL (which used my pin names so I'm happy with how I'm driving bsdlanno). So I think that coolrunner II is included in "most" but your support line doesn't yet agree. I'm sorry if I've communicated badly, my mind obviously works in a simillar way to Rickmans rather than yours :-) and this forum works on goodwill rather than expecting people to read reams of typing I obviously got the balance wrong. Interestingly there is a jtag usenet group but all the posts are in chinese which I guess reflects that western engineers know how to create great fpga IP and asians know how to manufacture them. Colin (from the UK) > > Peter and I will see about rewriting this so it makes better sense. > > In no way does my post suggest that you 'RTFM': rather, I spend a lot > of time to search for information, and post where I found it. Just > because I read very fast in no way suggests that I think you could have, > or should have, found this information. Again, please do not put words > in my mouth! > > I still have no idea if this is the "answer" to the "question" Colin > posed originally. > > AustinArticle: 110482
Instead of using the environment variable, try renaming the license file "license.dat" and place in it the directory c:\flexlm. My purchased version of Modelsim, which had worked for months, suddenly quit working even though the environment variable and license file were properly set. Making this changed fixed it. Remember, Mentor doesn't really want you to run their tool, they just want you to buy it :) On Sun, 15 Oct 2006 11:45:29 -0700, jacko wrote: > hi > > got the tester of model sim from altera, but it seem even though i set > the environment var from the system control panel, it don't appear > hence con not find file. this is both quartus II which has other > methods so no problem, and modelsim which does not find any environment > variable. > > don't work from command.exe either. > > any help would be appreciated. > > cheersArticle: 110483
I realized the the net adc_clk was the input to the DCM, so I switched to the clk0 output of the DCM and it prevented the aforementioned error. Oops! Thanks, that did the trick. -Brandon Brandon Jasionowski wrote: > John, > > I tried what you suggested, but I'm not having much luck because of > some restrictions on TNM u sage and DCMs. The TNM_NET I specified feeds > into a DCM_BASE, so I need it to derive all the child clocks. > > Page 279 of the cgd says, > <SNIP> > The TNM is pushed through the CLKDLL or DCM (as described below) only > if the following conditions are met: > =B7 The TNM group is used in exactly one PERIOD specification. > =B7 The TNM group is not used in any FROM-TO or OFFSET specifications. > =B7 The TNM group is not referenced in any user group definition. > If any of the above conditions are not met, the TNM is not be pushed > through. > </SNIP> > > I tried the following in my UCF, but it fails. > > <SNIP> > NET "adc_clk" TNM_NET =3D "TG_adc_clk"; > TIMESPEC "TS_adc_clk" =3D PERIOD "TG_adc_clk" 4.0 ns HIGH 50 %; > NET "adc_clk_dcm_clkfx" TNM =3D "TG_logic_clk"; > TIMESPEC "TS_adcclk_to_logicclk" =3D FROM "TG_adc_clk" TO "TG_logic_clk" > TIG; > </SNIP> > > <SNIP> > WARNING:XdmHelpers:793 - The TNM "TG_logic_clk" drives the CLKIN pin of > DCM_ADV > "adc_clkfx_dcm_inst". This TNM cannot be traced through the DCM_ADV > because > it is not used exclusively by one PERIOD specification. This TNM is > used in > the following user groups and/or specifications: > TS_adcclk_to_logicclk=3DFROM TG_adc_clk TO TG_logic_clk TIG > WARNING:XdmHelpers:625 - No instances driven from the following signals > or pins > are valid for inclusion in TNM group "TG_adc_clk". A TNM property on > a pin or > signal marks only the flip-flops, latches and/or RAMs which are > directly or > indirectly driven by that pin or signal. > signal "adc_clk" > WARNING:XdmHelpers:644 - No appropriate elements were found for the TNM > group > "TG_adc_clk". This group has been removed from the design. > ERROR:XdmHelpers:650 - The period specification "TS_adc_clk" is invalid > because > the "TG_adc_clk" group was removed. > ERROR:XdmHelpers:648 - The specification "TS_adcclk_to_logicclk" is > invalid > because its FROM group (TG_adc_clk) was removed. > </SNIP> > > Do I have to manually derived all of the DCM clocks (I have a lot)? > This seems ridiculous! > > Thanks, > -Brandon > > JustJohn wrote: > > On Oct 11, 8:03 am, "Brandon Jasionowski" <killerhe...@gmail.com> > > wrote: > > > > > Why is ISE ignoring my constraint? > > > > Your statement: > > > > > The first two nets listed are assigned to a timing name belonging to > > > paths that are asychronous to another clock. > > > > may show a mis-understanding of how the TNM and TNM_NET constraints > > form timing groups (not "timing names", the name is just a label to > > refer to the group). Timing groups are composed of instances of FFs, > > memories, and other synchronous devices, they are _not_ composed of > > nets. TNM_NET fans _forward_ from the named net and collects any > > devices whose inputs are reached either directly or combinatorically > > from that net. > > > > To get a clue what's happening, use Timing Analyzer to take a look at > > the timing groups that are formed by your grouping constraints: > > > > > NET "ctrl1_clr" TNM_NET =3D "TN_ctrl_clr"; > > > NET "ctrl2_clr" TNM_NET =3D "TN_ctrl_clr"; > > > NET "sync_drpp_clr_inst/sync_r2<0>" TNM_NET =3D "TN_sync_drpp_clr"; > > > NET "sync_drpp_clr_inst/sync_r2<1>" TNM_NET =3D "TN_sync_drpp_clr"; > > > > Look at the group "TN_ctrl_clr". > > Does it contain "Source: ctrl2_ins/curr_st_FFd1 (FF)"? > > Look at the group "TN_sync_drpp_clr". > > Does it contain "Destination: sync_drpp_clr_inst/sync_r1_1 (FF)"? > > (I'm guessing no on both...) > > > > If the groups don't contain the source and destination devices for the > > timing path you want to ignore, the TIG constraint is not applied (or > > worse, applied to a different set of sources/destinations that you did > > not intend). > > > > Three possible suggestions are: > > 1) If you want to ignore _all_ cross clock domain timing, you easily do > > that with a TIG applied from your CLK1 group to your CLK2 group: > > NET "adc_clk_dcm_clk0" TNM_NET "TG_Clk1"; > > NET "adc_clk_dcm_clkfx" TNM_NET "TG_Clk2"; > > TIMESPEC "TS_Clk1_to_Clk2" =3D FROM "TG_Clk1" TO "TG_Clk2" TIG; > > (or whatever names you want to use for your TIMEGROUPsand TIMESPEC.) > > I don't particularly like this though, it may hinder Place/Route by > > allowing domain crossing nets to be excessively long, thus getting in > > the way of more critical nets. It may be nicer to simply use a small > > but achievable value: > > TIMESPEC "TS_Clk1_to_Clk2" =3D FROM "TG_Clk1" TO "TG_Clk2" 2 ns; > > (or whatever value works for you). > > > > 2) Closer to what you seem to want to do, use TPTHRU: > > > > NET "ctrl1_clr" TPTHRU=3D TH_clr; > > NET "ctrl2_clr" TPTHRU=3D TH_clr; > > and either: > > TIMESPEC "TS_Thru_clr" =3D FROM "TG_Clk1" THRU "TH_clr" TO "TG_Clk2" TI= G; > > or possibly better for P/R: > > TIMESPEC "TS_Thru_clr" =3D FROM "TG_Clk1" THRU "TH_clr" TO "TG_Clk2" 2 > > ns; > > > > 3) To pick out only the particular paths that you show failing, use the > > instance grouping constraint: > > INST "ctrl2_ins/curr_st_FFd1" TNM "TG_Src1"; > > INST "sync_drpp_clr_inst/sync_r1_1" TNM "TG_Dst1"; > > TIMESPEC "TS_Src1_to_Dst1" =3D FROM "TG_Src1" TO "TG_Dst1" TIG; > > or > > TIMESPEC "TS_Src1_to_Dst1" =3D FROM "TG_Src1" TO "TG_Dst1" 2 ns; > > > > Hope one of these is of some help. > > Regards, > > John > > > > > I've been performing post-map static timing analysis and have noticed > > > that my TIG UCF constraint is being ignored for some reason. Here is > > > what I have: > > > > > > <SNIP> > > > ## TIG > > > NET "ctrl1_clr" TNM_NET =3D "TN_ctrl_clr"; > > > NET "ctrl2_clr" TNM_NET =3D "TN_ctrl_clr"; > > > NET "sync_drpp_clr_inst/sync_r2<0>" TNM_NET =3D "TN_sync_drpp_clr"; > > > NET "sync_drpp_clr_inst/sync_r2<1>" TNM_NET =3D "TN_sync_drpp_clr"; > > > TIMESPEC "TS_TIG_clr2synch" =3D FROM "TN_ctrl_clr" TO "TN_sync_drpp_c= lr" > > > TIG; > > > </SNIP> > > > > > > The first two nets listed are assigned to a timing name belonging to > > > paths that are asychronous to another clock. This clock drives > > > registered ports of an instance (synchronization circuit) with port > > > name sync_r2(1:0). Normally I would edit the UCF manually, but it > > > absorbed some of the signal names, so instead I used the constraint > > > tool to generate the above. > > > > > > When I run timing I get the following: > > > <SNIP> > > > WARNING:Timing:3223 - Timing constraint PATH "TS_TIG_clr2synch_path" > > > TIG; > > > ignored during timing analysis. > > > </SNIP> > > > > > > Here is one of the timing errors from the post-map static timing > > > analyzer: > > > <SNIP> > > > Timing constraint: TS_adc_clk_dcm_clkfx =3D PERIOD TIMEGRP > > > "adc_clk_dcm_clkfx" TS_adc_clk / 0.7 > > > HIGH 50%; > > > > > > 278920 items analyzed, 4 timing errors detected. (4 setup errors, 0 > > > hold errors) > > > Minimum period is 8.415ns. > > > ---------------------------------------------------------------------= ------=AD----- > > > Slack: -0.270ns (requirement - (data path - clock pa= th > > > skew + uncertainty)) > > > Source: ctrl2_ins/curr_st_FFd1 (FF) > > > Destination: sync_drpp_clr_inst/sync_r1_1 (FF) > > > Requirement: 0.571ns > > > Data Path Delay: 0.590ns (Levels of Logic =3D 1) > > > Clock Path Skew: 0.000ns > > > Source Clock: adc_clk_dcm_clk0_bufg rising at 28.000ns > > > Destination Clock: adc_clk_dcm_clkfx_bufg rising at 28.571ns > > > Clock Uncertainty: 0.251ns > > > Timing Improvement Wizard > > > Data Path: ctrl2_ins/curr_st_FFd1 to sync_drpp_clr_inst/sync_r1_1 > > > Delay type Delay(ns) Logical Resource(s) > > > ---------------------------- ------------------- > > > Tcko 0.291 ctrl2_ins/curr_st_FFd1 > > > net (fanout=3D22) e 0.100 ctrl2_ins/curr_st_FFd1 > > > Tfck 0.199 ctrl2_ins/curr_st_Out11 > > > sync_drpp_clr_inst/sync_r1_1 > > > ---------------------------- --------------------------- > > > Total 0.590ns (0.490ns logic, 0.100ns route) > > > (83.1% logic, 16.9% route) > > > > > > </SNIP> > > > > > > Why is ISE ignoring my constraint? How am I supposed to know what my > > > true worst path is if I can't eliminate this timing error? > > >=20 > > > Thanks, > > > -BrandonArticle: 110484
Generally speaking, a scoreboard is a mechanism for tracking which tests and which requirements have been run/verified. For example, a testbench may have multiple tests which verify multiple requirements (not often in 1:1 correspondence either). A portion of the overall testbench is to capture and record the success/failure of each test, and/or requirement verified. This is the purpose of the scoreboard. Another aspect of good verification is to segregate interface specification verification from performance specification verification. For example you could create a protocol checker that monitors an interface and verifies that each transaction on that interface is per the protocol on the interface. But to keep it portable, that protocol checker would not verify specific contents of transactions, that is done elsewhere (so the content checker can be portable across different interfaces too). Andy Davy wrote: > Hi all, > > IMHO, there is something compare the golden output and DUT output in > testbench (I call it Checker). But in verification book, there is both > Scoreboard and Checker. Are they similar? > > Please recommend some reading on it.Thanks! > > Best regards, > DavyArticle: 110485
Hey every1, I just created a memory with Xilinx coregen and it uses the CAM_V4_0.v xilinx file. When i try synthesise everything with Leonardo Spectrum it errors out: "C:/Xilinx/verilog/src/XilinxCoreLib/CAM_V4_0.v", line 671: Warning, system task enable ignored for synthesis "C:/Xilinx/verilog/src/XilinxCoreLib/CAM_V4_0.v", line 700: Warning, initial statement not supported. Ignored "C:/Xilinx/verilog/src/XilinxCoreLib/CAM_V4_0.v", line 769: Error, Before all asynchronous conditions have been tested, checking for other expressions is not allowed When i looked into CAM_V4_0).v it looks like a behavioural model and has lots of things that wont synthesise. Does the coregen have any options for synthesisable output? Or any1 got any ideas - am i going about this the wrong way? This is my first attempt at using the coregen tool. Cheers for any feedback, Rob.Article: 110486
hi i'm using a microblaze system with lwip raw api. i'm trying to get the sample code to work but it's not working. my guess is that the timer isn't working correctly. if you click on the link you can see the code. if you look at the "void mytimer_int_handler (void* baseaddr_p)" i was wondering if that function doesn't have to be register with an interrupt somewhere? www.pfeilheim.sth.ac.at/xilinx/echo_main.c can anybody give me a hint here? thanksArticle: 110487
Al wrote:
> I use emacs to edit vhdl, synplify to
> synthesize it and Modelsim to simulate it and Designer to make the P&R
> and to generate the back-annotate vhdl for the post-layout simulation.
I would recommend this order:
1. emacs+vcom for entry and syntax check of uut and
functional testbench code.
define a vhdl-mode project for the source directory.
2. Modelsim to debug uut and functional testbench code.
3. Run synplify on the debugged uut source and fix synthesis errors.
4. Run libero place+route on the synplify netlist and
check static timing.
A post-layout sim is not always needed for a synchronous design.
This keeps libero out of the loop until it is actually needed.
-- Mike Treseler
Article: 110488
robquigley@gmail.com wrote:
> I just created a memory with Xilinx coregen and it uses the CAM_V4_0.v
> xilinx file.
>
> When i try synthesise everything with Leonardo Spectrum it errors out:
Leo needs to see either a synthesis code template
or a black box instance.
-- Mike Treseler
Article: 110489<pbdelete@spamnuke.ludd.luthdelete.se.invalid> wrote in message news:45334a2d$0$487$cc7c7865@news.luth.se... > devices <me@home> wrote: > >Is it possible to grab video or still frames directly into a NAND flash? Is > >it a common practise or are such devices still too slow? > > Consider that many digital cameras use flash "discs" and handle > 640x480 @ 30fps (2MiB/s mjpg canon s2is). So it is possible. > I'm not sure digital cameras store data directly into flash discs. They might use some SDRAM as buffers. And if they do image processing they can't avoid sdram, unless the processing is done by hardware. So this is my concern. Anyway i would store the raw image data directly into flash and no image processing would pose any overhead. Maybe a small FIFO could reduce the "timing gap" if any...Article: 110490
Greetings How is this supposed to work ? I have installed webpack for Linux on my FC5 box, and that part is working. I can compile my VHDL files, generate fitterrepports etc. But the following does'nt work: "Assign Package Pins" When i click it, it says >>Started : "Assign Package Pins".<< But nothing happens. I think that the executable is a file name "pace", and when i run pace in a console window i get the error /opt/Xilinx/bin/lin/_pace: error while loading shared libraries: libXm.so.3: cannot open shared object file: No such file or directory I have installed openmotif, which should contain the file in question, but without any luck. Then i have tried executing different files in the /opt/Xilinx/bin/lin/ directory. (create_sdc, arwz, qtconfig) and a couple others all of them generates errors about missing libX?????.so files that actually are located in the same directory. How do i go about narrowing down the problem and getting it to work ? Henrik From paulu@sx4all.nl Mon Oct 16 12:21:30 2006 Path: newssvr25.news.prodigy.net!newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed.freenet.de!feeder.news-service.com!newsgate.cistron.nl!xs4all!transit3.news.xs4all.nl!post2.news.xs4all.nl!newszilla.xs4all.nl!not-for-mail Message-Id: <4533dbba$0$2574$e4fe514c@dreader16.news.xs4all.nl> From: Paul Uiterlinden <paulu@sx4all.nl> Subject: Re: Synopsys's VMM and Mentor's AVM Newsgroups: comp.lang.verilog,comp.lang.vhdl,comp.arch.fpga Date: Mon, 16 Oct 2006 21:21:30 +0200 References: <1160967443.885458.176120@e3g2000cwe.googlegroups.com> User-Agent: KNode/0.10.1 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 39 NNTP-Posting-Host: 213.84.176.29 X-Trace: 1161026490 dreader16.news.xs4all.nl 2574 213.84.176.29:10166 Xref: prodigy.net comp.lang.verilog:34031 comp.lang.vhdl:66857 comp.arch.fpga:121436 Davy wrote: > Hi all, > > I want to use SystemVerilog to construct next generation of my > testbench. > > And I found Synopsys provide VMM while Mentor provide AVM. Anyone > can give some comment on these two methodology? Or are they similar? A comparison of AVM and VMM in Verification Horizons: http://lyris.mentor-info.com/t/5001/4363723/7325/1846/ PDF version: http://lyris.mentor-info.com/t/5001/4363723/7330/1851/ Four articles in the EETIMES on the SystemVerilog reference verification methodology: http://www.eetimes.com/news/design/showArticle.jhtml?articleID=183702807 http://www.eetimes.com/news/design/showArticle.jhtml?articleID=187001913 http://www.eetimes.com/news/design/showArticle.jhtml?articleID=188703275 http://www.eetimes.com/news/design/showArticle.jhtml?articleID=192501500 The first is by Mentor, the second by Synopsys (IIRC). Both of course with their own biases. > I don't know if Synopsys's VMM is open document and open source > code. As far as I know the VMM book is not an open document: http://www.vmm-sv.com/ The AVM cookbook clearly is. The same goes for VMM and AVM itself. AVM is opensource, VMM source is heavily licensed (word choice from Verification Horizons). -- Paul.Article: 110491
Jim Granville a écrit : > and not only that, if you wanted the FPGA to change CLk speed any > earlier ( ie before the bitstream loads ) it would need to be > clairvoyant ;) Now *that* would be a real technology breakthrough ! NicolasArticle: 110492
> If you need large amounts of on-chip memory or multi gigabit > communications, the new Lattice ECP2M series warrants serious consideration. fyi, the largest LatticeECP2M device has 95K LUTs, 5.3Mb Block RAM, and 16 SERDES channels, operating up to 3.125Gbps. http://www.latticesemi.com/products/fpga/ecp2/index.cfm hope this helps. Regards, Bart Borosky, LatticeArticle: 110493
Hmmm, first in industry with built-in PCI-express? Lattice SCM devices have built-in PCI express, have had since Feb (along with a boat-load of other stuff too). 100mW per channel, finally catching up with Altera and Lattice... S3A may have built-in Flash...seen that before too. It's kinda fun watching Xilinx playing catch-up.... ;) Antti wrote: > Antti schrieb: > > > http://www.xilinx.com/prs_rls/2006/silicon_vir/0696v5lxt.htm > > > > already pricing given for 1000qty not bad at all. > > > > unfortunatly the LXT related user guides > > ug194 EMAC > > ug196 GTP > > ug197 PCIe > > > > are all deadlinks at the moment but hopefully those documents become > > available shortly. > > > > new eval boards (besides ML501) are > > > > ML505 - allows PCIe testing > > ML523 - GTP characterization board > > ML555 - 8x PCIe card > > > > GTP has OOB support for PCIe/SATA and supports spread spectrum clocking > > as well. > > > > Antti > > correction ug194 and ug196 are already available (appearead 6 minutes > after the post), so the only missing one is the PCIe UG > > myselfArticle: 110494
Is anyone running ISE on an Intel based Macintosh? I'm considering a MacPro with dual Core 2 Duo processors, running ISE on XP Pro. --- Joe Samson Pixel VelocityArticle: 110495
Built-in PCIe or built-in SERDES? "ddrinkard" <dale.drinkard@gmail.com> wrote in message news:1161035523.262190.222240@k70g2000cwa.googlegroups.com... > Hmmm, first in industry with built-in PCI-express? Lattice SCM devices > have built-in PCI express, have had since Feb (along with a boat-load > of other stuff too). 100mW per channel, finally catching up with > Altera and Lattice... S3A may have built-in Flash...seen that before > too. It's kinda fun watching Xilinx playing catch-up.... ;)Article: 110496
dd, Hardened PCIe (in V5). Not a core. Don't see any hardened PCIe on Lattice website. Am I missing something? Not that the Lattice SC products are not nice, they are, and I have acknowledged that a long time ago. But I don't see any hardened PCIe core(s). Is this something they are keeping secret? Austin ddrinkard wrote: > Hmmm, first in industry with built-in PCI-express? Lattice SCM devices > have built-in PCI express, have had since Feb (along with a boat-load > of other stuff too). 100mW per channel, finally catching up with > Altera and Lattice... S3A may have built-in Flash...seen that before > too. It's kinda fun watching Xilinx playing catch-up.... ;) > > > Antti wrote: >> Antti schrieb: >> >>> http://www.xilinx.com/prs_rls/2006/silicon_vir/0696v5lxt.htm >>> >>> already pricing given for 1000qty not bad at all. >>> >>> unfortunatly the LXT related user guides >>> ug194 EMAC >>> ug196 GTP >>> ug197 PCIe >>> >>> are all deadlinks at the moment but hopefully those documents become >>> available shortly. >>> >>> new eval boards (besides ML501) are >>> >>> ML505 - allows PCIe testing >>> ML523 - GTP characterization board >>> ML555 - 8x PCIe card >>> >>> GTP has OOB support for PCIe/SATA and supports spread spectrum clocking >>> as well. >>> >>> Antti >> correction ug194 and ug196 are already available (appearead 6 minutes >> after the post), so the only missing one is the PCIe UG >> >> myself >Article: 110497
On Oct 16, 8:22 am, "Brandon Jasionowski" <killerhe...@gmail.com> wrote: > I realized the the net adc_clk was the input to the DCM, so I switched > to the clk0 output of the DCM and it prevented the aforementioned > error. Oops! > > Thanks, that did the trick. > > -Brandon I was going to reply that if you have a complex design with lots of cross clock domain timing to worry about, then you're going to have complicated timing constraints that no automated system is going to be able to work out for you. But it looks like you've found your solution. Great, and thanks for letting us know (it was nagging at me)!Article: 110498
>How is this supposed to work ? >I have installed webpack for Linux on my FC5 box, and that part is working. >I can compile my VHDL files, generate fitterrepports etc. >But the following does'nt work: >"Assign Package Pins" >When i click it, it says >>Started : "Assign Package Pins".<< >But nothing happens. >I think that the executable is a file name "pace", and when i run pace in a >console window i get the error >/opt/Xilinx/bin/lin/_pace: error while loading shared libraries: libXm.so.3: >cannot open shared object file: No such file or directory >I have installed openmotif, which should contain the file in question, but >without any luck. >Then i have tried executing different files in the /opt/Xilinx/bin/lin/ >directory. (create_sdc, arwz, qtconfig) and a couple others all of them >generates errors about missing libX?????.so files that actually are located >in the same directory. >How do i go about narrowing down the problem and getting it to work ? Check ldconfig + setenv LD_LIBRARY_PATH ,it might help. I have run it under FreeBSD.org myself without major problems.Article: 110499
On Mon, 16 Oct 2006 20:14:07 +0200, Henrik Pedersen wrote: > Greetings > > How is this supposed to work ? > > I have installed webpack for Linux on my FC5 box, and that part is working. > I can compile my VHDL files, generate fitterrepports etc. > But the following does'nt work: > > "Assign Package Pins" > When i click it, it says >>Started : "Assign Package Pins".<< > But nothing happens. > I think that the executable is a file name "pace", and when i run pace in a > console window i get the error > /opt/Xilinx/bin/lin/_pace: error while loading shared libraries: libXm.so.3: > cannot open shared object file: No such file or directory > I have installed openmotif, which should contain the file in question, but > without any luck. > > Then i have tried executing different files in the /opt/Xilinx/bin/lin/ > directory. (create_sdc, arwz, qtconfig) and a couple others all of them > generates errors about missing libX?????.so files that actually are located > in the same directory. > > How do i go about narrowing down the problem and getting it to work ? > > Henrik Make sure you have the compatibility libraries loaded. The Xilinx tools are targeted at RHEL which is way behind Fedora so you need to load the compatibility libraries.
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