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1) The sample period is 1/clock rate. If you put the sample period as 10 ns in the System Generator token, you should provide a 100 MHz clock to the design generated by Sysgen. 2) The generated design will automatically implement the different sampling rates that appear in the Simulink model. This is done by using the CE (clock enable) pin on devices within the generated model. As long as the design successfully generates, the generated model will have taken care of sample rate changing.Article: 110426
"Peter Alfke" <alfke@sbcglobal.net> schrieb im Newsbeitrag news:1160928029.998208.36480@e3g2000cwe.googlegroups.com... > Antti, > As I write this, V5LXT (and SystemMonitor) has not yet been officially > announced or released. But, hold your breath, it will be "soon". > As I mentioned once before, a Product Announcement is a rutual dance, > involving not only Xilinx, but also the press. And they are obsessed > about the "virginity" of the information. So we have to keep mum. > But soon we can discuss this openly. > I am glad you got the ML501 board faster than anybody thought. > But it has an 'LX, not LXT device on it. > We will look at the other points in your posting. > Peter > smiling here - I was excited about sysmon in Virtex-4 so it was obviously the first thing I wanted to check out on Virtex-5, I was almost to try out the V-5 sysmon based on the information from Virtex-4 datasheet and trial and error, but decided to wait a little (but I am really bad at waiting!) from what I understand it is available in LX50 (except the lack of documentation). regarding the CRC32/CRC64 I should have double checked they are only in T parts, so I assume they will all be documented with the official release of LXT devices. I am just wondering - 1 the LX parts are shipping, but full datasheets are not available 2 LXT parts seem to orderable, but are not announced 3 LXT parts have passed PCISIG PCIe compliance there seems to be lot of things going on, but very little exposure. hm.. I hope thist time there will be a PCIe capable board made by Xilinx/SEG the competitor Lattice has already 4 different boards (2 different FPGA families) with PCIe capability. Sure there are some 3rd party Xilinx/PCIe boads available, but if Xilinx/SEG made board is available I will almost sure prefer the Xilinx direct board. Antti has to go make panncakes now.Article: 110427
David Ashley wrote: > Antti wrote: > >>unverified and only has the important FX2 <> CPLD connections >> >>http://rapidshare.de/files/36822701/xil_jtag.pdf.html >> >>Antti >> > > > Antti, > > I'm really shocked you would post a URL like this > to this newsgroup. I urge everyone to avoid > visiting this ridiculous site. Is there any "administrator" who can remove the post? > > -Dave -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 110428
Is it possible to grab video or still frames directly into a NAND flash? Is it a common practise or are such devices still too slow?Article: 110429
Avion wrote: > i have read the edif file but i am not sure what is top level in it. is > there any document which expalins edif file format? i guess the word > "design" indicates what is top level. i found this at the end of the > file : > " (design ROOT > (cellRef xr16vx_1k > (libraryRef xr16vx_1k))) > so i renamed the edif file to ROOT.edf and also changed it in the vhdl > file where i instantiated this. but still i am getting the same error. > how can i find the top level entity name and input and out put ports > from edif file while opening it in text editor? > In the edif files I have used, above the "design ROOT" section (which does indicate the top level), there should be a "cell ROOT" section, and within that an "interface" section which will list the ports.Article: 110430
David Ashley wrote: > Antti wrote: > > unverified and only has the important FX2 <> CPLD connections > > > > http://rapidshare.de/files/36822701/xil_jtag.pdf.html > > > > Antti > > > > Antti, > > I'm really shocked you would post a URL like this > to this newsgroup. I urge everyone to avoid > visiting this ridiculous site. > > -Dave On the contrary, this is not spam. It is on topic (fpga's) and isn't selling anything. I am curious. Do you object to: 1. Posting schematics for download? 2. Charging a fee for downloads (there is a free option)? 3. A website that just sells disk space and bandwidth? 4. The advertisement on the website? 5. Reverse engineering? Alan NishiokaArticle: 110431
Alan Nishioka wrote: > David Ashley wrote: > >>Antti wrote: >> >>>unverified and only has the important FX2 <> CPLD connections >>> >>>http://rapidshare.de/files/36822701/xil_jtag.pdf.html >>> >>>Antti >>> >> >>Antti, >> >>I'm really shocked you would post a URL like this >>to this newsgroup. I urge everyone to avoid >>visiting this ridiculous site. >> >>-Dave > > > On the contrary, this is not spam. It is on topic (fpga's) and isn't > selling anything. > > I am curious. Do you object to: > 1. Posting schematics for download? > 2. Charging a fee for downloads (there is a free option)? > 3. A website that just sells disk space and bandwidth? > 4. The advertisement on the website? > 5. Reverse engineering? > > Alan Nishioka > That site just really bugged me. So much stuff on it, and the thing you want is like finding a needle in a haystack. Then you figure out you've got to enter a 3 letter code based on a picture, and when you do that... it says "sorry, try again." I posted the complaint after the first failed attempt. I tried a 2nd time and got the file. I think my complaint isn't any of 1-5 specifically, it's just how this particular site functions. -DaveArticle: 110432
> > Antti, > > > > I'm really shocked you would post a URL like this > > to this newsgroup. I urge everyone to avoid > > visiting this ridiculous site. > > > > -Dave > > On the contrary, this is not spam. It is on topic (fpga's) and isn't > selling anything. > > I am curious. Do you object to: > 1. Posting schematics for download? > 2. Charging a fee for downloads (there is a free option)? > 3. A website that just sells disk space and bandwidth? > 4. The advertisement on the website? > 5. Reverse engineering? > > Alan Nishioka Hi Alan, first :) - tnx. I am very technical person, so the SPAM thing didnt even occour on my mind. really. I had found something that I think is of interest - the schematic is essentially what is missing in the Spartan3e starterkit schematics, e.g. it is what belongs on that empty page there. To what i know that is of interest to several people who want to use the FX2 on s3esk board. There is some reasoning for the style of initial posting, and secondly I was really busy today with tasks like scarving ships out of skin of wood and making panncakes. So i had not much time. The children are in listening mode now (evning fairy tale reading) so here is the direct and hassle free download link to the same schematic. http://www.antti-brain.com/xil_jtag.pdf Antti PS the link referenced in the original posting is auto-deleting in 30 days last download.Article: 110433
In article <WuWdnSRMFN1bxq_YnZ2dnUVZ_oadnZ2d@adelphia.com>,
David Ashley <dash@nowhere.net.dont.email.me> writes:
|> Antti wrote:
|> > unverified and only has the important FX2 <> CPLD connections
|> >
|> > http://rapidshare.de/files/36822701/xil_jtag.pdf.html
|> >
|> > Antti
|> >
|>
|> Antti,
|>
|> I'm really shocked you would post a URL like this
|> to this newsgroup. I urge everyone to avoid
|> visiting this ridiculous site.
You haven't understood the purpose of this site. Maybe because it's only in
German... It is NO spam! Rapidshare is a sort of "free web space" provider and
quite popular.
To download the file, you have to choose the "Free"-button at the bottom, enter
the chars you see in the funny image, click "Download" and you get the file. Not
really convenient, but for usable for a quick file exchange without an own server.
BTW: The file is really a PDF with a schematic...
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 110434there is no other mention of ROOT in the entire file and above "design ROOT" is the following cell: (cell (rename xr16vx_1k "xr16vx_1k") and it does have all the ports which i got after converting ngd to vhdl file. does not the line "cellRef xr16vx_1k" inside design ROOT block indicate the top level entity? should i rename the ROOT to xr16vx_1k in edf file? is there detailed description of edif file format available somewhere? Duane Clark wrote: > Avion wrote: > > i have read the edif file but i am not sure what is top level in it. is > > there any document which expalins edif file format? i guess the word > > "design" indicates what is top level. i found this at the end of the > > file : > > " (design ROOT > > (cellRef xr16vx_1k > > (libraryRef xr16vx_1k))) > > so i renamed the edif file to ROOT.edf and also changed it in the vhdl > > file where i instantiated this. but still i am getting the same error. > > how can i find the top level entity name and input and out put ports > > from edif file while opening it in text editor? > > > > In the edif files I have used, above the "design ROOT" section (which > does indicate the top level), there should be a "cell ROOT" section, and > within that an "interface" section which will list the ports.Article: 110435
hi got the tester of model sim from altera, but it seem even though i set the environment var from the system control panel, it don't appear hence con not find file. this is both quartus II which has other methods so no problem, and modelsim which does not find any environment variable. don't work from command.exe either. any help would be appreciated. cheersArticle: 110436
Peter Alfke wrote: > It obviously has to be this way, so that the beginning of the bitstream > can be loaded in the least demanding way. > Pter Alfke, Xilinx and not only that, if you wanted the FPGA to change CLk speed any earlier ( ie before the bitstream loads ) it would need to be clairvoyant ;) -jgArticle: 110437
Hi it seems that full MicroBlaze ver 5 uClinux support is now there - required is GCC toolchain based on EDK 8.2 (to have PVR support in compiler) "old" toolchain binaries are now vanished from queensland university and the binaries available from petalogix are outdated (EDK 8.1 based) but the VMware player platform referenced in Xilinx XAPP934 has pre-installed microblaze toolchain based on EDK 8.2 so all uclinux images built within can take advantages of the new features in MB v5. There is no other download for the 8.2 release linux binaries known, should be easy to compile from sources though. links http://direct.xilinx.com/bvdocs/appnotes/xapp934.pdf http://direct.xilinx.com/bvdocs/appnotes/xapp730.pdf AnttiArticle: 110438
Kolja Sulimma wrote: > Jim Granville schrieb: > > >> eg I have a Flash-RAM CPLD here, that is appx 200x more Icc during >>Config load, than static icc. To me, that certainly IS significant. > > > But that one is not built in a 65nm technology, right? Why is the process relevent to design selection ? The FPGA vendor chooses what tradeoffs to make, and then release a spec. I design using that spec. If their trade-off's miss the customer's target needs, they miss the sale. > Static sv. dynamic power consumption changed a lot with newer technologies. Of course; and some vendors are more focused on power than others. Actels latest Igloo variant makes for interesting reading http://www.actel.com/images/products/igloo/IGLOO_battery_life_chart.jpg I presume their values are valid, but was interesting to see the PolarPro way down the bottom, and also that Coolrunner II is so poor, nearly as bad as MAX II (for their test conditions). Be interestng to see the SAME test with 98% idle, and 2% run, and even 99.8% idle and 0.2% run. On the portable-power spin front, I do have to smile at Altera's push on the MAX II - their power off/wakeup suggestions look like Diode-Transistor Logic decades old. Seems they hope customers will ignore PCB/Stocking/Placement costs of all those bits.... -jg -jgArticle: 110439
jacko wrote: > hi > > got the tester of model sim from altera, but it seem even though i set > the environment var from the system control panel, it don't appear > hence con not find file. this is both quartus II which has other > methods so no problem, and modelsim which does not find any environment > variable. > > don't work from command.exe either. > > any help would be appreciated. > > cheers > If this is on Windows, I believe the syntax is echo %LM_LICENSE_FILE% Also note that at least on my system, it's spelled "licenSe". Not sure if this helps.Article: 110440
I found: http://www.xilinx.com/xlnx/xil_tt_gettingstarted.jsp?sProduct=JTAG&iLanguageID=1&iCountryID=1 which states: "Boundary Scan tests on Xilinx devices should only be performed after configuration under the following circumstances: -When configuration cannot be prevented -When differential signaling standards are used" So, before configuration, the IO pin will be the default IO standard (LVCMOS12_F), and after configuration, the IO standard will be that as programmed by the configuration. AustinArticle: 110441
Al wrote: > Antti wrote: > > > > things are not always reasonable. > > the libero/designer is just to make people crazy. > > > > use it at the minimum, that is prepare all files > > using some other tools, then port to libero and try to get the > > bitstream file > > minimizing the work you do with libero. > > This is what I usually do, I use emacs to edit vhdl, synplify to > synthesize it and Modelsim to simulate it and Designer to make the P&R > and to generate the back-annotate vhdl for the post-layout simulation. > Unfortunately I'm still not able to use them without the Libero setup, > which configures all the libraries to compile and everything, but it > makes you crazy. > I thought about migrating on something smarter but still don't have > other choices. > All the Libero tools can be used standalone. And this is what I do. It looks like you are missing some setup information. Compare your paths with what you get from your Libero project directory, or post the error message you get. Regards, Daniel Leu Inicore, Inc.Article: 110442
alessandro basili wrote: > Hi Daniel, > > Daniel Leu wrote: > > > > Routing depends on your design structure. Even with high device > > utilization, Designer usually is successful. If routing fails or you > > can't get timing closure, you can try place&route with the "Multiple > > Passes" option. > > I will try it, thanks. Does it have any drawback? Longer runtime. > > > > Certainly. You can export the netlist together with the SDF to perform > > gate-level simulation with effective cell and routing delays. > > > > I thought that this is what the back-annotate does, am I wrong? > I usually do the back-annotate and then do the post-layout simulation > with Model-Sim (unfortunately by the mean of Libero IDE, that I > personally hate, but still didn't have time to make rid of it). > What do you mean by "gate-level simulation"? Yes, this is what I meant. You should be able to run the back-annotated with Modelsim without Libero. Regards, Daniel Leu Inicore, Inc.Article: 110443
Henry Wong wrote: > jacko wrote: > > hi > > > > got the tester of model sim from altera, but it seem even though i set > > the environment var from the system control panel, it don't appear > > hence con not find file. this is both quartus II which has other > > methods so no problem, and modelsim which does not find any environment > > variable. > > > > don't work from command.exe either. > > > > any help would be appreciated. > > > > cheers > > > > If this is on Windows, I believe the syntax is > > echo %LM_LICENSE_FILE% > > Also note that at least on my system, it's spelled "licenSe". > > Not sure if this helps. got the echo working using % but still no luck finding it even with the S. it's definatly there.Article: 110444
Hans wrote: > Hi Davy, > > The AVM cookbook from Mentor describes these terms, you can download a free > copy from: > > http://www.mentor.com/products/fv/_3b715c/cb_dll.cfm [snip] Hi Hans, This cookbook is so good, thanks a lot! Best regards, Davy > > Hans > www.ht-lab.com > > > "Davy" <zhushenli@gmail.com> wrote in message > news:1160799509.696951.204680@b28g2000cwb.googlegroups.com... > > Hi all, > > > > IMHO, there is something compare the golden output and DUT output in > > testbench (I call it Checker). But in verification book, there is both > > Scoreboard and Checker. Are they similar? > > > > Please recommend some reading on it.Thanks! > > > > Best regards, > > Davy > >Article: 110445
Thank you..I found that Avnet willing to sell its board to me. -kunil zyan wrote: > Hi, > > You can try to buy from Avnet <http://www.avnet.com/>Article: 110446
Hi all, I want to use SystemVerilog to construct next generation of my testbench. And I found Synopsys provide VMM while Mentor provide AVM. Anyone can give some comment on these two methodology? Or are they similar? I don't know if Synopsys's VMM is open document and open source code. The AVM cookbook/source code, you can download a free copy from: http://www.mentor.com/products/fv/_3b715c/cb_dll.cfm Best regards, DavyArticle: 110447
Hi all,
I have ChipScope Pro 7.1. I successfully evlauate all signal of top
module my design. Now i want to also evaluate all signals which is
instantiate in top module. For this i just add ChipScope on that
particular file and add ILA core and finally select signals. But
finally when i implement design, synthsiser skip the inserted ILA core.
Can any body tell me how i can monitor low lvel signals without porting
these in TOP file.
_____ UART TOP______
--------> Successfully Done thr ILA
|
|
UART RX UART TX
---------> How i monitor
|
|
RX_SM
TX_SM --------> How i monitor
Best Regards
Article: 110448Hi Please select in XST parameters : "Keep Hierarchy - Yes" and restart. Alexander "naumanqau@gmail.com =D0=BF=D0=B8=D1=81=D0=B0=D0=BB(=D0=B0): " > Hi all, > I have ChipScope Pro 7.1. I successfully evlauate all signal of top > module my design. Now i want to also evaluate all signals which is > instantiate in top module. For this i just add ChipScope on that > particular file and add ILA core and finally select signals. But > finally when i implement design, synthsiser skip the inserted ILA core. > Can any body tell me how i can monitor low lvel signals without porting > these in TOP file. > > _____ UART TOP______ > --------> Successfully Done thr ILA > | > | > UART RX UART TX > ---------> How i monitor > | > | > RX_SM > TX_SM --------> How i monitor =20 >=20 >=20 > Best RegardsArticle: 110449
I just started learning about fpga technology, I am looking for a solution to this minor problem. I'm supposed to build a physical layer repeater for a Wi-Fi signal using any of the xilinx products.this is actually a simulation project for school. the intial part is just a physical layer repeater. then i'll have to add the data link layer components for the final part of the project. Any assistance, suggestions will be appreciated.
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Compare FPGA features and resources
Threads starting:
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