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Hello, The RAMB16 component has much less clock-to-out time when using the optional output register. However, I need valid data one clock cycle after the address input is valid. The Virtex-4 User Guide ug070 states in Figure 4-5 (Page 115) that there are two optional inverters in the clock path. Also the port signal description (pg. 119): CLK polarity is configurable. I wanted to enable both inverters. The RAM content should than be clocked out at the falling edge. And the register delivers data at the following rising edge. Problem: There are only generic parameters to enable the clock inverter at the output register: INVERT_CLK_DO[A|B]_REG Does anyone know how I can adjust the clock polarity (without using the DCM CLK180 output)? Thanks FrankArticle: 110126
Amontec, Larry schrieb: > Antti wrote: > > > get from Xilinx website > > > > http://www.xilinx.com/bvdocs/appnotes/xapp730.zip > > > > unzip, then look in /pcores/microblaze_4_00_a/hdl/vhdl > > > > that looks like true unscrambled RTL source of the MicroBlaze !? > > > > Or am I seeing wrong ? > > > > Antti > > > > Yes it is as the RTL VHDL source of the Xilinx Microblaze. > Publish Error from Xilinx ? > > Regards, > Laurent > ________________________ > Amontec > http://www.amontec.com > New JTAG solution: JTAGkey-Tiny @ =8029.- Hi Larry. looks like and Xilinx Error, both the PDF and ZIP file seem to be removed from Xilinx website! AnttiArticle: 110127
Jim Granville wrote: > scott moore wrote: > > > > I don't see testability as a barrier. Your yield is not dependent on the > > good or bad design of the customer (as it is in custom ICs), so the > > design as burned is testable. The design flow becomes more like an ASIC, > > with the customer providing bits and vectors. All the maker cares about > > is the go/no go for the device. It certainly argues for the maker > > getting more involved in the programming process, and judging from > > typical makers web sites, that is exactly what they do (Actel, etc.). > > Where that matters, is in the impacts of < 100% yield. > You can't really mount the devices before programing, and so > suffer another handling step. Then you ideally need to > be able to decide which devices are duds _before_ you mount them > on your expensive PCB (that means costly vector testing), and > finally, who pays for the dud's ? > I think only TI still makes OTP CPLDs (Atmel have a couple of MilSpec > ones alive )- everyone else has gone to EE, and that's on small/simple > devices. > Looking at Actel's latest push, I see their FLASH devices are > pushed as low power (not their antifuse), and Actel claim the QuickLogic > PolarPro benchmark as the worst battery life of the low power alternatives. > http://www.actel.com/products/igloo/ > > Pretty much places any OTP device in the NFND bucket ? I think you missed Scott's point. He is saying that for a production of any volume, you can let the manufacturer program the devices. They are better equipped and at that point it adds little to the price. Let's face it, the cost of testing any large FPGA is not trivial and the cost of factory programming antifuse parts is lost in the noise. In fact, once you let the factory program the parts, you can likely save on test costs since you only need to test the logic you are using, just like EasyPath, if I have the right name. So factory programming will likely reduce the price of the antifuse parts over buying them yourself even without considering the cost of programming them in house. If the programming were done with something other than electricity, the programming circuitry could be eliminated. I seem to recall a company that used to provide fast ASIC-like prototypes with laser cutting of traces. I have not heard much about them lately. What was the down side of this approach?Article: 110128
Hello. I do not succeed to make the Simulink Co-simulation through parallel-door or with platform cable USB. How it is made?Article: 110129
me_2003@walla.co.il wrote: > Hi Goran, > I did not understood your answer.. > Do you mean that I need to create a system which contains two > microblaze instances and afterwards export it to the ISE ? > > What if I want to have these two microblazes in two different systems > and afterwards export them to ISE separately (my top.vhd will contain > two system (microblaze) instances ? Can I do it ? Can I use two BMM > files in that case ? > > Thanks in advance, Mordehay. > > > Göran Bilski wrote: >> Just add the 2nd MicroBlaze in the XPS tool. >> >> Göran Bilski >> >> <me_2003@walla.co.il> wrote in message >> news:1160296753.788965.57640@m73g2000cwd.googlegroups.com... >>> Hi all, >>> I have a microblaze processor that I've built using the EDK and >>> afterwards simulated and it seems to work fine. Now I need to make two >>> instances of this Microblaze system in my design. >>> Can I use the same module and instantiate it twice or I maybe I need to >>> make a copy of the system and name it differently. If I instance the >>> same module twice I figured out that it will be problematic to fill the >>> BRAM with code data. >>> Can anyone help ? >>> Thanks, Mordehay. >>> > You can instantiate a microblaze system twice in your toplevel. The only problem you have is the .bmm file. This is only describing the memory layout for one system. You can do the following: - take the generated .bmm file (generated by edk); - rename it to dual_mb.bmm for instance; - copy the contents from the file at the end of the file: ADDRESS_BLOCK plb_bram RAMB16 [0xffffc000:0xffffffff] BUS_BLOCK rtx/ppc_stub/plb_bram/plb_bram/ramb16_0 [63:56] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_1 [55:48] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_2 [47:40] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_3 [39:32] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_4 [31:24] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_5 [23:16] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_6 [15:8] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_7 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; ADDRESS_BLOCK plb_bram RAMB16 [0xffffc000:0xffffffff] BUS_BLOCK rtx/ppc_stub/plb_bram/plb_bram/ramb16_0 [63:56] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_1 [55:48] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_2 [47:40] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_3 [39:32] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_4 [31:24] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_5 [23:16] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_6 [15:8] ; rtx/ppc_stub/plb_bram/plb_bram/ramb16_7 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; - rename the name of the address blocks and rename the first part of every line which describes a memory part; ADDRESS_BLOCK txc_plb_bram RAMB16 [0xffffc000:0xffffffff] BUS_BLOCK transmitter_core/ppc_stub/plb_bram/plb_bram/ramb16_0 [63:56] ; transmitter_core/ppc_stub/plb_bram/plb_bram/ramb16_1 [55:48] ; transmitter_core/ppc_stub/plb_bram/plb_bram/ramb16_2 [47:40] ; transmitter_core/ppc_stub/plb_bram/plb_bram/ramb16_3 [39:32] ; transmitter_core/ppc_stub/plb_bram/plb_bram/ramb16_4 [31:24] ; transmitter_core/ppc_stub/plb_bram/plb_bram/ramb16_5 [23:16] ; transmitter_core/ppc_stub/plb_bram/plb_bram/ramb16_6 [15:8] ; transmitter_core/ppc_stub/plb_bram/plb_bram/ramb16_7 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; ADDRESS_BLOCK rxc_plb_bram RAMB16 [0xffffc000:0xffffffff] BUS_BLOCK receiver_core/ppc_stub/plb_bram/plb_bram/ramb16_0 [63:56] ; receiver_core/ppc_stub/plb_bram/plb_bram/ramb16_1 [55:48] ; receiver_core/ppc_stub/plb_bram/plb_bram/ramb16_2 [47:40] ; receiver_core/ppc_stub/plb_bram/plb_bram/ramb16_3 [39:32] ; receiver_core/ppc_stub/plb_bram/plb_bram/ramb16_4 [31:24] ; receiver_core/ppc_stub/plb_bram/plb_bram/ramb16_5 [23:16] ; receiver_core/ppc_stub/plb_bram/plb_bram/ramb16_6 [15:8] ; receiver_core/ppc_stub/plb_bram/plb_bram/ramb16_7 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; - include this .bmm file in your ise project and a dual_mb_bd.bmm file will be created. In your toplevel you should call the instances of your microblaze system respectively transmitter_core and receiver_core (using the example code above); Now the problem is: how to get the software executable into both memory locations, because importing the .bmm file in the edk won't work (the system is only having one memory layout for one microblaze, while the generated .bmm file has two). You can fix this by manually import the software executable in the generated .bit file. You have to use the tool data2mem. Look at the following line and modify it to your own situation. data2mem -bm syn\dual_mb_bd.bmm -bt syn\toplevel.bit -bd ..\code\executable.elf tag txc_plb_bram -bd ..\code\executable.elf tag rxc_plb_bram -o b download.bit I use this solution for a dual powerpc system, but I am sure it will work for the microblaze too. I had a conference call with xilinx in the past about this issue (using an edk project with one powerpc and instantiate it twice in a vhdl design). They told me that the tools are not made for this functionality. There solution was: make an edk project with both processors. This is not an option if you want to make a common block with one processor which you can instantiate multiple times. The only problem you could have is debugging your software. With the powerpc system you can only have one jtagppc_cntlr in the fpga. So it must be placed outside the edk project. I gave it a try but was not able to make contact through the edk. The edk simply detected no jtagppc_cntlr in the .mhs file so it assumed there was none in the fpga. I don't know if it would work with the microblaze in combination with the opb_mdm module. FrankArticle: 110130
damb.flaviano@libero.it schrieb: > Hello. > > I do not succeed to make the Simulink Co-simulation through > parallel-door or with platform cable USB. > > How it is made? if your doors are really parallel then you need to exit both doors in parallel! it takes some time practicing :) AnttiArticle: 110131
Paul Schreiber <synth1@airmail.net> wrote: > > a look at the Xilinx "online" shop or other Xilinx sources shows that the > > Product line of Spartan 3E still shows gaps. While e.g. the datasheet > > shows > > both the XC3S100E and XC3S250E planned in TQ144, only the XC3S100E is > > available yet. Same for 250/500 in PQ208. This defeats migration from one > > size to another. > The 250K gate in PQ208 is shipping, I have 100 of them sitting here in a > box. Yes, but the 500E in PQ208 is missing... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 110132
I've been performing post-map static timing analysis and have noticed
that my TIG UCF constraint is being ignored for some reason. Here is
what I have:
<SNIP>
## TIG
NET "ctrl1_clr" TNM_NET = "TN_ctrl_clr";
NET "ctrl2_clr" TNM_NET = "TN_ctrl_clr";
NET "sync_drpp_clr_inst/sync_r2<0>" TNM_NET = "TN_sync_drpp_clr";
NET "sync_drpp_clr_inst/sync_r2<1>" TNM_NET = "TN_sync_drpp_clr";
TIMESPEC "TS_TIG_clr2synch" = FROM "TN_ctrl_clr" TO "TN_sync_drpp_clr"
TIG;
</SNIP>
The first two nets listed are assigned to a timing name belonging to
paths that are asychronous to another clock. This clock drives
registered ports of an instance (synchronization circuit) with port
name sync_r2(1:0). Normally I would edit the UCF manually, but it
absorbed some of the signal names, so instead I used the constraint
tool to generate the above.
When I run timing I get the following:
<SNIP>
WARNING:Timing:3223 - Timing constraint PATH "TS_TIG_clr2synch_path"
TIG;
ignored during timing analysis.
</SNIP>
Here is one of the timing errors from the post-map static timing
analyzer:
<SNIP>
Timing constraint: TS_adc_clk_dcm_clkfx = PERIOD TIMEGRP
"adc_clk_dcm_clkfx" TS_adc_clk / 0.7
HIGH 50%;
278920 items analyzed, 4 timing errors detected. (4 setup errors, 0
hold errors)
Minimum period is 8.415ns.
--------------------------------------------------------------------------------
Slack: -0.270ns (requirement - (data path - clock path
skew + uncertainty))
Source: ctrl2_ins/curr_st_FFd1 (FF)
Destination: sync_drpp_clr_inst/sync_r1_1 (FF)
Requirement: 0.571ns
Data Path Delay: 0.590ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: adc_clk_dcm_clk0_bufg rising at 28.000ns
Destination Clock: adc_clk_dcm_clkfx_bufg rising at 28.571ns
Clock Uncertainty: 0.251ns
Timing Improvement Wizard
Data Path: ctrl2_ins/curr_st_FFd1 to sync_drpp_clr_inst/sync_r1_1
Delay type Delay(ns) Logical Resource(s)
---------------------------- -------------------
Tcko 0.291 ctrl2_ins/curr_st_FFd1
net (fanout=22) e 0.100 ctrl2_ins/curr_st_FFd1
Tfck 0.199 ctrl2_ins/curr_st_Out11
sync_drpp_clr_inst/sync_r1_1
---------------------------- ---------------------------
Total 0.590ns (0.490ns logic, 0.100ns route)
(83.1% logic, 16.9% route)
</SNIP>
Why is ISE ignoring my constraint? How am I supposed to know what my
true worst path is if I can't eliminate this timing error?
Thanks,
-Brandon
Article: 110133Uwe Bonnes schrieb: > Paul Schreiber <synth1@airmail.net> wrote: > > > a look at the Xilinx "online" shop or other Xilinx sources shows that the > > > Product line of Spartan 3E still shows gaps. While e.g. the datasheet > > > shows > > > both the XC3S100E and XC3S250E planned in TQ144, only the XC3S100E is > > > available yet. Same for 250/500 in PQ208. This defeats migration from one > > > size to another. > > > The 250K gate in PQ208 is shipping, I have 100 of them sitting here in a > > box. > > Yes, but the 500E in PQ208 is missing... > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Uwe you are still looking for largest FPGA in non-BGA? wait a moment - the s3e500 PQ208 does exist! I do have a module where it on and already for 3 months so I wonder why you cant order this part? AnttiArticle: 110134
Antti ha scritto: > damb.flaviano@libero.it schrieb: > > > Hello. > > > > I do not succeed to make the Simulink Co-simulation through > > parallel-door or with platform cable USB. > > > > How it is made? > > if your doors are really parallel then you need to exit both doors in > parallel! > > it takes some time practicing :) > > Antti parallel cable!!!Article: 110135
So, you wish to drive a LVCMOS input from a SSTL output? If this is what you are doing, at 2.5 volts, then if the CPLD is programed for SSTL class I, and there are no resistors used (no terminations), then the SSTL output is compatible with the LVCMOS input. This can be simulated with any signal integrity simulation tool (like Mentor's Hyperlynx) in about 60 seconds (which I did). To really know, and to be absolutely sure, I would need the part number and manufacturer of the CPLD, and the IBIS file for the SSTL output (I used the SSTL_I output for a V4 FPGA). I think I understand the hotline's confusion now. Your boundary scan has nothing to do with JTAG. How confusing, as the only context that we have heard of boundary scan in, is JTAG. AustinArticle: 110136
Bob, I am still waiting for an official "yes" or "no". Austin > Austin, > > What did you find out about this? Is LVDS_25_DCI and SSTL2_II_DCI allowed > in the same S3 bank? > > Thanks, > Bob > >Article: 110137
Austin I'm fairly sure that you understand most/all of this but you have suggested to the world that I don't...... :-) I am using a third party boundary scan tool from assett intertech which uses the JTAG port to twiddle pins on certain devices and read back the values on other pins on the same net so yes I'm fairly certain that I'm using JTAG. If the coolrunner II is not programmed then there is no confusion, one uses the bsdl file provided by xilinx which defines the jtag behaviour of the device and the coolrunner will drive outputs and receive inputs as CMOS to the value of whatever I have set VCCIO to for that bank. If the coolrunner has been programmed then there is a tool from xilins called BSDLANNO which looks at the fitter output and the original bsdl file and creates a new bsdl because inputs are input only for jtag, but outputs can be IO still for JTAG. your tech support took a week to tell me that outputs are output only for jtag so 13 days ago I showed them the bsdlanno documentation and they said they would get back to me. There is no issue with SSTL receiving CMOS because CMOS drives rail to rail (2.5v) which is what the SSTL driver does. However a CMOS receiver threshold is somewhat different to a SSTL rx threshold which means there is not as much (I said it was a marketing thing) noise immunity by the time the sstl signal has gone through the sstl termination scheme. My question is therefore what do I do to ensure that my boundary scan gets done using sstl levels. Now waiting 3 weeks for this bit. Colin Austin Lesea wrote: > So, you wish to drive a LVCMOS input from a SSTL output? > > If this is what you are doing, at 2.5 volts, then if the CPLD is > programed for SSTL class I, and there are no resistors used (no > terminations), then the SSTL output is compatible with the LVCMOS input. > > This can be simulated with any signal integrity simulation tool (like > Mentor's Hyperlynx) in about 60 seconds (which I did). > > To really know, and to be absolutely sure, I would need the part number > and manufacturer of the CPLD, and the IBIS file for the SSTL output (I > used the SSTL_I output for a V4 FPGA). > > I think I understand the hotline's confusion now. Your boundary scan > has nothing to do with JTAG. How confusing, as the only context that we > have heard of boundary scan in, is JTAG. > > AustinArticle: 110138
"u_stadler@yahoo.de" <u_stadler@yahoo.de> writes: > hi > > i hav a problem with edk. i created a poject a while ago and everything > worked fine. but today i changed some c code and wanted to compile it. > i got the following error message : > > Console Log) > At Local date and time: Tue Oct 10 22:53:30 2006 > xbash -q -c "cd /cygdrive/c/CodeGeeks/test_edk8/; /usr/bin/make -f > system.make program; exit;" started... > system.make:173: *** target pattern contains no `%'. Stop. > > Done! > > > i tired to reinstall everything but it didn't help. any ideas somebody? > EDK is incompatible with the new version of cygwin make. I got around this by deleting the make.exe from the cygwin install - EDK puts it's version back in after that. It was Antti that I got this solution from up another thread somewhere - thanks Antti! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 110139
radarman wrote: > KJ wrote: > > > > Maybe because there are companies like Synplicity and Mentor Graphics that > > sell tools that are not vendor specific and do not sell parts. When > > Microsoft bundles things in and 'gives things away' people rant about how > > they drive the independent software vendors out of business....a similar > > argument would likely apply here. > > > > Altera, Xilinx, Synplicity, Mentor Graphics et al pay out hard cash to > > provide software tools and all expect some return on that investment in some > > form (either directly from the tool or indirectly through parts or both). > > If one (or more) of the parts guys gives the tools away it can probably be > > construed by the legal eagles in Washington as a tactic to drive a > > competitor out of business thus deserving of some close and unprofitable > > scrutiny. Obviously they can get away with giving limited versions of the > > tool away; I'm sure Synp and Ment would prefer to make money off of those as > > well but apparently the perceived loss in revenue is not considered to be > > worth trying to recoup via the legal system, anti-trust laws, that sort of > > approach. > > > > Just my speculation. > > > > No, I think Altera and Xilinx give away the low-end stuff so that > students and hobbiests will get exposure to their products. After all, > if the price of entry is > $3k, how many college's, much less students, > will be able to provide a reasonable number of seats to do FPGA > designs? Also, the best students are going to want to do some work at > home, and most are certainly NOT going to be able to afford the full > Quartus or ISE package. With both Xilinx and Altera giving away low-end > versions of the software, those students can now choose either, or > both, to try out at home. The cost of development boards becomes the > next issue. (Xilinx is still winning this one) > > Thus, the free software is almost a promotional expense for the FPGA > vendors. It gives people a taste of what's available, and (hopefully) > gives the users a good impression. I have no doubt that it's in Altera and Xilinx and all other FPGA/CPLD vendors to supply free design software as a mechanism to hook potential and future customers. My point was that if you're Mentor Graphics or Synplicity your flagship product is now competing against the free stuff. Giving stuff away for 'free' causes companies to wave the 'anti-trust' flag when they see their business going down the tubes or rally the 'anti-dumping' troops when it comes from a foreign owned company. Their are of course other responses as well but if you're running the business you might want to limit your exposure to that sort of thing. For yet another reason for a nominal charge..... Obviously one business strategy for the Mentors and Synplicitys of the world to try to compete in that environment is to wangle their way in and make the FPGA/CPLD vendors pay a license in exchange they will supply the hobbled version of their software.....which is why practically every FPGA vendor has some 'free' form of Modelsim for anyone who wants it basically. Now if the license fee that say Altera (or whoever) pays to Mentor Graphics is based on the number of Modelsim seats that they give away then Altera has an economic incentive to keep track of just how many of these 'freebies' they've given away. Charging even a nominal fee to get that license is generally enough to thwart the spam attacks that might otherwise cause them to pony up a big chunk of cash to pay for all those freebies that were simply someone hatching an e-assault on them. The FPGA vendors that choose to not charge even a nominal fee are potentially opening themselves up to a big cash payout if the fee they must pay is tied to how many seats they give away and someone decides to hit them up with a cyber attack. I'm not saying what they're doing is right, wrong or indifferent or that I even have a clue about how the agreements between the companies are worded just that I see a very plausible reason for some modest amount money to change hands, not as a profit making measure (since it isn't) or for future business (which it might), or for goodwill (which it is) but simply to limit their exposure to a license fee. KJArticle: 110140
"Ben Twijnstra" <btwijnstra@gmail.com> schrieb im Newsbeitrag news:2e07f$452c0685$d52e23a9$1525@news.chello.nl... > Frank van Eijkelenburg wrote: > >> I know about the bscan blocks in the xilinx virtex devices (bscan_virtex4 >> for instance). With these blocks you can make your own interface by use >> of >> the boundary scan usercode instruction. >> >> Does something like this exists for altera devices? > > Yes, but not very well documented. Contact me directly. > > Best regards, > > > Ben actually it is documented :) or was until my webserver got hacked and I had to format the HD. altera docs contain enough info to use the altera scan primitive and lately there was some new app notes about this useage but I dont have those references handy - I think it was posted on c.a.f. as a sidenote - all FPGAs have it today, Xilinx Altera Lattice Actel the primitive is a bit different depending on family and device but it is available for use in user logic AnttiArticle: 110141
daughenbaugh@gmail.com schrieb: > Antti wrote: > > JTAG BPI S3E issue - there is a solution that fixes the problem > > the external flash memory can be put into status read mode using > > CFI commands and boundary scan, then the JTAG can be used to > > work with the FPGA as if there S3e bug wasnt there. Its a bit tricky > > but working solution. > > I like your solution. Clever! > > Does this mean that you ran into this problem too? Do you see it with > Stepping 1 as well? > > Jason Thanks! I developed this solution in order to provide flash programming solution for the "s3e sample pack" it works nicely. I cant comment on stepping 1 as I have no s3e boards with nr flash so I can not test it. AnttiArticle: 110142
Martin Thompson schrieb: > "u_stadler@yahoo.de" <u_stadler@yahoo.de> writes: > > > hi > > > > i hav a problem with edk. i created a poject a while ago and everything > > worked fine. but today i changed some c code and wanted to compile it. > > i got the following error message : > > > > Console Log) > > At Local date and time: Tue Oct 10 22:53:30 2006 > > xbash -q -c "cd /cygdrive/c/CodeGeeks/test_edk8/; /usr/bin/make -f > > system.make program; exit;" started... > > system.make:173: *** target pattern contains no `%'. Stop. > > > > Done! > > > > > > i tired to reinstall everything but it didn't help. any ideas somebody? > > > > EDK is incompatible with the new version of cygwin make. I got around > this by deleting the make.exe from the cygwin install - EDK puts it's > version back in after that. > > It was Antti that I got this solution from up another thread somewhere > - thanks Antti! > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt - Consultancy in Engineering, Knowledge and Technology > http://www.conekt.net/electronics.html hi Martin, ROTFL I was just looking at "what it is about here" in this thread and browsed the thread until "... thanks Antti" :) great. Antti still LOLArticle: 110143
"Frank Leischnig" <leischni@vialux.de> wrote in message news:Pine.WNT.4.64.0610111610270.3048@wxpvl06.iwu.fhg.de... <snip> > Does anyone know how I can adjust the clock polarity (without using the > DCM CLK180 output)? > > Thanks > > Frank Do you explicitly have a problem if you invert the clock in your source code?Article: 110144
Sorry for the OT post... but the curiosity... (kill the cat...)
Is Sun acquiring Xilinx ?
http://www.xilinx.com/favicon.ico
seems the Sun logo
xilinx guys... please change your favicon ;-)
Sandro
Article: 110145that worked!! thanks a lot guys!!!Article: 110146
Colin, Do not use any termination. If you use any termination at all, it will not work. That simple. If you don't use any termination, you may get reflections, and that might be a problem, too. Get Hyperlynx, and run the simulations yourself. Austin colin wrote: > Austin > > I'm fairly sure that you understand most/all of this but you have > suggested to the world that I don't...... :-) > > I am using a third party boundary scan tool from assett intertech which > uses the JTAG port to twiddle pins on certain devices and read back the > values on other pins on the same net so yes I'm fairly certain that I'm > using JTAG. > > If the coolrunner II is not programmed then there is no confusion, one > uses the bsdl file provided by xilinx which defines the jtag behaviour > of the device and the coolrunner will drive outputs and receive inputs > as CMOS to the value of whatever I have set VCCIO to for that bank. > > If the coolrunner has been programmed then there is a tool from xilins > called BSDLANNO which looks at the fitter output and the original bsdl > file and creates a new bsdl because inputs are input only for jtag, but > outputs can be IO still for JTAG. > your tech support took a week to tell me that outputs are output only > for jtag so 13 days ago > I showed them the bsdlanno documentation and they said they would get > back to me. > > There is no issue with SSTL receiving CMOS because CMOS drives rail to > rail (2.5v) which is what the SSTL driver does. > However a CMOS receiver threshold is somewhat different to a SSTL rx > threshold which means there is not as much (I said it was a marketing > thing) noise immunity by the time the sstl signal has gone through the > sstl termination scheme. > My question is therefore what do I do to ensure that my boundary scan > gets done using sstl levels. Now waiting 3 weeks for this bit. > > Colin > > > > Austin Lesea wrote: >> So, you wish to drive a LVCMOS input from a SSTL output? >> >> If this is what you are doing, at 2.5 volts, then if the CPLD is >> programed for SSTL class I, and there are no resistors used (no >> terminations), then the SSTL output is compatible with the LVCMOS input. >> >> This can be simulated with any signal integrity simulation tool (like >> Mentor's Hyperlynx) in about 60 seconds (which I did). >> >> To really know, and to be absolutely sure, I would need the part number >> and manufacturer of the CPLD, and the IBIS file for the SSTL output (I >> used the SSTL_I output for a V4 FPGA). >> >> I think I understand the hotline's confusion now. Your boundary scan >> has nothing to do with JTAG. How confusing, as the only context that we >> have heard of boundary scan in, is JTAG. >> >> Austin >Article: 110147
well that was a bit early. thanks again for the tip that solved the firs problem. but now i have another Running synthesis... bash -c "cd synthesis; ./synthesis.sh" ./synthesis.sh: line 2: : command not found Release 8.1.02i - xst I.27 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. ERROR:Xst:427 - Entry File system_xst.scr not found ./synthesis.sh: line 9: syntax error: unexpected end of file make: *** [implementation/system.ngc] Error 2 Done! can anybody help me out here? i already replaced the "bash" file but that didn't help. also the system_xst.src fiel is there and in the synthesis.sh line 2 is blank.?!? any ideas? thanks urbanArticle: 110148
> I am buying a new for my work. I do a lot of synhesis, map and P&R > using ISE 8.2 (Windows) in Xilinx EDK with quite complex systems. > Building a HW for such a system can take a very long time, so selection > of an appropriate computer is a must. this question pops up every few months ... - Most important is the CPU cache (so Intel Core 2 Duo with 4M should give some speedup) - second factor is memory size - if ISE and your OS run out of memory then swapping will last forever (2 GBytes is not too much) I ordered a machine like this 2 weeks ago but it has not yet arrived look at message id 45124c6e$1@news.fhg.de and follow ups ... multi-core does not yet give you anything for ISE bye, MichaelArticle: 110149
One of the problems with OPB is that the more peripherals you add the slower it goes. All of the control signals data returns from modules etc are ORed together. There are ways to improve module response to clock e.g. pipelining the return of data. It is worth looked at the results in timing analyser to identify problem modules and see if you can do anything to improve the speed of them. On the brute force approach try using multiple place and route. Option can be set in the Placement options in ISE. Also playing with synthesiser switches - especially hierarchy settings may also help. John Adair Enterpoint Ltd. u_stadler@yahoo.de wrote: > hi > > i hvea a question about implementing a microblaze with ethernet. i'm > using a spartan 3e 500 an edk8.2. i created a new project with a > microblaze, an ethernet core, sdram, timer debug module an uart. in the > ethernet datasheet it says that in order to be able to use 100MBit the > obp bus hast to run at least with 65 MHz. my problem now is the the > design wont synthesize with more than 59 MHz even if i do multiple > iterations. > can anybody give me a hint what to do? > do i have to set some more constraints or anything else? > > thanks > urban
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