Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
W dniu 5/7/2011 02:11, Alexander Kane pisze: > Just a bit about the project I'm working on: Have an FPGA gathering > and manipulating data, and we need a processor to run the show and to > send the data over a network. At the moment we are planning on using > a soft-processor. Still early stages in the project and and I'm > currently deciding between Cyclone and Spartan. I haven't had any > experience with either Nios II or MicroBlaze (and I believe that these > are the only real options out there if you want strong community and/ > or professional support). I used Nios in one of my projects. Around 16 running cores on 10 fpga's with single JTAG chain. Really great. > > Anyway, what's really confusing me is the licensing issues. I know > these questions have been asked before but I'm still confused. I also had such problem with Altera - licensing & pricing. I had to clarify this before I started with my project. > > I understand that to use the MicroBlaze processor you either need to > purchase the ISE Embedded Edition or purchase Platform Studio and the > Embedded Development Kit (and use it with ISE WebPACK). However from > what I can find out it says that you're free to put MicroBlaze > processors on as many devices as you wish so long as they remain on > site. I can't find any information about what type of license you > need to include MicroBlaze in a product being sold. > > In the case of Nios II, you can use and develop with the Nios II with > the Quartus II Web Edition because it comes with the OpenCore license > that lets you use IP on an Altera FPGA so long as your development > board is plugged in to the PC (I assume it doesn't matter who's > hardware you use). The e variant you can use for free, but the other > variants require a license to work when disconnected. The license you > need is IP-NIOS, and though I can't find an official price listing > anywhere I've seen $US500 being mentioned on forums... and presumably > this allows you to sell as many products as you wish with Nios II > processors on them? With IP-NIOS Licence you can sell as many products as you want. Without also but only slowest NIOS version - now is for free. Without IP-NIOS you can't make flash programming files for FPGA( for fastest & middle version), you can only download image to FPGA using JTAG. In other words you have to load image after every power-up. > > I've stated a whole bunch of assumptions here and I'd appreciate it if > someone could tell me if I'm on the right track. > Any advice on choosing between MicroBlaze and Nios II, or is there > another option I'm missing? > My company wants to spend as little as possible on licensing and/or > development tools (this is their first time using an FPGA in a > product), but my time is effectively free to them (I'm there under a > research grant). That said, I know the free way is usually the hard > way so if I can make a compelling case for them to spend money it may > make my life a lot easier. In this case free NIOS version really works . I know only one disadventage - C/C++ IDE is based on eclips which makes me somtimes upset. BTW I've never used Xilinx uBlaze or similar - so I can't compare. AdamArticle: 151726
> >avionion@gmail.com wrote: >> the pcores flder is empty now :( >> can anyone email me the origianl zip file which has pdf and zip file in >> it? > >Hmm. Would that be legal? > >The files all have their copyright in tact, but by placing something on >the web, have you implicitly given someone the right to copy (if not to >distribute further copies, at least to retain the copy for yourself)? > >Good luck to anyone trying to port it though ;-) > >Cheers, >Jon > > I know this is an old post but can anyone please tell me how might be able to acquire a copy of this file with the included microblaze source code... thank you! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151727
Good day everyone I am fairly new to FPGA based architectures, and I'm interested in applications that are very sensitive to IO bus latency (PCIe or FSB). Can anyone advise of FPGA cards that can plug in directly into SDRAM bus socket. Looking for cards with only one or two FPGAs on board. Thanks & regards, Khaled --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151728
> If you don't adjust the phase to align the clock to the timing of the > return data your clock speed will be limited by the round trip delay > path. What exactly should be adcjusted? Which round trip? Let's start by the addr/cmd delivery to the SDRAM. How matching FB length with the trace to SDRAM clock helps the command to arrive closer to the falling edge? > That's also why they use a 90 degree phase relationship between > the output clock and the input clock. That puts the sample time in > the middle of the data stable time. I believe the 90 degree-shift is independent from the feedback. I more or less under stand how it works. It is discrete and logical. I do not understand the feedback. How should I adjust it in the FPGA and how does it help.Article: 151729
You dont actually need this pcb trace. Just clock the SDRAM using the clock output of a DCM and clock the data from a 90 degree output. That will give you ample setup time. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151730
valtih1978 <intellij@yandex.ru> wrote: > >> If you don't adjust the phase to align the clock to the timing of the >> return data your clock speed will be limited by the round trip delay >> path. > >What exactly should be adcjusted? Which round trip? >Let's start by the addr/cmd delivery to the SDRAM. How matching FB length >with the trace to SDRAM clock helps the command to arrive closer to the >falling edge? > >> That's also why they use a 90 degree phase relationship between >> the output clock and the input clock. That puts the sample time in >> the middle of the data stable time. > >I believe the 90 degree-shift is independent from the feedback. I more or >less under stand how it works. It is discrete and logical. I do not >understand the feedback. How should I adjust it in the FPGA and how does it >help. The problem is that you don't know the delay between the output of the flipflop and the signal arriving at the SDRAM. When reading appnotes on memory controllers you should bear in mind that FPGA vendors want to push their devices to the limits and come up with overcomplicated solutions. Like Rickman said, if don't push the design to the limits and do a proper timing analysis you can come up with a much simpler solution. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 151731
Hello,
Alexander Kane wrote:
> Just a bit about the project I'm working on: Have an FPGA gathering
> and manipulating data, and we need a processor to run the show and to
> send the data over a network.
First, make sure that a FPGA is really necessary, as many embedded chips
can do great work already with ready-made IP stacks and such...
Furthermore, you could use Ethernet-enabled coprocessors such
as the Wiznet chips. Quite handy, saves you an OS and RAM and such.
Then here are other VIABLE solutions that I know :
* As mentioned in other posts, check http://milkymist.org/
it's free (as in open source) and it works, using MICO32.
From what I heard by the developer, it uses MICO32 for very
good reasons, after trying other cores.
If you already have a FPGA board, you can download the source
code, tweak it for your specific platform, and see what you get.
At least the TCP/IP stack, compiler, CPU core and even memory interface
are already cared of.
* Actel has ARM solutions, either as soft cores (precompiled and
able to run at around 60MHz) or hard cores (in the latest SmartFusion).
I have not used any but ARM is well known (it's not an obscure ad hoc
"me too" architecture) and in the case of the A3P family, you can order
the chips with the license key for the softcore at no additional cost.
Two points to check : the Actel price/speed points are different
from the competitors, check that your application fits. Then check
how you will add the TCP/IP/ethernet connection, what will your
software stack be, what physical interfaces etc. ?
Good luck !
yg
--
http://ygdes.com / http://yasep.org
Article: 151732Hi! So, I'm using XUPV2P board (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,794&Prod=XUPV2P). And I'm having a problem setting up my DDR SDRAM module to work properly (it never passes Memory Test). Memory module that I'm using is : Hynix HY5DU56822BT-D43( http://www.intel.com/technology/memory/ddr/specs/hy5du564%288%2922btd4%283%29%28rev0.3%29.pdf ). Unfortunately, this module is not among modules in mpmc_memory_database.csv I've tried everything. From using other similar module configurations to setting my own module configuration from the datasheet. But it just doesn't work. Could someone please help me? Give me the configuration for this memory module, or give me some directions on how to do it? Btw. , I'm using EDK 10.1 sp3 if that matters. I would really appreciate it. Thanks in advance! kensvebary --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151733
Hi, I'm very impressed with a J1 forth processor: http://excamera.com/sphinx/fpga-j1.html I'd like to use it to implement simple non-time critical control and debugging layer in my FPGA based DSP system. However to accomplish it I need to add possibility of interactive work via console connected either by UART or by JTAG. Has anybody tried to extend the J1 published in http://excamera.com/files/j1demo.tar.gz with possibility to interactively define new words and execute them? -- TIA & Regards, WZabArticle: 151734
Hi, I have been using Xilins XST for a while and have come to a performance problem which leads me to think of if there is any better syntheses like Synopsys or other. The device is a Spartan3 4000 an I use Xilinx 13.1 since a couple weeks ago after a upgrade from 9.2 Anyone that can share some experience of syntheses? /michaelArticle: 151735
There is a developer that just ported the Verilog version of the J1 processor to MyHDL. You might be able to leverage this work to easily make the modifications you mention. Posting to the MyHDL newsgroup might get a response. Regards, Chris Felton On 5/13/2011 7:34 AM, wzab wrote: > Hi, > > I'm very impressed with a J1 forth processor: http://excamera.com/sphinx/fpga-j1.html > I'd like to use it to implement simple non-time critical control and > debugging layer > in my FPGA based DSP system. > However to accomplish it I need to add possibility of interactive work > via console > connected either by UART or by JTAG. > Has anybody tried to extend the J1 published in http://excamera.com/files/j1demo.tar.gz > with possibility to interactively define new words and execute them? > -- > TIA& Regards, > WZabArticle: 151736
You will get a bit better performance with Synplify, but do you really want to have to pay a lot of money for it. Not sure of the current price of Synplify but I think its in the thousands of dollars. I would of thought you would be better off using a faster fpga like Spartan 6. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151737
Hi, On 05/13/11 05:41 PM, maxascent wrote: > You will get a bit better performance with Synplify, but do you really want > to have to pay a lot of money for it. Not sure of the current price of > Synplify but I think its in the thousands of dollars. I would of thought > you would be better off using a faster fpga like Spartan 6. > > Jon Yes I know the price, I would be in the range of $1-20000 I guess, that is the same as one month of work. A newer FPGA would be great but not when you have systems all over the planet, that will make Synplicity a bargain if it does the job :) Have you lately done something with Synplicity and Xilinx 13.1? /michaelArticle: 151738
To be honest I think you can probably multiply your Synplify estimate by about x5. Anyway I dont really think you are going to get something like a 50% perfromance increase with Synplify, maybe 10% or 20%. I think that XST has improved a lot and the gap to the other tools isn't as big as it maybe was a few years back. I can't believe that you are getting worst performance by upgrading to to 13.1 from what you had with an older version. What frequency are you tring to achieve and how much is it failing? Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151739
On May 11, 1:39=A0pm, valtih1978 <intel...@yandex.ru> wrote: > > If you don't adjust the phase to align the clock to the timing of the > > return data your clock speed will be limited by the round trip delay > > path. > > What exactly should be adcjusted? Which round trip? > Let's start by the addr/cmd delivery to the SDRAM. How matching FB length > with the trace to SDRAM clock helps the command to arrive closer to the > falling edge? > > > That's also why they use a 90 degree phase relationship between > > the output clock and the input clock. =A0That puts the sample time in > > the middle of the data stable time. > > I believe the 90 degree-shift is independent from the feedback. I more or > less under stand how it works. It is discrete and logical. I do not > understand the feedback. How should I adjust it in the FPGA and how does = it > help. Draw a timing diagram of the clock, address and data, including the path delays on the PCB. The round trip is the clock plus address/data leaving the FPGA (include the internal delays as well as external) going to the ram, then the read data returning. What does the delay through the IO pins and on the PCB do to the setup and hold timing of the read data at the FFs inside the FPGA? Remember that the FFs are being clocked by the internal clock. Now consider that the read data FFs are being clocked by a DCM that is sync'd to a signal that is going out of the chip, through a trace equal to the path to the ram and back in the chip IO pins. The IO delays are multiple nanoseconds while the PCB trace is likely less than a single nanosecond, but at the speeds they push memory every fraction of a nanosecond counts. On the newer ram modules the interface includes a clock going to the ram, regenerated on the module and back to the memory interface. That's how important compensation of these delays are. If this is still not enough, maybe I can draw a diagram for you, but I'm away for the weekend. It will be likely Tuesday before I can look at this. RickArticle: 151740
On May 13, 8:34=A0am, wzab <wza...@gmail.com> wrote: > Hi, > > I'm very impressed with a J1 forth processor:http://excamera.com/sphinx/f= pga-j1.html > I'd like to use it to implement simple non-time critical control and > debugging layer > in my FPGA based DSP system. > However to accomplish it I need to add possibility of interactive work > via console > connected either by UART or by JTAG. > Has anybody tried to extend the J1 published inhttp://excamera.com/files/= j1demo.tar.gz > with possibility to interactively define new words and execute them? > -- > TIA & Regards, > WZab Perhaps I don't understand what you are asking. The web page says there is a development system supported under gforth. "Cross compiler runs on Windows, Mac and Unix" Are you talking about extending the hardware design rather than new words in Forth? Oh, you mean "interactive" rather than batch mode... I get it. No, that would require a certain amount of work on run time code on the device as well as supporting code on the host system. You might take a look at Riscy Pygness. They have already done this for the ARM processor I believe. It might be easier to adapt that code to the J1 app than to reinvent (or recode) the wheel. RickArticle: 151741
Hi:
I'm using a Xilinx Spartan 3E FPGA (on the Digilent NEXYS2 500k board)
to implement a quadrature encoder simulator, among other things.
The qep_sim.v code is shown below. The clock input to qep_sim() is
multiplexed from one of two buffered and isolated external world inputs.
The problem is that when the multiplexer selects one clock input, the
qep_sim() occasionally counts on a negedge. While, if the other input
is used, it never glitches like this and performs correctly.
The 288kHz clocks at the point where they enter the NEXYS2 board have
been probed and are clean, including when the counting glitch occurs.
What is stranger is that if I try to send a copy of the multiplexed
clock out to an IO pin to scope it, then the glitching goes away no
matter which clock source is selected.
Thanks for ideas on what might be wrong. I suspect it has something to
do with non-ideal choices of IO pins for the clock inputs. I didn't
have time to test this today, but I suspect if I simply move the
ext_sim_clk to a different pin, the problem will go away.
I wouldn't be satisfied with this however, as I wish to understand the
real cause of the problem.
Here is the multiplexing code (excerpted from a longer module):
module shaft (
// Begin QEP related ports
// Switch SW0 selects: 0 = ext_sim_clk, 1 = dsp_sim_clk
input clk_mux_sel,
// Note: signal dsp_sim_clk is being temporarily supplied for
// troubleshooting from an identical external buffer circuit
// as the ext_sim_clk:
input dsp_sim_clk, // sim clk generated by DSP.
input ext_sim_clk, // external sim clk input
// diagnostic sim clk output. Problem goes away if this is used:
// output sim_clk_o,
[edited out many lines]
);
wire sim_clk; // muxed sim clk to feed to qep_sim.v
// Select the simulation clock source:
assign sim_clk = clk_mux_sel ? dsp_sim_clk : ext_sim_clk;
// Instantiate the QEP simulator. Source for qep_maxcnt is not shown
// here for brevity, and since this isn't being used in qs1 at present.
qep_sim
qs1( .clk(sim_clk), .maxcnt(qep_maxcnt),
.a(qep_a_sim), .b(qep_b_sim), .m(qep_mex_sim) );
// The outputs of qs1 go to another mux, to select the simulator vs.
// a real encoder to send to the DSP's QEP counter peripheral. This
// code is not shown.
endmodule
Here's the relevant excerpt from my .ucf file (the sim_clk_o is
commented out when the problem is happening):
NET "dsp_sim_clk" LOC = "R18" | IOSTANDARD = LVCMOS33; # JB-2
NET "sim_clk_o" LOC = "G15" | IOSTANDARD = LVCMOS33 | SLEW = FAST; # JC-1
NET "ext_sim_clk" LOC = "H16" | IOSTANDARD = LVCMOS33; # JC-4
------------------------------------------------------------------------
// This module simulates the outputs of a BEI incremental
// (quadrature) encoder
module qep_sim(
input clk,
input [15:0] maxcnt, // not used at present, until problem diagnosed
output a,
output b,
output m
);
parameter MAX_CNT = 31; // using fixed period during troubleshooting
reg [15:0] cnt;
always @ (posedge clk) begin
if (cnt == MAX_CNT)
cnt = 0;
else
cnt = cnt + 1;
end
assign a = ~cnt[1];
assign b = cnt[1] ^ cnt[0];
assign m = ~b & (cnt == 0 || cnt == MAX_CNT);
// index pulse m is high
// straddling max count and zero. Why the redundant '&' with ~b is
// performed? I forget. Maybe this is unnecessary.
endmodule
------------------------------------------------------------------------
--
_____________________
Mr.CRC
crobcBOGUS@REMOVETHISsbcglobal.net
SuSE 10.3 Linux 2.6.22.17
Article: 151742
> Thanks for ideas on what might be wrong. I suspect it has something to
> do with non-ideal choices of IO pins for the clock inputs. I didn't
> have time to test this today, but I suspect if I simply move the
> ext_sim_clk to a different pin, the problem will go away.
Rather than using these signals as clocks, why not sample the incoming
signal with the Nexys2's 50 MHz clock?
Register the input and check for rising edges:
reg [1:0] ext_clk;
always @(posedge clk50)
ext_clk[1:0] <= {ext_clk[0], sim_clk};
wire rising_edge = ext_clk[1] & ~ext_clk[0];
and then count these:
always @(posedge clk50)
if (rising_edge)
if (cnt == MAX_CNT) ...
Joel
Article: 151743"Mr.CRC" <crobcBOGUS@REMOVETHISsbcglobal.net> wrote in message news:iqkvcv01c5r@news6.newsguy.com... > Hi: > > I'm using a Xilinx Spartan 3E FPGA (on the Digilent NEXYS2 500k board) > to implement a quadrature encoder simulator, among other things. > > The qep_sim.v code is shown below. The clock input to qep_sim() is > multiplexed from one of two buffered and isolated external world inputs. > > The problem is that when the multiplexer selects one clock input, the > qep_sim() occasionally counts on a negedge. While, if the other input > is used, it never glitches like this and performs correctly. > > The 288kHz clocks at the point where they enter the NEXYS2 board have > been probed and are clean, including when the counting glitch occurs. > > What is stranger is that if I try to send a copy of the multiplexed > clock out to an IO pin to scope it, then the glitching goes away no > matter which clock source is selected. > > Thanks for ideas on what might be wrong. I suspect it has something to > do with non-ideal choices of IO pins for the clock inputs. I didn't > have time to test this today, but I suspect if I simply move the > ext_sim_clk to a different pin, the problem will go away. > > I wouldn't be satisfied with this however, as I wish to understand the > real cause of the problem. > > > Here is the multiplexing code (excerpted from a longer module): > > module shaft ( > // Begin QEP related ports > // Switch SW0 selects: 0 = ext_sim_clk, 1 = dsp_sim_clk > input clk_mux_sel, > // Note: signal dsp_sim_clk is being temporarily supplied for > // troubleshooting from an identical external buffer circuit > // as the ext_sim_clk: > input dsp_sim_clk, // sim clk generated by DSP. > input ext_sim_clk, // external sim clk input > // diagnostic sim clk output. Problem goes away if this is used: > // output sim_clk_o, > [edited out many lines] > ); > > wire sim_clk; // muxed sim clk to feed to qep_sim.v > > // Select the simulation clock source: > assign sim_clk = clk_mux_sel ? dsp_sim_clk : ext_sim_clk; > > // Instantiate the QEP simulator. Source for qep_maxcnt is not shown > // here for brevity, and since this isn't being used in qs1 at present. > qep_sim > qs1( .clk(sim_clk), .maxcnt(qep_maxcnt), > .a(qep_a_sim), .b(qep_b_sim), .m(qep_mex_sim) ); > > // The outputs of qs1 go to another mux, to select the simulator vs. > // a real encoder to send to the DSP's QEP counter peripheral. This > // code is not shown. > > endmodule > > > Here's the relevant excerpt from my .ucf file (the sim_clk_o is > commented out when the problem is happening): > > > NET "dsp_sim_clk" LOC = "R18" | IOSTANDARD = LVCMOS33; # JB-2 > NET "sim_clk_o" LOC = "G15" | IOSTANDARD = LVCMOS33 | SLEW = FAST; # JC-1 > NET "ext_sim_clk" LOC = "H16" | IOSTANDARD = LVCMOS33; # JC-4 > > > > ------------------------------------------------------------------------ > // This module simulates the outputs of a BEI incremental > // (quadrature) encoder > module qep_sim( > input clk, > input [15:0] maxcnt, // not used at present, until problem diagnosed > output a, > output b, > output m > ); > > parameter MAX_CNT = 31; // using fixed period during troubleshooting > > reg [15:0] cnt; > > always @ (posedge clk) begin > if (cnt == MAX_CNT) > cnt = 0; > else > cnt = cnt + 1; > end > > assign a = ~cnt[1]; > assign b = cnt[1] ^ cnt[0]; > assign m = ~b & (cnt == 0 || cnt == MAX_CNT); > // index pulse m is high > // straddling max count and zero. Why the redundant '&' with ~b is > // performed? I forget. Maybe this is unnecessary. > endmodule This module qep_sim will have glitches in the middle of the high pulse on output b when cnt[1] changes picoseconds before cnt[0] as it can do, depending on internal routing.Article: 151744
Hi, On 05/13/11 07:16 PM, maxascent wrote: > To be honest I think you can probably multiply your Synplify estimate by > about x5. Anyway I dont really think you are going to get something like a > 50% perfromance increase with Synplify, maybe 10% or 20%. I think that XST > has improved a lot and the gap to the other tools isn't as big as it maybe > was a few years back. I can't believe that you are getting worst > performance by upgrading to to 13.1 from what you had with an older > version. What frequency are you tring to achieve and how much is it > failing? > Who said 13.1 was worse than 9.2, I did not say that! My question was if you or anyone else have any experience with the latest Xilinx and a third party syntheses tool! /michaelArticle: 151745
I misunderstood and thought that you where saying that you had a design in 9.2 which was fine and after moving to 13 you have problems. I guess it depends by how much you are missing timing to if Synplify would help you. Personally I would think it will not make a big improvement over XST. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151746
On May 14, 12:40=A0am, rickman <gnu...@gmail.com> wrote: > Perhaps I don't understand what you are asking. =A0The web page says > there is a development system supported under gforth. > > "Cross compiler runs on Windows, Mac and Unix" > > Are you talking about extending the hardware design rather than new > words in Forth? Well, this requires both extension of hardware (bidirectional port) and extension of Forth (compiler words in target system). > Oh, you mean "interactive" rather than batch mode... I get it. =A0No, > that would require a certain amount of work on run time code on the > device as well as supporting code on the host system. > On the host system the minicom for UART connection should be enough. For JTAG connection I have ready to use open solutions which may provide conectivity to such bidirectional port. https://groups.google.com/group/alt.sources/browse_thread/thread/38186c49dc= 5cf32e https://groups.google.com/group/alt.sources/browse_thread/thread/603ff14bdf= 020776 > You might take a look at Riscy Pygness. =A0They have already done this > for the ARM processor I believe. =A0It might be easier to adapt that > code to the J1 app than to reinvent (or recode) the wheel. Well, what I expect to have is something like amforth ( http://amforth.sf.n= et ) but without implementing of ARM core in FPGA. In fact I have already succesfully experimented with similar solution based on 6809 core published on googlecode : http://code.google.com/p/rekonstrukt/ However the 6809 SoC is slow and resource hungry. J1 is both faster and simpler. BTW I have found, that the sources mentioned in the J1 paper as published under BSD license: http://excamera.com/files/j1.pdf and which may be downloaded via: svn co https://code.ros.org/svn/ros-pkg/stacks/camera_drivers/trunk/wge100_= camera_firmware/src/ are much better for experiments then j1demo.tar.gz (eg.they allow you to use different Ethernet PHY). WZabArticle: 151747
Hi, On 05/14/11 01:04 PM, maxascent wrote: > I misunderstood and thought that you where saying that you had a design in > 9.2 which was fine and after moving to 13 you have problems. I guess it > depends by how much you are missing timing to if Synplify would help you. > Personally I would think it will not make a big improvement over XST. > > Jon No,I have design and it needs to be improved I and I don't belive in some fantastic tool or miracle which means that I need to try and gain 10-15% here and there in the hope that the result will be the 50-60% I need to make it work. /michaelArticle: 151748
Andrew Holme wrote: > "Mr.CRC" <crobcBOGUS@REMOVETHISsbcglobal.net> wrote in message > news:iqkvcv01c5r@news6.newsguy.com... >> reg [15:0] cnt; >> >> always @ (posedge clk) begin >> if (cnt == MAX_CNT) >> cnt = 0; >> else >> cnt = cnt + 1; >> end >> >> assign a = ~cnt[1]; >> assign b = cnt[1] ^ cnt[0]; >> assign m = ~b & (cnt == 0 || cnt == MAX_CNT); >> // index pulse m is high >> // straddling max count and zero. Why the redundant '&' with ~b is >> // performed? I forget. Maybe this is unnecessary. >> endmodule > > > This module qep_sim will have glitches in the middle of the high pulse on > output b when cnt[1] changes picoseconds before cnt[0] as it can do, > depending on internal routing. Yes, I see. Not sure why I didn't think of that. Now this reminds me that the reason why m includes the & ~b is to prevent a glitch on m when the cnt goes from MAX_CNT->0. But of course, that presumes b doesn't have glitches... I will try to work this out. BTW, the potential glitching you describe has never actually been observed from this module. Though with my slow slew rate outputs, it may have just been unobservable externally. So this is a seperate issue from the original problem, which is that cnt changes on the wrong edge of the clock sometimes. This results in shortened pulses for a, b, and less frequently, m, since the phenomenon is random so only in 2/(1+MAX_CNT) of cases does it overlap with m. It is also true that when the clocking glitch occurs, the correct phase of the a and b signals is preserved, So the encoder "speeds up" effectively by half a clock cycle. Thanks for the reply. -- _____________________ Mr.CRC crobcBOGUS@REMOVETHISsbcglobal.net SuSE 10.3 Linux 2.6.22.17Article: 151749
Joel Williams wrote:
>> Thanks for ideas on what might be wrong. I suspect it has something to
>> do with non-ideal choices of IO pins for the clock inputs. I didn't
>> have time to test this today, but I suspect if I simply move the
>> ext_sim_clk to a different pin, the problem will go away.
>
> Rather than using these signals as clocks, why not sample the incoming
> signal with the Nexys2's 50 MHz clock?
>
> Register the input and check for rising edges:
>
> reg [1:0] ext_clk;
>
> always @(posedge clk50)
> ext_clk[1:0] <= {ext_clk[0], sim_clk};
>
> wire rising_edge = ext_clk[1] & ~ext_clk[0];
>
> and then count these:
>
> always @(posedge clk50)
> if (rising_edge)
> if (cnt == MAX_CNT) ...
I could probably do something like this.
BTW, doesn't the above produce 20ns pulses on "rising_edge" when sim_clk
goes H->L, ie. on the falling edge?
Also, I wonder about the use of a once-registered asynchronous input
signal. Shouldn't the sim_clk be registered at least twice before
engaging in combinatorial functions? Ie, it seems that if ext_clk[0]
waffles for a few extra ns due to metastability, then the pulse on
"rising_edge" could be shorter than 20ns and not reliable.
Wouldn't it make more sense to simply use:
wire rising_edge = ext_clk[1] & ext_clk[0]; // ???
In which case I think it is safe even employing the once-registered
ext_clk[0] ?
There is still an unresolved engineering principles question here
though. Do FPGA logic designers ALWAYS sync asynchronous inputs to the
internal clock? If there is a circuit which is to be clocked by an
external source, and it is not going to interact with other process on
different clocks, then why bother syncing this clock input to the 50MHz
on-board clock? Ie, my qep_sim.v exists in its own clock domain, albeit
there is still the mux to choose which external clock to use.
This also doesn't answer the question of why the behavior changes vs.
input pin.
I have gathered that when clocks are to be brought in to the FPGA, it is
highly recommended to use a GCLK IO pin, so the signal may be buffered
onto a global clock routing line. I have to see if I can rearrange my
IOs to get these external inputs onto GCLK IOs, but there are two of
them and the NEXYS2 isn't very liberal about providing GCLKs on the pin
headers. Some other GCLKs are available on another connector, but I
don't yet have the mating for that.
Of course, when muxing external clock sources, if there are a lot of
them, one could eat into the supply of GCLKs quickly, so this is
undesirable.
A more interesting question is then, is it possible to take a GP IO
input pin, and internally buffer it onto an internal clock routing line?
Thanks for input and clarification.
--
_____________________
Mr.CRC
crobcBOGUS@REMOVETHISsbcglobal.net
SuSE 10.3 Linux 2.6.22.17
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z