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Try run xmd from edk http://forums.xilinx.com/t5/EDK-and-Platform-Studio/Simple-SDK-question-how-to-debug-as-simulation-in-SDK/m-p/124820#M17844Article: 151851
On May 7, 2:02=A0pm, valtih1978 <inte...@yandex.ru> wrote: > I see it in many SDRAM controllers, e.g.ftp://ftp.xilinx.com/pub/applicat= ions/xapp/xapp608.pdf, and nobody explains > WHY > > The extranal feedback trace must equal to CK len. Ok. This means that SDR= AM > will be clocked in phase with the FPGA system I think I can explain to this point. rest of question I don't know The DCM needs to "see" what the clock looks like at the memory, so it can adjust the phase accordingly, for this purpose whoever wrote that app notes thinking that the ext. feed back need to be same length as the CK lengthArticle: 151852
Hi, No idea about sysid...but you can investigate it...anyway there is a menu in EDS to say that is not needed to check it ...to avoid any problem with sysid... In my experience, if I remember well, I've seen this happening only when ram is not working properly...let me suppose...0x80000 is a ram address where your application is linked to??? Usually you link an application to start from base address of a "ram" inside your system...but before starting the processor the tools check what you have downloaded.... Is the link address correct?? Is the ram working??? If you have, actually, any problem with ram...insert an onchip ram in your design...build the memtest small template that comes with eds and check external ram for real problems... Carlo >Hello, > >I've been attempting to basically run through the mem_test template and >tutorial,on Cyclone® III EP3C120 chip board. > >I am able to compile the custom SOPC design, the encompassing Quartus file, >download the SRAM Object File .sof to the board correctly, create the >Application from BSP and Template, and even build the file in NIOS II with >no errors. The problem comes about when I attempt to run the system; the >.elf downloads in its entirety , but then fails during verification. > > >Verifying 08000000 ( 0%) >Verify failed between address 0x80000 and 0x08FFFF >Leaving target processor paused. > > > > >--------------------------------------- >Posted through http://www.FPGARelated.com > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151853
On May 24, 2:19=A0pm, "carlob" <carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it> wrote: > Hi, > No idea about sysid...but you can investigate it...anyway there is a menu > in EDS to say that is not needed to check it ...to avoid any problem with > sysid... > > In my experience, if I remember well, I've seen this happening only when > ram is not working properly...let me suppose...0x80000 is a ram address > where your application is linked to??? > > Usually you link an application to start from base address of a "ram" > inside your system...but before starting the processor the tools check wh= at > you have downloaded.... > Is the link address correct?? Is the ram working??? If you have, actually= , > any problem with ram...insert an onchip ram in your design...build the > memtest small template that comes with eds and check external ram for rea= l > problems... > > Carlo Not sure about the board you're using, but on my DE0 board, the code defaults to going into the largest RAM section (which of course is the SDRAM). So, if you're testing from 0x800000, you'll be overwriting the code itself. The memtest.c that comes with Quartus 10.1 allows you to specify a start and end address to test, so I was using 0x820000 to 0xf00000. Note that the top-end of ram is used for the stack, so you need to not overwrite part of that too. If you need to test all your ram, you'll need to set up an 8k+ on-chip RAM, and edit your BSP's linker-script to place the code in the smaller on-chip RAM. Then you'll have all the SDRAM to play with. SimonArticle: 151854
On May 24, 2:52=A0pm, colin <colin_toog...@yahoo.com> wrote: > On May 24, 9:39=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- > > > > > > > > > > darmstadt.de> wrote: > > shyam <mail.ghanashyam.pra...@gmail.com> wrote: > > > If on a bidirectional bus, if there is a strong pull up and there is = a > > > device which is drives the line low, can we reduce the fall time > > > substantially, if we reduce the pull up on the lines? > > > Or is it that the low overrides the pull up and does not affect fall > > > time at all? > > > Did you do the math? Did you try to simulate? > > > Take the Pull up current in relation to the low drive sink current... > > -- > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-d= armstadt.de > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > Let's give the poor guy a clue. > > What impedance is a driver designed to drive an edge into? If you > don't know what a transmission line is you are in it up to your neck. I am trying to analyze the behavior of the SD card data lines. According to the specifications, the SD card is supposed to drive the data at the falling edge of the clock and the host shall sample the data at the rising edge of the clock. Now I see that the data transition of line going low, happens 8ns after a falling edge. Now _assuming_ that the card uses a flip flop to drive the output line, I would imagine the clock to output to be anywhere between 2ns to 3ns. But I observe an 8ns clock to output. So I am not sure if it is the card that is at fault of driving the output so slow or is it the pull up on the line that is pulling the line hard to keep it 1 for a longer time. Thanks ShyamArticle: 151855
On May 24, 1:39=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > shyam <mail.ghanashyam.pra...@gmail.com> wrote: > > If on a bidirectional bus, if there is a strong pull up and there is a > > device which is drives the line low, can we reduce the fall time > > substantially, if we reduce the pull up on the lines? > > Or is it that the low overrides the pull up and does not affect fall > > time at all? > > Did you do the math? Did you try to simulate? There is no simulation that I am doing here. I have a board and am observing the behavior mentioned in my next post in reply to colin. The pullup is via a 10K resistor to a 3.3v supply line. Thanks Shyam > > Take the Pull up current in relation to the low drive sink current... > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 151856
> Hi, > No idea about sysid...but you can investigate it...anyway there is a menu > in EDS to say that is not needed to check it ...to avoid any problem with > sysid... > > In my experience, if I remember well, I've seen this happening only when > ram is not working properly...let me suppose...0x80000 is a ram address > where your application is linked to??? > > Usually you link an application to start from base address of a "ram" > inside your system...but before starting the processor the tools check what > you have downloaded.... > Is the link address correct?? Is the ram working??? If you have, actually, > any problem with ram...insert an onchip ram in your design...build the > memtest small template that comes with eds and check external ram for real > problems... > > Carlo > >> Hello, >> >> I've been attempting to basically run through the mem_test template and >> tutorial,on Cyclone® III EP3C120 chip board. >> >> I am able to compile the custom SOPC design, the encompassing Quartus > file, >> download the SRAM Object File .sof to the board correctly, create the >> Application from BSP and Template, and even build the file in NIOS II > with >> no errors. The problem comes about when I attempt to run the system; the >> .elf downloads in its entirety , but then fails during verification. >> >> >> Verifying 08000000 ( 0%) >> Verify failed between address 0x80000 and 0x08FFFF >> Leaving target processor paused. >> I had similar problem once. Even with "don't check sysid" feature marked, I couldn't download app. As I remember with Q10.0 or similar. What is located in this area from hardware side ? Program ram, flash , IO ? AdamArticle: 151857
On May 25, 4:19=A0am, shyam <mail.ghanashyam.pra...@gmail.com> wrote: > On May 24, 2:52=A0pm, colin <colin_toog...@yahoo.com> wrote: > > > On May 24, 9:39=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- > > > darmstadt.de> wrote: > > > shyam <mail.ghanashyam.pra...@gmail.com> wrote: > > > > If on a bidirectional bus, if there is a strong pull up and there i= s a > > > > device which is drives the line low, can we reduce the fall time > > > > substantially, if we reduce the pull up on the lines? > > > > Or is it that the low overrides the pull up and does not affect fal= l > > > > time at all? > > > > Did you do the math? Did you try to simulate? > > > > Take the Pull up current in relation to the low drive sink current... > > > -- > > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu= -darmstadt.de > > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > > Let's give the poor guy a clue. > > > What impedance is a driver designed to drive an edge into? If you > > don't know what a transmission line is you are in it up to your neck. > > I am trying to analyze the behavior of the SD card data lines. > According > to the specifications, the SD card is supposed to drive the data at > the > falling edge of the clock and the host shall sample the data at the > rising > edge of the clock. > > Now I see that the data transition of line going low, happens 8ns > after a > falling edge. Now _assuming_ that the card uses a flip flop to drive > the > output line, I would imagine the clock to output to be anywhere > between > 2ns to 3ns. But I observe an 8ns clock to output. So I am not sure if > it is > the card that is at fault of driving the output so slow or is it the > pull up > on the line that is pulling the line hard to keep it 1 for a longer > time. > > Thanks > Shyam To answer your original question, the fall time of an open collector/ drain is largely determined by the drive strength of the output and the capacitance of the line and input. There is some contribution by the pullup as any current through the pullup is not going through the capacitance, but with a value of 10 kohms it won't have much contribution. I can't say why the delay inside the SD card is 8 ns rather than 3 ns. But I would not read too much into it. This is a device designed for low power, not for high logic speed necessarily. How fast is the clock specified to operate? Is the 8 ns delay a significant portion of the clock cycle? RickArticle: 151858
On May 25, 1:19=A0am, shyam <mail.ghanashyam.pra...@gmail.com> wrote: > On May 24, 2:52=A0pm, colin <colin_toog...@yahoo.com> wrote: > > > > > > > On May 24, 9:39=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- > > > darmstadt.de> wrote: > > > shyam <mail.ghanashyam.pra...@gmail.com> wrote: > > > > If on a bidirectional bus, if there is a strong pull up and there i= s a > > > > device which is drives the line low, can we reduce the fall time > > > > substantially, if we reduce the pull up on the lines? > > > > Or is it that the low overrides the pull up and does not affect fal= l > > > > time at all? > > > > Did you do the math? Did you try to simulate? > > > > Take the Pull up current in relation to the low drive sink current... > > > -- > > > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu= -darmstadt.de > > > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > > Let's give the poor guy a clue. > > > What impedance is a driver designed to drive an edge into? If you > > don't know what a transmission line is you are in it up to your neck. > > I am trying to analyze the behavior of the SD card data lines. > According > to the specifications, the SD card is supposed to drive the data at > the > falling edge of the clock and the host shall sample the data at the > rising > edge of the clock. > > Now I see that the data transition of line going low, happens 8ns > after a > falling edge. Now _assuming_ that the card uses a flip flop to drive > the > output line, I would imagine the clock to output to be anywhere > between > 2ns to 3ns. But I observe an 8ns clock to output. So I am not sure if > it is > the card that is at fault of driving the output so slow or is it the > pull up > on the line that is pulling the line hard to keep it 1 for a longer > time. > > Thanks > Shyam- Hide quoted text - > > - Show quoted text - Why would you imagine what the timing would be instead of looking at a device datasheet to see what the real specifications are? Here's one example: http://www.stec-inc.com/downloads/flash_datasheets/SLSDxxxB_I_U61000-05203.= pdf In the high speed mode Table 13, the data output will occur between 2.5 to 14nS after the clock. Ed McGettigan -- Xilinx Inc.Article: 151859
Hi, Does anybody here have experience designing something to do PCIe over cable? I need to design (ie, draw the schematic of) a target device that will have a Molex cable/connector coming in, some Pericom or such equalizer chips, and an Altera Arria II GX45 FPGA. There are enough ways to mess this up that I'd sure like to have a consultant check what I'm doing for me. We plan to use a OneStop host-end board to drive the cable, in the customer's control computer. This will be 8-lane Gen1, so the electricals (PCB layout and such) shouldn't be too bad... if I connect the right things to the right things. jjlarkin atsign highlandtechnology dotthing comArticle: 151860
> >I had similar problem once. Even with "don't check sysid" feature >marked, I couldn't download app. Uhmmm..strange...10.0 bug??? >As I remember with Q10.0 or similar. >What is located in this area from hardware side ? Program ram, flash , IO ? > >Adam This is the best question...what is starting from 0x80000 and where do you link your sw...said in other way...which address your software starts from?? As somebody suggested...you cannot test a piece of ram where you are running your test code...pay attention.... Anyway in my opinion this is not the case....eds is not able to download correctly the code...if this is not related to sysid (I never experimented that problem so I cannot say) it should be related to memory problems or link address problems...check it.. If you are using a demo board with a standard project..I tend to exclude ram problems...the board and the netlist have been already checked before selling ...if you are using custom hw...ram could not be working...if you are using custom project..check againg your .sopc and, eventually, timing constraints for the ram...that can be the problem... Carlo --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151861
On May 25, 2:10=A0pm, "carlob" <carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it> wrote: > >I had similar problem once. Even with "don't check sysid" feature > >marked, I couldn't download app. > > Uhmmm..strange...10.0 bug??? I ran into this myself earlier today while I was trying to debug DMA. The problem (in my case) was that I'd forgotten to include the PLL that offsets the SDRAM (off-chip) clock from the cpu (on-chip) clock. The SDRAM would work intermittently, sometimes the download would succeed, sometimes it would fail. Adding the PLL solved this for me, although it didn't help me get DMA working :( I had to jump to Quartus2 v11 to get the DMA to successfully transfer data - what appeared to be the same design in 10.1 didn't work for me. SimonArticle: 151862
On May 25, 3:14=A0pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > Hi, > > Does anybody here have experience designing something to do PCIe over > cable? I need to design (ie, draw the schematic of) a target device > that will have a Molex cable/connector coming in, some Pericom or such > equalizer chips, and an Altera Arria II GX45 FPGA. There are enough > ways to mess this up that I'd sure like to have a consultant check > what I'm doing for me. > > We plan to use a OneStop host-end board to drive the cable, in the > customer's control computer. > > This will be 8-lane Gen1, so the electricals (PCB layout and such) > shouldn't be too bad... if I connect the right things to the right > things. > > jjlarkin > atsign > highlandtechnology > dotthing > com A PCIe extender? We bought and built some at my old place. http://www.samtec.com/ProductInformation/TechnicalSpecifications/overview.a= spx?series=3DPCIECArticle: 151863
On Wed, 25 May 2011 15:45:23 -0700 (PDT), a7yvm109gf5d1@netzero.com wrote: >On May 25, 3:14 pm, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> Hi, >> >> Does anybody here have experience designing something to do PCIe over >> cable? I need to design (ie, draw the schematic of) a target device >> that will have a Molex cable/connector coming in, some Pericom or such >> equalizer chips, and an Altera Arria II GX45 FPGA. There are enough >> ways to mess this up that I'd sure like to have a consultant check >> what I'm doing for me. >> >> We plan to use a OneStop host-end board to drive the cable, in the >> customer's control computer. >> >> This will be 8-lane Gen1, so the electricals (PCB layout and such) >> shouldn't be too bad... if I connect the right things to the right >> things. >> >> jjlarkin >> atsign >> highlandtechnology >> dotthing >> com > >A PCIe extender? We bought and built some at my old place. >http://www.samtec.com/ProductInformation/TechnicalSpecifications/overview.aspx?series=PCIEC What we're going to do is have the customer plug one of these http://www.onestopsystems.com/pcie_hib25_x8.php into his system, then run it through one of these http://www.molex.com/webdocs/datasheets/pdf/en-us/0745460802_CABLE_ASSEMBLIES.pdf then into a mating connector on our board. Then a couple of equalizer chips, then into the FPGA. I'm trying to piece together the puzzle. I've made an honest try at reading the Mindshare (mind-numbing) PCIe book, all 1047 pages of it, but it's very light on the hardware aspects, and don't even mention PCIe over cable. The index doesn't include the words "cable" or even "connector." PCIe is shockingly complex; I'm amazed it works at all. JohnArticle: 151864
On 26 Maj, 01:17, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > On Wed, 25 May 2011 15:45:23 -0700 (PDT), a7yvm109gf...@netzero.com > wrote: > > > > > > > > > > >On May 25, 3:14 pm, John Larkin > ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >> Hi, > > >> Does anybody here have experience designing something to do PCIe over > >> cable? I need to design (ie, draw the schematic of) a target device > >> that will have a Molex cable/connector coming in, some Pericom or such > >> equalizer chips, and an Altera Arria II GX45 FPGA. There are enough > >> ways to mess this up that I'd sure like to have a consultant check > >> what I'm doing for me. > > >> We plan to use a OneStop host-end board to drive the cable, in the > >> customer's control computer. > > >> This will be 8-lane Gen1, so the electricals (PCB layout and such) > >> shouldn't be too bad... if I connect the right things to the right > >> things. > > >> jjlarkin > >> atsign > >> highlandtechnology > >> dotthing > >> com > > >A PCIe extender? We bought and built some at my old place. > >http://www.samtec.com/ProductInformation/TechnicalSpecifications/over... > > What we're going to do is have the customer plug one of these > > http://www.onestopsystems.com/pcie_hib25_x8.php > > into his system, then run it through one of these > > http://www.molex.com/webdocs/datasheets/pdf/en-us/0745460802_CABLE_AS... > > then into a mating connector on our board. Then a couple of equalizer > chips, then into the FPGA. > > I'm trying to piece together the puzzle. I've made an honest try at > reading the Mindshare (mind-numbing) PCIe book, all 1047 pages of it, > but it's very light on the hardware aspects, and don't even mention > PCIe over cable. The index doesn't include the words "cable" or even > "connector." PCIe is shockingly complex; I'm amazed it works at all. > > John looked at something like this for inspiration? http://www.opalkelly.com/products/xem6110/ -LasseArticle: 151865
On Mon, 16 May 2011 21:02:44 -0700, "Mr.CRC" <crobcBOGUS@REMOVETHISsbcglobal.net> wrote: >Hi: > >Today I took scope shots of a clock input to my Xilinx Spartan 3e, >Digilent NEXYS2 board. The clock goes to a counter, simulating a >quadrature encoder, as explained in post "Counter clocks on both edges >sometimes, but not when different IO pin is used" on 5-13-2011. > >I have discovered that I'm dealing with a different animal here than >even the fastest logic chips I've grown comfortable with, the AC family. We were recently playing with a Spartan 3, to see how narrow a pulse we could count, using LVDS inputs feeding the first flop of a ripple counter. 1 ns seemed to work OK. We have seen slow input edges with a tiny amount of noise clock on the wrong edge. Even CCLK does this! Output edges are similarly screaming fast, sub-ns. One can also do serious amounts of logic and get jitter in the 10s of ps RMS. They should give us a slow+schmitt input option. JohnArticle: 151866
On 25 Mai, 22:14, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > Hi, > > Does anybody here have experience designing something to do PCIe over > cable? I need to design (ie, draw the schematic of) a target device > that will have a Molex cable/connector coming in, some Pericom or such > equalizer chips, and an Altera Arria II GX45 FPGA. There are enough > ways to mess this up that I'd sure like to have a consultant check > what I'm doing for me. You should get the PCIe-over-cable spec. The communication staff is actually rather simple. PCIe is surprisingly robust. But there are rather confusing hot plug signaling requirements. Regards, Kolja cronologicArticle: 151867
We are trying to implement a toplevel module which has an IN and an OUT port which are records. The synthesis works fine but we have the problem that synplify converts these record ports in a big port like "i_inputs[80:0]" instead of single ports like i_inputs.in0, i_inputs_flag, i_inputs.enable ... This way its impossible later to assign the pins of the FPGA in Designer to the correct port. Is there anyway or work around to solve this problem or to change this behaviour? Can the pins be assigned before synthesis? in the sdc file? And if it is possible which format do I use for the records? Thanks and congratulations for the forum, always source of solutions! --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151868
We have been running PCIe Gen1 with our Raggedstone2 Spartan-6 development boards over short ribbon cables and it is remarkably robust like other people have seen. We have not tried that yet with our Raggedstone3 Cyclone IV GX development boards yet but that is on the list to do. Proper PCIe cables e.g. http://www.tmcscsi.com/PCIe_cables.shtml?gclid=3DCO= yvzJX9hakCFUEb4QodPGjjkg should be pretty good. John Adair Enterpoint Ltd. On May 25, 9:14=A0pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > Hi, > > Does anybody here have experience designing something to do PCIe over > cable? I need to design (ie, draw the schematic of) a target device > that will have a Molex cable/connector coming in, some Pericom or such > equalizer chips, and an Altera Arria II GX45 FPGA. There are enough > ways to mess this up that I'd sure like to have a consultant check > what I'm doing for me. > > We plan to use a OneStop host-end board to drive the cable, in the > customer's control computer. > > This will be 8-lane Gen1, so the electricals (PCB layout and such) > shouldn't be too bad... if I connect the right things to the right > things. > > jjlarkin > atsign > highlandtechnology > dotthing > comArticle: 151869
On Thu, 26 May 2011 05:25:12 -0700 (PDT), Kolja Sulimma <ksulimma@googlemail.com> wrote: >On 25 Mai, 22:14, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> Hi, >> >> Does anybody here have experience designing something to do PCIe over >> cable? I need to design (ie, draw the schematic of) a target device >> that will have a Molex cable/connector coming in, some Pericom or such >> equalizer chips, and an Altera Arria II GX45 FPGA. There are enough >> ways to mess this up that I'd sure like to have a consultant check >> what I'm doing for me. > >You should get the PCIe-over-cable spec. Probably so. It's $1000. Or I can join the consortium, and get all the specs, for $3000. I think I can get my customer to pay for it! This money-for-specs thing is sort of annoying. JohnArticle: 151870
John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Thu, 26 May 2011 05:25:12 -0700 (PDT), Kolja Sulimma ><ksulimma@googlemail.com> wrote: > >>On 25 Mai, 22:14, John Larkin >><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>> Hi, >>> >>> Does anybody here have experience designing something to do PCIe over >>> cable? I need to design (ie, draw the schematic of) a target device >>> that will have a Molex cable/connector coming in, some Pericom or such >>> equalizer chips, and an Altera Arria II GX45 FPGA. There are enough >>> ways to mess this up that I'd sure like to have a consultant check >>> what I'm doing for me. >> >>You should get the PCIe-over-cable spec. > >Probably so. It's $1000. Or I can join the consortium, and get all the >specs, for $3000. I think I can get my customer to pay for it! > >This money-for-specs thing is sort of annoying. Nahh, just search on internet. Its out there for free! -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 151871
John, We've been using One Stop Systems ( http://www.onestopsystems.com/ ) - Gen1 and Gen2 PCIe cables, host adapters, and express cards. Thanks, Evgeni http://outputlogic.comArticle: 151872
On Thu, 26 May 2011 12:00:00 -0700 (PDT), OutputLogic <evgenist@gmail.com> wrote: >John, > >We've been using One Stop Systems ( http://www.onestopsystems.com/ ) - >Gen1 and Gen2 PCIe cables, host adapters, and express cards. > >Thanks, >Evgeni >http://outputlogic.com My customer plans to use their XMC board to drive their end of the cable. JohnArticle: 151873
Hello Guys, I am working with Synplify Pro. I have a RTL wrapper in Verilog where a module is instantiated. But this module is available as an EDF netlist. How can I include this EDF netlist in my Synplify project so that it can be integrated with the wrapper RTL without any compilation error? Best regards, Rahul --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151874
On May 25, 4:17=A0pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > On Wed, 25 May 2011 15:45:23 -0700 (PDT), a7yvm109gf...@netzero.com > wrote: > > > > > > > > > > >On May 25, 3:14=A0pm, John Larkin > ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >> Hi, > > >> Does anybody here have experience designing something to do PCIe over > >> cable? I need to design (ie, draw the schematic of) a target device > >> that will have a Molex cable/connector coming in, some Pericom or such > >> equalizer chips, and an Altera Arria II GX45 FPGA. There are enough > >> ways to mess this up that I'd sure like to have a consultant check > >> what I'm doing for me. > > >> We plan to use a OneStop host-end board to drive the cable, in the > >> customer's control computer. > > >> This will be 8-lane Gen1, so the electricals (PCB layout and such) > >> shouldn't be too bad... if I connect the right things to the right > >> things. > > >> jjlarkin > >> atsign > >> highlandtechnology > >> dotthing > >> com > > >A PCIe extender? We bought and built some at my old place. > >http://www.samtec.com/ProductInformation/TechnicalSpecifications/over... > > What we're going to do is have the customer plug one of these > > http://www.onestopsystems.com/pcie_hib25_x8.php > > into his system, then run it through one of these > > http://www.molex.com/webdocs/datasheets/pdf/en-us/0745460802_CABLE_AS... > > then into a mating connector on our board. Then a couple of equalizer > chips, then into the FPGA. > > I'm trying to piece together the puzzle. I've made an honest try at > reading the Mindshare (mind-numbing) PCIe book, all 1047 pages of it, > but it's very light on the hardware aspects, and don't even mention > PCIe over cable. The index doesn't include the words "cable" or even > "connector." PCIe is shockingly complex; I'm amazed it works at all. > > John I own a Magma PCI bus extender, which sounds similar to your project. DigiDesign on the peninsula used to use them extensively in digital sound recording before multichannel cards existed. It is a grossly overpriced product, but it you need one, you pay the piper. http://www.magma.com/ Maybe they can OEM something for you. Just don't expect it to be cheap. Incidentally, windows and linux recognize the bus extender without a hitch. No driver issues at all.
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