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Frank van Eijkelenburg wrote:
> Can you tell me what the location of your eclipse workspace is?
DRIVE_ROOT
\_work
\_project_name
\_FPG
| \_software (nios II software)
| | \_syslib (location of syslib source)
| | \_application (location of application source)
| \_synth (location of Quartus source and .PTF)
\_workspace (workspace directory)
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
Article: 110101get from Xilinx website http://www.xilinx.com/bvdocs/appnotes/xapp730.zip unzip, then look in /pcores/microblaze_4_00_a/hdl/vhdl that looks like true unscrambled RTL source of the MicroBlaze !? Or am I seeing wrong ? AnttiArticle: 110102
Mark McDougall wrote: > Frank van Eijkelenburg wrote: > >> Can you tell me what the location of your eclipse workspace is? > > DRIVE_ROOT > \_work > \_project_name > \_FPG > | \_software (nios II software) > | | \_syslib (location of syslib source) > | | \_application (location of application source) > | \_synth (location of Quartus source and .PTF) > \_workspace (workspace directory) > > Regards, > Many thanks Mark (also for the quick reponse :) , Finally it's working now. I had some conflicts in creating the projects in combination with the workspace location. best regards, FrankArticle: 110103
On 11 Oct 2006 02:25:26 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >get from Xilinx website > >http://www.xilinx.com/bvdocs/appnotes/xapp730.zip > >unzip, then look in /pcores/microblaze_4_00_a/hdl/vhdl > >that looks like true unscrambled RTL source of the MicroBlaze !? > >Or am I seeing wrong ? > >Antti It really seems. Nice! ZaraArticle: 110104
"David Brown" <david@westcontrol.removethisbit.com> wrote in message news:452c982b$0$16505$8404b019@news.wineasy.se... >> >> I believe the reason is that you can convert the "free" edition into >> the "full" edition by buying a license with no need to do a full >> reinstall. However, I understand there are some problems with that >> approach. >> > > Personally, I don't see why they have a licensing system at all, even on > the full package, or why they charge for the full package. It would be > much easier for users if the FPGAs cost very slightly more (to be fair, > the increase should be on larger FPGAs, and only when bought in small > quantities), and the software should be free. I fully understand why > Altera would like it to be registered in some way, and to track who is > using it, but letting users use it freely would remove all the hassles > associated with licensing, node locks, battles with "FlexLM", moving > computers, and so on. In recent times I've had a couple of customers > battle with licensing issues (not with any FPGA-related software) - the > wasted time and effort has cost far more than the software licenses in the > first place. Maybe because there are companies like Synplicity and Mentor Graphics that sell tools that are not vendor specific and do not sell parts. When Microsoft bundles things in and 'gives things away' people rant about how they drive the independent software vendors out of business....a similar argument would likely apply here. Altera, Xilinx, Synplicity, Mentor Graphics et al pay out hard cash to provide software tools and all expect some return on that investment in some form (either directly from the tool or indirectly through parts or both). If one (or more) of the parts guys gives the tools away it can probably be construed by the legal eagles in Washington as a tactic to drive a competitor out of business thus deserving of some close and unprofitable scrutiny. Obviously they can get away with giving limited versions of the tool away; I'm sure Synp and Ment would prefer to make money off of those as well but apparently the perceived loss in revenue is not considered to be worth trying to recoup via the legal system, anti-trust laws, that sort of approach. Just my speculation. KJArticle: 110105
Austin I have a coolrunner II with some pins which are functionaly (after programming) SSTL. I want to perform boundary scan (interconnect) testing and I want to know whether the CPLD will do it using SSTL or CMOS logic levels on these pins. I am aware that CMOS levels will work but for marketing reasons it would be much better if they were SSTL. I talked about BSDLANNO because xilinx support said that once a pin is used as an input or output that is all it will do during boundary scan but the BSDLANNO documentation and a quick experiment on my part says otherwise. (I created a design with pinA <= pinB and created a BSDL file) I understand why you might think I was talking about the JTAG port itself but curiously despite a lengthy first email in my webcase they thought I meant the jtag port as well. Colin Austin Lesea wrote: > Colin, > > Are you trying to interface to the JTAG port using SSTL drivers and > receivers? If so, then this is an interfacing question (and one that > can be answered in 60 seconds with a simulator), and really has nothing > to do with boundary scan at all. > > If you post the part family (eg Spartan 3E), and the SSTL interface > class and supply voltages, I can run the simulation, and see if it works. > > AustinArticle: 110106
daughenbaugh@gmail.com schrieb: > Ray Andraka wrote: > > trust me, "Open" is better than "closed" with the notation of something > > like "will be addressed in next major release". Once they get a CR > > assigned, they go into a black hole. > > I agree. But I have an even bigger complaint about the whole webcase > system. > > We use a lot of Xilinx parts, and occasionally we run into problems. > We generally only use webcase as a last resort, as I hate to clog up > their system with simple cases. So sometimes we find a problem and a > work-around ourselves. This information should be valuable to Xilinx, > so I open a case to tell them this. My frustration is that the basic > response is "So you have a work-around? Case closed!" This info goes > into the same black hole. > > My most recent example: > > We are using a lot of spartan 3E parts, with the BPI mode configuration > - which is awesome for our application. The early parts (stepping 0) > had an issue where JTAG configuration would fail if the FPGA is set to > BPI mode and the attached memory had a valid bitstream. The datasheet > says that this has been fixed in stepping 1. We have never had any > stepping 0 devices so we ignored this issue, but it turns out that it > is still present in stepping 1. This wasted a lot of our time until we > figured out what was going on. Xilinx has two suggested work arounds, > which both work, but weren't good for our application. Now we are in > production and the JTAG interface is not needed (as it was used for > development only), so this is no longer an issue for us. I figured > that Xilinx would like to know that this issue was not fixed in > stepping 1, and that they still have an issue with their silicon, so I > opened a webcase. But I basically got the response I mentioned > previously: > "So this isn't a problem for you? Case Closed!" > > I opened the case in August, and the engineer ran an example design > himself and then ended the case with: > > "I let the Spartan group know that this problem still exists in > Stepping 1 parts. They are looking into why this is not fixed. Since > you are ok with the workaround and expressed that this is not a > problem. I am going to go ahead and close this case. Please feel free > to open up additional cases if need be. Thank you." > > No, it isn't a problem for us, anymore, but there should be some sort > of errata posted ASAP so that other customers do not run into the same > problems we did. I gave it some time, but I still don't see anything, > so I am posting here. > > Xilinx's system is broken, as they have no good means for customer > feedback. So I am hoping that comp.arch.fpga might work better than > webcase? > > Jason Daughenbaugh > http://www.advanced.pro JTAG BPI S3E issue - there is a solution that fixes the problem the external flash memory can be put into status read mode using CFI commands and boundary scan, then the JTAG can be used to work with the FPGA as if there S3e bug wasnt there. Its a bit tricky but working solution. AnttiArticle: 110107
Hi, With all this talk of sync resets, I was curious: 1. If you apply reset async and de-assert sync, does this signal automatically get distributed using the FPGA's global reset resources (GSR for Xilinx, Global for Altera)? Are there any hidden gremlins with this technique (aside from not filtering glitches on the reset input pin) ? 2. Do all modern FPGAs have flops with synchronous reset inputs? Or does it even matter? I'm thinking in the case of a purely synchronous reset, you might want to avoid any nebulousness by NOT using the async reset, even if your reset signal is fully synchronized. John.Article: 110108
Zara wrote: > On 11 Oct 2006 02:25:26 -0700, "Antti" <Antti.Lukats@xilant.com> > wrote: > > >get from Xilinx website > > > >http://www.xilinx.com/bvdocs/appnotes/xapp730.zip > > > >unzip, then look in /pcores/microblaze_4_00_a/hdl/vhdl > > > >that looks like true unscrambled RTL source of the MicroBlaze !? > > > >Or am I seeing wrong ? > > > >Antti > > > It really seems. Nice! > So, will someone be getting a telling off later today, or are Xilinx following Lattice's lead? Cheers, JonArticle: 110109
Brannon wrote: > 7. Is Xilinx making its money on software or hardware? If it is not > making money on software, then consider making it open source. More > eyes on the code mean more speed. This is not just a Xilinx problem. Across the industry slow poor tools have resulted from tight fisted IP policies regarding FPGA internal design and routing data bases to build bit streams. High cost, low performance. And it means the tools are limited by the creativity and (lack of) experience of the vendors in house tools programmers. A mix of NIH and paranioa over disclosure are self defeating in selling FPGA chips in high volume. We hear complaints by the vendor that they don't have unlimited resources and must focus on selected key customer needs (AKA high volume customers demands). This same lack of resources has prevented innovative redesign of the tools to take advantage of multicore processors and cluster technologies. More importantly, the vendor doesn't have a broad systems view of their own products, and has failed to capitalize on building low cost design systems which are representive of the very market they are feeding .... FPGA centric designs. Consider that a well executed motherboard built around multiple FPGA's with PPC CPU cores could easily have far more place and route performance than any equivalently priced PC workstation by using the FPGA's as high speed parallel coprocessing routing engines. This isn't a new idea .... see http://www.cs.caltech.edu/research/ic/pdf/fastroute_fpga2003.pdf That they block both 3rd parties and open source from having access to the FPGA internals and tools internals means their customers are limited to what tools their limited resource development teams can cobble togather. With a more open disclosure, it would be interesting to see what both open source and for-profit 3rd parties could do to make a market out of providing high performance FPGA tools and integrated development systems with FPGA assisted routing.Article: 110110
Antti wrote: > get from Xilinx website > > http://www.xilinx.com/bvdocs/appnotes/xapp730.zip > > unzip, then look in /pcores/microblaze_4_00_a/hdl/vhdl > > that looks like true unscrambled RTL source of the MicroBlaze !? > > Or am I seeing wrong ? > > Antti > Yes it is as the RTL VHDL source of the Xilinx Microblaze. Publish Error from Xilinx ? Regards, Laurent ________________________ Amontec http://www.amontec.com New JTAG solution: JTAGkey-Tiny @ €29.-Article: 110111
vittal wrote: > Hi , > I need either the ARMv6 ISA or the ARMv7-A ISA doc. > Please help http://www.arm.com/documentation/ Cheers, JonArticle: 110112
Hey man I already tried it. but i couldnt get any detailed ISA. I got only quick reference cards. and many links are not working ,they are broken links. Jon Beniston wrote: > vittal wrote: > > Hi , > > I need either the ARMv6 ISA or the ARMv7-A ISA doc. > > Please help > > http://www.arm.com/documentation/ > > Cheers, > JonArticle: 110113
David, I don't have the hardware yet, so, I'm just doing simulations. It will take more 3 to 4 months for the prototype board, but I'm trying to catch early designs faults. (Actually I'm doing everything, hardware, software and pre-layout, and a lot of times I have to stop and do other things!) At simulations, it worked (using auxiliary signals as that LOAD_ADDR), but I want a robust, clear and as simple as possible design. So I asked for some guide lines/ideias. I'll share the results when I have them. Luiz CarlosArticle: 110114
Hi Mordehay, I haven't tried this myself but you should be able to import two EDK system into a ISE project. You can't have two .bmm but you could merge them into a common .bmm. In a .bmm file there is the hierarchical path to the BRAMs so they should be possible to merge as long the paths are different. Göran <me_2003@walla.co.il> wrote in message news:1160487896.970522.203900@i3g2000cwc.googlegroups.com... Hi Goran, I did not understood your answer.. Do you mean that I need to create a system which contains two microblaze instances and afterwards export it to the ISE ? What if I want to have these two microblazes in two different systems and afterwards export them to ISE separately (my top.vhd will contain two system (microblaze) instances ? Can I do it ? Can I use two BMM files in that case ? Thanks in advance, Mordehay. Göran Bilski wrote: > Just add the 2nd MicroBlaze in the XPS tool. > > Göran Bilski > > <me_2003@walla.co.il> wrote in message > news:1160296753.788965.57640@m73g2000cwd.googlegroups.com... > > Hi all, > > I have a microblaze processor that I've built using the EDK and > > afterwards simulated and it seems to work fine. Now I need to make two > > instances of this Microblaze system in my design. > > Can I use the same module and instantiate it twice or I maybe I need to > > make a copy of the system and name it differently. If I instance the > > same module twice I figured out that it will be problematic to fill the > > BRAM with code data. > > Can anyone help ? > > Thanks, Mordehay. > >Article: 110115
> process(ALE, WRITE#) > if (ALE = '1') then > addr <= dtadd; > elsif rising_edge(WRITE#) then > addr <= addr + 1; > end if; > end process; Marlboro, This means that the CLB storage must have flip-flop and latch behavior at the same time, and I think it's not possible. When it's a flip-flop you can have preset/clear input, but it is preset or clear. Well, looking at the datasheet I found that "rev" input, I need to read more about it. Luiz CarlosArticle: 110116
KJ wrote: > "David Brown" <david@westcontrol.removethisbit.com> wrote in message > news:452c982b$0$16505$8404b019@news.wineasy.se... > >> > >> I believe the reason is that you can convert the "free" edition into > >> the "full" edition by buying a license with no need to do a full > >> reinstall. However, I understand there are some problems with that > >> approach. > >> > > > > Personally, I don't see why they have a licensing system at all, even on > > the full package, or why they charge for the full package. It would be > > much easier for users if the FPGAs cost very slightly more (to be fair, > > the increase should be on larger FPGAs, and only when bought in small > > quantities), and the software should be free. I fully understand why > > Altera would like it to be registered in some way, and to track who is > > using it, but letting users use it freely would remove all the hassles > > associated with licensing, node locks, battles with "FlexLM", moving > > computers, and so on. In recent times I've had a couple of customers > > battle with licensing issues (not with any FPGA-related software) - the > > wasted time and effort has cost far more than the software licenses in the > > first place. > > Maybe because there are companies like Synplicity and Mentor Graphics that > sell tools that are not vendor specific and do not sell parts. When > Microsoft bundles things in and 'gives things away' people rant about how > they drive the independent software vendors out of business....a similar > argument would likely apply here. > > Altera, Xilinx, Synplicity, Mentor Graphics et al pay out hard cash to > provide software tools and all expect some return on that investment in some > form (either directly from the tool or indirectly through parts or both). > If one (or more) of the parts guys gives the tools away it can probably be > construed by the legal eagles in Washington as a tactic to drive a > competitor out of business thus deserving of some close and unprofitable > scrutiny. Obviously they can get away with giving limited versions of the > tool away; I'm sure Synp and Ment would prefer to make money off of those as > well but apparently the perceived loss in revenue is not considered to be > worth trying to recoup via the legal system, anti-trust laws, that sort of > approach. > > Just my speculation. > > KJ I believe it is a bit more strategic than that. Consider that Microsoft practically gives away Windows and Office to universities, with the expectation that most of those new grads will have used the software during their studies. Now, consider those same college students when they get to the point where buying decisions are made. Will they go with Microsoft products, or something else? No, I think Altera and Xilinx give away the low-end stuff so that students and hobbiests will get exposure to their products. After all, if the price of entry is > $3k, how many college's, much less students, will be able to provide a reasonable number of seats to do FPGA designs? Also, the best students are going to want to do some work at home, and most are certainly NOT going to be able to afford the full Quartus or ISE package. With both Xilinx and Altera giving away low-end versions of the software, those students can now choose either, or both, to try out at home. The cost of development boards becomes the next issue. (Xilinx is still winning this one) Thus, the free software is almost a promotional expense for the FPGA vendors. It gives people a taste of what's available, and (hopefully) gives the users a good impression. Perhaps it's better that they have the same licensing restrictions in a sense. It prevents perception problems later, when you have a real license, and can't move it between PC's.Article: 110117
Hello, a look at the Xilinx "online" shop or other Xilinx sources shows that the Product line of Spartan 3E still shows gaps. While e.g. the datasheet shows both the XC3S100E and XC3S250E planned in TQ144, only the XC3S100E is available yet. Same for 250/500 in PQ208. This defeats migration from one size to another. Is there any (reliable) roadmap when the gaps will be filled? Something like TI's product pages, showing inventory and production status, would be highly welcome! Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 110118
G=F6ran Bilski schrieb: > Hi Mordehay, > > I haven't tried this myself but you should be able to import two EDK syst= em > into a ISE project. > You can't have two .bmm but you could merge them into a common .bmm. > In a .bmm file there is the hierarchical path to the BRAMs so they should= be > possible to merge as long the paths are different. > > G=F6ran If you just add two XPS instances to ISE then it says: "Two instances detected, only one is allowed" and doesnt proceed. this is when you use normal flow where you just have XPS system as submodule in ISE if you add the stub.vhd manually (And not the XMP file) maybe it want complain so much then AnttiArticle: 110119
> a look at the Xilinx "online" shop or other Xilinx sources shows that the > Product line of Spartan 3E still shows gaps. While e.g. the datasheet > shows > both the XC3S100E and XC3S250E planned in TQ144, only the XC3S100E is > available yet. Same for 250/500 in PQ208. This defeats migration from one > size to another. The 250K gate in PQ208 is shipping, I have 100 of them sitting here in a box. Paul S.Article: 110120
Antti wrote: > JTAG BPI S3E issue - there is a solution that fixes the problem > the external flash memory can be put into status read mode using > CFI commands and boundary scan, then the JTAG can be used to > work with the FPGA as if there S3e bug wasnt there. Its a bit tricky > but working solution. I like your solution. Clever! Does this mean that you ran into this problem too? Do you see it with Stepping 1 as well? JasonArticle: 110121
oen_br wrote: > > process(ALE, WRITE#) > > if (ALE = '1') then > > addr <= dtadd; > > elsif rising_edge(WRITE#) then > > addr <= addr + 1; > > end if; > > end process; > > Marlboro, > > This means that the CLB storage must have flip-flop and latch behavior > at the same time, and I think it's not possible. When it's a flip-flop > you can have preset/clear input, but it is preset or clear. Well, > looking at the datasheet I found that "rev" input, I need to read more > about it. > > Luiz Carlos Good point, I guess the synthesizer will "decode" the combine logic of dtadd & ALE and feed outputs to async R/P of the flipflops... For example R(0) = ALE and not(dtadd(0)), P(0) = ALE and dtadd(0)...Article: 110122
Brannon wrote: > 7. Is Xilinx making its money on software or hardware? If it is not > making money on software, then consider making it open source. More > eyes on the code mean more speed. As a side note, it's not either/or between being a hardware or software company. Most major Open Source products are staffed with paid developers from multiple supporting For-Profit companies to leverage industry development dollars as far as possible. Linux exists as a viable commercial product because of hundreds of millions of dollars in salaries paid by many (MANY) large hardware and software corporations to develop the product. They did this to get out of the other extreme, which is everyone having a mediocre product due to limited development dolars because everyone was reinventing the same wheel, and claiming theirs was somehow better. A For-Profit project (UNIX) changed that model, and had everyone supporting a common UNIX development goal, which over time, out grew UNIX and became OpenSource in a number of UNIX clone forms. Pooling paid labor from both FPGA/PLD companies, and major end user companies with inhouse EDA programmers, plus educational and volunteer labor does over time generate a better product. Mostly because of the professional paid developers that are mutually committed to making it the best for THIER companies use and sale.Article: 110123
Ben Twijnstra wrote: > Michael Kraemer wrote: > > > Actually I cannot understand why Altera is so generous to give away > > this software for free, which I appreciate a lot, and then attach such > > restrictions. Anyway, this is perhaps the wrong question if one gets > > something for free. > > > > Well, it's not entirely Altera's fault. The FlexLM license software they > _link_ (i.e. they don't have the source code) in has a function that > queries the validity of a certain feature name based on the feature name, > the current date, software version etc. The linked-in FlexLM bit then > refuses to validate _ANY_ feature if the system clock has been set back, > and there you go. > > On the other hand, many customer calling me with this problem tend to find > some bug in their overall system (network, application, whatever), so from > a sysadmin standpoint it could actually be positive that this check is > there (ducks and runs). > > In the past I have questioned Altera Tools Marketing's decision to have a > license check in the Free Edition at all, but I do understand their reasons > for it - they want to know which sites are active and which ones are not. > > Best regards, > > > > Ben Also, when the Quartus web edition is "free," my license file is only good for 6 months and must renew it afterwards. I guess Altera can pull the plug any time if they decide to do so. S. C.Article: 110124
Ben Twijnstra wrote: > Michael Kraemer wrote: > > > Actually I cannot understand why Altera is so generous to give away > > this software for free, which I appreciate a lot, and then attach such > > restrictions. Anyway, this is perhaps the wrong question if one gets > > something for free. > > > > Well, it's not entirely Altera's fault. The FlexLM license software they > _link_ (i.e. they don't have the source code) in has a function that > queries the validity of a certain feature name based on the feature name, > the current date, software version etc. The linked-in FlexLM bit then > refuses to validate _ANY_ feature if the system clock has been set back, > and there you go. > > On the other hand, many customer calling me with this problem tend to find > some bug in their overall system (network, application, whatever), so from > a sysadmin standpoint it could actually be positive that this check is > there (ducks and runs). > > In the past I have questioned Altera Tools Marketing's decision to have a > license check in the Free Edition at all, but I do understand their reasons > for it - they want to know which sites are active and which ones are not. > > Best regards, > > > > Ben Also, when the Quartus web edition is "free," my license file is only good for 6 months and must renew it afterwards. I guess Altera can pull the plug any time if they decide to do so. S. C.
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