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On Mon, 09 Oct 2006 08:55:58 -0700, Austin Lesea <austin@xilinx.com> wrote: >Rajeev, > >Xilinx takes seriously any suggestions. > >We, of all people, with the introduction of the Virtex 5 LX330, know >that we need to somehow make everything work better, and faster. > >Note that due to the memory required, the LX330 can ONLY be complied on >a 64 bit Linux machine.... there are just too many logic cells, and too >much routing. 8 Gbytes is about what you need, and windoze can't handle >it (at all). Austin, you are mistaken. There has been a 64 bit version of windows for more than a year now and a new updated version is going to be released before the end of the year (Vista is in RC2 stage now). Looking forward to a 64 bit version of ISE on Vista 64 which I am running now. From henrik.kirneh@gmail.com Mon Oct 09 10:29:27 2006 Path: newssvr25.news.prodigy.net!newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!news.linkpendium.com!news.linkpendium.com!news.banetele.no!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Message-Id: <452a86f7$0$49197$14726298@news.sunsite.dk> From: Henrik Pedersen <henrik.kirneh@gmail.com> Subject: Re: Xilinx-Modelsim on Linux Newsgroups: comp.arch.fpga Reply-To: henrik.kirneh@gmail.com Date: Mon, 09 Oct 2006 19:29:27 +0200 References: <452939b3$0$49200$14726298@news.sunsite.dk> <1160330147.727925.97230@m73g2000cwd.googlegroups.com> <45294c9d$0$49204$14726298@news.sunsite.dk> <1160345129.433745.192090@i42g2000cwa.googlegroups.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8Bit Lines: 12 Organization: SunSITE.dk - Supporting Open source NNTP-Posting-Host: 217.116.244.170 X-Trace: news.sunsite.dk DXC=FcFRWLMYmfo`;IS0i7S8TaYSB=nbEKnkkZ\2W;M6kDQoYDoQ\kQ?kDd^PgABlB42EoIHQFW\gATbk1VYSn^jGTgdGX_hS]faD:c^E3K5gcDldj X-Complaints-To: staff@sunsite.dk Xref: prodigy.net comp.arch.fpga:120937 GaLaKtIkUs™ wrote: > comxlib --s mti_se -arch all -l all -lib all -w [root@p1800 bin]# find / -name comxlib [root@p1800 bin]# Have'nt got that file. Should it be run under vine ? Henrik From henrik.kirneh@gmail.com Mon Oct 09 10:33:19 2006 Path: newssvr25.news.prodigy.net!newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!pd7cy3no!shaw.ca!border2.nntp.dca.giganews.com!nntp.giganews.com!news.maxwell.syr.edu!uio.no!news.banetele.no!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail Message-Id: <452a87df$0$49197$14726298@news.sunsite.dk> From: Henrik Pedersen <henrik.kirneh@gmail.com> Subject: Re: Xilinx-Modelsim on Linux Newsgroups: comp.arch.fpga Reply-To: henrik.kirneh@gmail.com Date: Mon, 09 Oct 2006 19:33:19 +0200 References: <452939b3$0$49200$14726298@news.sunsite.dk> <1160330147.727925.97230@m73g2000cwd.googlegroups.com> <45294c9d$0$49204$14726298@news.sunsite.dk> <452959c1$0$5542$ba620e4c@news.skynet.be> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8Bit Lines: 48 Organization: SunSITE.dk - Supporting Open source NNTP-Posting-Host: 217.116.244.170 X-Trace: news.sunsite.dk DXC=J;L?Zk@dC[fE406ddB4h2jYSB=nbEKnkkZ\2W;M6kDQoYDoQ\kQ?kDd^PgABlB42EoIHQFW\gATbk1VYSn^jGTgdGX_hS]faD:c^E3K5gcDldj X-Complaints-To: staff@sunsite.dk Xref: prodigy.net comp.arch.fpga:120938 Sylvain Munaut wrote: > Henrik Pedersen wrote: >> GaLaKtIkUs? wrote: >> >>> Hi, >>> After you got the libraries compiled using the compxlib tool (included >>> in ISE), you shouldn't get any trouble. >>> Please precise the exact problem you encountred >>> >>> >>> On Oct 8, 9:47 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote: >>>> Hey there >>>> >>>> I have a lot of trouble finding directions/guides/manuals on how to get >>>> subject working. >>>> >>>> Anyone able to point me in the right direction ? >>>> >>>> Henrik >> >> I'm a step further from that. >> What libs should i compile. >> >> Let me resume for a moment. >> Downloaded WebPack 8,2,03i and installed it. >> Done a few recomended jumps and it works. >> >> When i click "Simulate Behavorial" i get a error saying: >> Model technologies vsim cannot be found be Project navigator. .... >> >> Where do i start ? > > Contact modeltech to buy modelsim ... > > The free/limited modelsim-XE doens't exists for linux, so you need the > full one. But you could use the included ISE simulator. In your project > settings or global preferences, there should be an option to select your > simulation tool. > > > Sylvain Tried using that instead and got this far: Building mod_Timers_isim_beh.exe ERROR:Simulator:222 - Generated C++ compilation was unsuccessful HenrikArticle: 110001
mk, How well does it deal with memory? Can you place 16 or 32 Gbytes in the box? Austin mk wrote: > On Mon, 09 Oct 2006 08:55:58 -0700, Austin Lesea <austin@xilinx.com> > wrote: > >> Rajeev, >> >> Xilinx takes seriously any suggestions. >> >> We, of all people, with the introduction of the Virtex 5 LX330, know >> that we need to somehow make everything work better, and faster. >> >> Note that due to the memory required, the LX330 can ONLY be complied on >> a 64 bit Linux machine.... there are just too many logic cells, and too >> much routing. 8 Gbytes is about what you need, and windoze can't handle >> it (at all). > > Austin, you are mistaken. There has been a 64 bit version of windows > for more than a year now and a new updated version is going to be > released before the end of the year (Vista is in RC2 stage now). > Looking forward to a 64 bit version of ISE on Vista 64 which I am > running now.Article: 110002
Austin Lesea schrieb: > mk, > > How well does it deal with memory? > > Can you place 16 or 32 Gbytes in the box? Much more important question. How mature is it? The Xilinx software itself makes trouble enough. Adding a very beta stage operating system will bring a lot of "fun" to the software guys. Regards Falk P.S. Woh a bit the suggested partioning. Incremental design is a must at this level of size/complexity. You dnot take a big staircase in one step, dont you? Unless you fall down ;-)Article: 110003
On 9 Oct 2006 09:27:57 -0700, "KJ" <Kevin.Jennings@Unisys.com> wrote: > >Bob Perlman wrote: >> >Like I said, I don't discount that there may be these cases...but have yet >> >to hear anyone actually name a specific case where the clock isn't running >> >but a specific reset condition is required. >> > >> >Can anyone actually provide one? Hard to believe that such a case doesn't >> >exist, but also hard to believe that one hasn't been articulated >> >either....oh well. >> >> How about TriState contention? If I'm controlling TriState buffers >> with FFs that aren't initialized until the clock comes along, I run >> the risk of turning on more than one set of TriStates on a signal or >> bus. And when you're using high-current drivers, this can cause >> smoke; I've seen it. >> >Those must be some hefty drivers if they can cause smoke in the >probably only a couple of milliseconds between when reset gets released >until the clock starts running (assuming that reset was even released >first, typically I wouldn't do that). The drivers I'm referring to are chips like the ones you'd find in the 74ABT and 74LVT families. If memory serves, they source 32 mA HIGH and sink 64mA LOW. If you have one 16-output buffer chip contending with another, believe me, you will burn at least one of them out, and it won't take long. And if you somehow manage to keep the contention short enough to avoid burning them out immediately, you will shorten their lives. This is not conjecture; I've seen it happen in actual hardware. I used to help design ultrasound machines, and I learned that if you want to get a physician mad, make smoke come out of something his clinic just paid $200K for. They are touchy like that. As for releasing the reset after the clock starts running, yes, that's what you want to do. But how does that prevent contention if the resets are purely synchronous? You could gate every TriState enable with the reset, but that slows down the enable path. Or you could rely on the end-of-configuration reset to initialize the TriState controls, but that's just another form of asynchronous reset. And what if the clock doesn't start? It's OK for the system to malfunction if the clock doesn't come up, but it's considered bad form for the system to destroy itself. > I've seen bus driver TTL type >devices, which are relatively hefty drivers, shorted for several weeks >while waiting for the short on the board to be found and fixed without >any smoke occurring and marveled that devices can take such abuse and >still work. Probably cut into the shelf life of that board a bit but >this was an engineering prototype. It's amazing how much you can abuse hardware and still have it function, but that doesn't mean that hardware abuse is a good idea. I, too, have seen single chip outputs shorted for long periods of time without destroying the driver, but when you short multiple high-current outputs, all bets are off. And low-drive outputs aren't a guarantee of trouble-free contention, either. In one system I worked on, we had a TriState bus with a RAM on it, and the RAM's TriState enable was under software control. Unfortunately, the software guys weren't aware that they were supposed to disable the RAM at startup, resulting in a brief period of contention every time the system booted. The RAM drivers were pretty weak, maybe 4mA, so you wouldn't suspect that'd be a problem, but we started getting boards back from the field with bad RAMs after 8 or 9 months. Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 110004
KJ wrote: > Peter Alfke wrote: > > Output tristate in Xilinx FPGAs is driven by a flip-flop. > > Peter Alfke > > Guess I won't be able to implement anything resembling a > 74xx244/374/etc. type of external interface in a Xilinx FPGA then ;) > We have got to wean ourselves away from the 30-year old 7400-MSI definitions. These circuits were defined as tiny sub-modules. Today's FPGAs take a higher perspective, and implement certain functions differently (=smarter). It hurts to say something negative about 7400-MSI. Defining, applying, and promoting it was my job in the early 'seventies. But that's a long time ago... Peter AlfkeArticle: 110005
What seems to be the problem? Before and during configuration all Xilinx FPGA outputs are tristated. During configuration, the 3-state-controlling flip-flop can and should be asynchronously held reset. It is only after the clock has started and the application runs that the output can become active, if the user wants that to happen. Where is the touchy problem? Just to support Bob: A 64-mA output sinks 64 mA at 0.4 V. And that is guaranteed worst case. At nominal conditions it may behave not as an 8 Ohm, but rather as a 3 to 4 Ohm resistor. Easy to smoke in a multiple-contention case. Peter AlfkeArticle: 110006
Peter Alfke wrote: > Well, we could get into a long discussion about relative security, and > about radiation mitigation, but this is not the right place for that. > I must, however, point out that "vendor-neutral" design pays a very > high price in not being able to take advantage of all the "goodies" > that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers, > clock manipulation and clock distribution, Serdes and 75-picosecond I/O > granularity, to name just a few that come to mind. And just wait what > we will announce in V-5LXT...) > Portability forces you to design with 15 year-old basic structures. > That's like living without indoor plumbing, electricity and telephone. > :-( > But your company seems to know why they like you to do it. Frugality > envigorates body and soul... You didn't have indoor plumbing 15 years ago? The plumbing I am using right now is nearly as old as I am and that is a lot more than 15 years!!! ;^) I think the providers of the "special" goodies, that require "special" techniques to use, are much more enthusiastic than the rest of us. I hate having to instantiate chip specific functions in my code. I try to use HDL inference to use block RAMs, FIFOs and the like. If you really need the special features to make your design work and not bloat the chip, then they can be useful, but being able to port code fits into a much higher level model of how to design chips than just trying to use every last gimick in the current generation of FPGAs.Article: 110007
Frank van Eijkelenburg wrote: > How can I do a "clean up project" with Quartus II 6.0? What do you mean with "clean up Project"? Remove unreferenced source files from the project? Remove unwanted settings? Or so? Best regards, BenArticle: 110008
Michael Kraemer wrote: > Actually I cannot understand why Altera is so generous to give away > this software for free, which I appreciate a lot, and then attach such > restrictions. Anyway, this is perhaps the wrong question if one gets > something for free. > Well, it's not entirely Altera's fault. The FlexLM license software they _link_ (i.e. they don't have the source code) in has a function that queries the validity of a certain feature name based on the feature name, the current date, software version etc. The linked-in FlexLM bit then refuses to validate _ANY_ feature if the system clock has been set back, and there you go. On the other hand, many customer calling me with this problem tend to find some bug in their overall system (network, application, whatever), so from a sysadmin standpoint it could actually be positive that this check is there (ducks and runs). In the past I have questioned Altera Tools Marketing's decision to have a license check in the Free Edition at all, but I do understand their reasons for it - they want to know which sites are active and which ones are not. Best regards, BenArticle: 110009
Seriously: We (Xilinx, Altera, et.al.) do not get much speed improvement from the newest and next process generations alone. We improve performance by incorporating clever (and still versatile) hard-coded functionality. We have been on that path ever since the first ripple-carry structures >15 years ago. But it has become more important and more pervasive recently. The user-visible difference between the present and the next generation FPGAs will be much more in architecture and specialized features than in raw logic speed. Smaller geometries help to reduce cost, but don't help much with delays, unless the architecture is changed. And that works against vendor-independence. Just my opinion... Peter Alfke ====================== rickman wrote: > Peter Alfke wrote: > > Well, we could get into a long discussion about relative security, and > > about radiation mitigation, but this is not the right place for that. > > I must, however, point out that "vendor-neutral" design pays a very > > high price in not being able to take advantage of all the "goodies" > > that you find in any moden FPGAs. (BlockRAMs, FIFO and ECC controllers, > > clock manipulation and clock distribution, Serdes and 75-picosecond I/O > > granularity, to name just a few that come to mind. And just wait what > > we will announce in V-5LXT...) > > Portability forces you to design with 15 year-old basic structures. > > That's like living without indoor plumbing, electricity and telephone. > > :-( > > But your company seems to know why they like you to do it. Frugality > > envigorates body and soul... > > You didn't have indoor plumbing 15 years ago? > > The plumbing I am using right now is nearly as old as I am and that is > a lot more than 15 years!!! ;^) > > I think the providers of the "special" goodies, that require "special" > techniques to use, are much more enthusiastic than the rest of us. I > hate having to instantiate chip specific functions in my code. I try > to use HDL inference to use block RAMs, FIFOs and the like. If you > really need the special features to make your design work and not bloat > the chip, then they can be useful, but being able to port code fits > into a much higher level model of how to design chips than just trying > to use every last gimick in the current generation of FPGAs.Article: 110010
rickman wrote: > I hear what you are saying, but this spam was targeted to FPGA users. > Like I said, I had this happen once before with Altera. I started > getting spam emails from a third party that was affiliated with Altera > indirectly. I expect it was a matter of Altera shared the mail list > with party A and party A shared it (properly or improperly) with party > B who starting sending me the spam. > > Worse, I could not get them to take me off the list. They were > emailing web links and the return address was not functional. Trying > to contact the advertising sponser was not effective so I complained to > Altera... twice. They finally responded and I stopped receiving the > emails. We'll see what it takes to stop the spam to the Xilinx > address. I want to say it was a distributor who sent the spam emails. <snip> If it was FPGA trageted, and from a Disti, then that's not what most users would call spam ? - so perhaps you should clarify the company and content ? eg I just got an offer to upgrade my Xilinx Modelsim, from the Mentor Model sim channel, and that's probably part of the conditions of the Xilinx-Mentor tie up, to allow Mentor to fish for upgrades. Maybe someone in Xilinx can clarify this 'more grey' area ? -jgArticle: 110011
Peter Alfke wrote: > What seems to be the problem? > Before and during configuration all Xilinx FPGA outputs are tristated. > During configuration, the 3-state-controlling flip-flop can and should > be asynchronously held reset. Yes....and it is done so automagically by the FPGA...thank you. > It is only after the clock has started and the application runs that > the output can become active, if the user wants that to happen. > Where is the touchy problem? No problem. My point is I'm looking for the actual application that really does require specified reset behaviour PRIOR to the clock starting. > > Just to support Bob: > A 64-mA output sinks 64 mA at 0.4 V. And that is guaranteed worst case. > At nominal conditions it may behave not as an 8 Ohm, but rather as a 3 > to 4 Ohm resistor. Easy to smoke in a multiple-contention case. Easy to smoke only if the condition persists for a 'long' time, where the definition of 'long' is likely getting smaller as time goes by since geometries shrink every few years and devices become less and less tolerant of abuse. So how long is 'long' for your representative Virtex-5 to smoke under the conditions you mentioned above? Also, I think you're bolstering my point not Bob's. Bob's point was that if the tri-state control is the output of a flip flop and you have to wait for the clock in order to set the state of that flip flop then you can have bus contention....I agree....however, using a device that tri-states the outputs before and during configuration and clears the flip flops you shouldn't have that contention because the output of that flip flop won't be some unknown, it can be designed to be shut off coming out of configuration and when the clock arrives, it arrives. With older technology parts that may not have cleared the flops for you the contention would only exist if reset was designed to be released prior to clock and then only for the probably few milliseconds until the clock actually started. But the older technology parts could also take the abuse for that period of time and the design error (IMO) was the releasing of reset prior to clock starting anyway. As an example, take the PCI bus; reset is async to the clock but reset will not be de-asserted until after the clock has been running for some nominal number of cycles. Even the motor control example that was posted on this thread was backed off a bit with the realization that there is outside logic that checks first to see if things are 'OK' before actually turning on the motors. In any case, nobody has articulated yet the application that really does require specified reset behaviour PRIOR to the clock starting thus requiring use of the async reset (with the exception of the reset signal synchronizer flip flop itself). I think I'll quit on this thread (and in the future when it comes up....hey stop the applause out there). If someone can actually demonstrate such an application I'll be happy to hear about it until then I'll just assume that such an application still might exist even if it after several prods from the group they have yet to produce a good example. KJArticle: 110012
Ben Twijnstra wrote: > Michael Kraemer wrote: > > > Actually I cannot understand why Altera is so generous to give away > > this software for free, which I appreciate a lot, and then attach such > > restrictions. Anyway, this is perhaps the wrong question if one gets > > something for free. > > > > Well, it's not entirely Altera's fault. The FlexLM license software they > _link_ (i.e. they don't have the source code) in has a function that > queries the validity of a certain feature name based on the feature name, > the current date, software version etc. The linked-in FlexLM bit then > refuses to validate _ANY_ feature if the system clock has been set back, > and there you go. > > On the other hand, many customer calling me with this problem tend to find > some bug in their overall system (network, application, whatever), so from > a sysadmin standpoint it could actually be positive that this check is > there (ducks and runs). > > In the past I have questioned Altera Tools Marketing's decision to have a > license check in the Free Edition at all, but I do understand their reasons > for it - they want to know which sites are active and which ones are not. > > Best regards, > > > > Ben I believe the reason is that you can convert the "free" edition into the "full" edition by buying a license with no need to do a full reinstall. However, I understand there are some problems with that approach.Article: 110013
Henrik Pedersen wrote: > GaLaKtIkUs™ wrote: > >> comxlib --s mti_se -arch all -l all -lib all -w > > [root@p1800 bin]# find / -name comxlib > [root@p1800 bin]# > > Have'nt got that file. > > Should it be run under vine ? > > Henrik compxlib (typo)Article: 110014
GaLaKtIkUs™ wrote: > Try to type in a shell: comxlib --s mti_se -arch all -l all -lib all -w > -smartmodel_setup > If it doesn't compile tell me the exact error message. > Be sure that the modelsim's binary files are accessible (update you > PATH environment variable) > > On Oct 8, 11:08 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote: >> GaLaKtIkUs™ wrote: >> > Hi, >> > After you got the libraries compiled using the compxlib tool (included >> > in ISE), you shouldn't get any trouble. >> > Please precise the exact problem you encountred >> >> > On Oct 8, 9:47 pm, Henrik Pedersen <henrik.kir...@gmail.com> wrote: >> >> Hey there >> >> >> I have a lot of trouble finding directions/guides/manuals on how to >> >> get subject working. >> >> >> Anyone able to point me in the right direction ? >> >> >> HenrikI'm a step further from that. >> What libs should i compile. >> >> Let me resume for a moment. >> Downloaded WebPack 8,2,03i and installed it. >> Done a few recomended jumps and it works. >> >> When i click "Simulate Behavorial" i get a error saying: >> Model technologies vsim cannot be found be Project navigator. .... >> >> Where do i start ? >> >> Henrik Tried above solution with the folowing result: ./compxlib --s mti_se -arch all -l all -lib all -w -smartmodel_setup ./compxlib: error while loading shared libraries: libPersonalityModule.so: cannot open shared object file: No such file or directory The module in question is located in the same directory. What would be a logical next step to try ? HenrikArticle: 110015
Most human-safety related requirements also include a "no single-point failures" clause, which includes failures of any type of the clock oscillator (no clock, fast/slow clock, etc.). Sure, there may be other ways to handle these failures, but often the cheapest, simplest (and all-importantly, easiest to verify/audit) method is an asynchronous reset. I've also designed VME interfaces in FPGAs when the only available clock (16 MHz off the backplane) was slow enough to miss the minimum gap between address strobes. Asynchronous reset saved the day... Not that I recommend such approaches, but they do have their uses. In general though, fully synchronous systems are usually easier to verify (assuming the clock is known good!), and therefore are preferable to asynchronous or partially asynchronous systems. Andy KJ wrote: > "Andrew FPGA" <andrew.newsgroup@gmail.com> wrote in message > news:1160349835.918930.124340@i42g2000cwa.googlegroups.com... > >> If you take a step back and realize that you probably shouldn't expect > >> anything useful out of a part that is not receiving the proper inputs yet > >> (perhaps by design, after all it could be a power saving measure) then > >> the > >> outputs that do not actually reset themselves until the clock does start > >> up > >> is not really an issue. > > > > Ok but what if those FPGA outputs can cause problems for other parts of > > the system, say if the FPGA is on a bus. Maybe there are some bus > > protocols out there where the bus clock can stop, and the peripheral > > needs to be able to be reset by the bus master?? > Like I said, I don't discount that there may be these cases...but have yet > to hear anyone actually name a specific case where the clock isn't running > but a specific reset condition is required. > > Can anyone actually provide one? Hard to believe that such a case doesn't > exist, but also hard to believe that one hasn't been articulated > either....oh well. > > KJArticle: 110016
radarman wrote: > Peter, > Reprogrammability, and testing, aren't an issue once the design is > stable. I believe that Peter was talking about chip test during manufacturing. You can not test an antifuse before shipping it to the customer. Therefore it is impossible to build large antifuse FPGAs. (Yield has an exponentian dependency size) Kolja SulimmaArticle: 110017
Ben Twijnstra wrote: > Frank van Eijkelenburg wrote: > >> How can I do a "clean up project" with Quartus II 6.0? > > What do you mean with "clean up Project"? Remove unreferenced source files > from the project? Remove unwanted settings? Or so? > > Best regards, > > > Ben > Generated netlists etc. All file which are generated from synthesis till assembler phase. In ISE it is an option in one of the menus, in Quartus I can't find it. FrankArticle: 110018
Henrik Pedersen <henrik.kirneh@gmail.com> wrote: >GaLaKtIkUs™ wrote: >> comxlib --s mti_se -arch all -l all -lib all -w >[root@p1800 bin]# find / -name comxlib >[root@p1800 bin]# >Have'nt got that file. Try: find / -name \*compxlib\*Article: 110019
I'm interfacing an FPGA to a multiplexed SRAM port (ALE, READ, WRITE,
DATA/ADDR bus).
I want to read from/write to the FPGA internal block RAM (SPARTAN 3E),
using burst accesses.
This is a write access example.
____
ALE ___/ \__________________________________________________
_______________ __ __ __ ______
WRITE# \______/ \______/ \______/ \______/
________ ________ ________ ________ ________
DTADD ____/ ADDR \/ DATA0 \/ DATA1 \/ DATA2 \/ DATA3 \______
\________/\________/\________/\________/\________/
For the address load and increment I combined ALE, READ and WRITE
signals to generate one clock signal.
CLOCK <= WRITE# and READ# and (not ALE);
The problem is, to determine if I must load a new address I must know
if it is the ALE cycle:
if rising_edge (CLOCK) then
if (ALE = '1') then -- problem
ADDRESS_REG <= DTADD;
else
ADDRESS_REG <= ADDRESS_REG+1;
end if;
end if;
But the clock is a delayed version ALE, READ# and WRITE#, so the
setup/hold times will no be met!
What's the best way of doing this?
Of course I can use an auxiliar signal:
if rising_edge (ALE) then
LOAD_ADDR <= '1';
end if;
if ((WRITE# = '0') or (READ# = '0')) then -- asyncronous clear
LOAD_ADDR <= '0';
end if;
And substitute:
if (ALE = '1') then
for:
if (LOAD_ADDR = '1') then
But now I have two clock sources/nets (CLOCK and ALE)!
Any suggestions?
Luiz Carlos
Article: 110020rponsard@gmail.com wrote: > I purchased Spartan3E starter kit (for edu.) It is shipped with ISE8.1 > and EDK8.1 > > Is 8.2 (with last patches) better than 8.1 (with last patches) ? > > Is there a way to use EDK8.1 (only a CD in box) with ISE 8.2 (webpack > freely available) ? > > Is it possible to download an other evaluation version of EDK (8.2 in > place of 8.1) ? > > thank xilinx folks... > The version of the EDK must match the version number of ISE. So EDK 8.2 can not used in combination with ISE 8.1. FrankArticle: 110021
oen_br schrieb: > I'm interfacing an FPGA to a multiplexed SRAM port (ALE, READ, WRITE, > DATA/ADDR bus). > I want to read from/write to the FPGA internal block RAM (SPARTAN 3E), > using burst accesses. > > This is a write access example. > ____ > ALE ___/ \__________________________________________________ > _______________ __ __ __ ______ > WRITE# \______/ \______/ \______/ \______/ > ________ ________ ________ ________ ________ > DTADD ____/ ADDR \/ DATA0 \/ DATA1 \/ DATA2 \/ DATA3 \______ > \________/\________/\________/\________/\________/ > > For the address load and increment I combined ALE, READ and WRITE > signals to generate one clock signal. > CLOCK <= WRITE# and READ# and (not ALE); Clock signal for what? The BRAM inside the FPGA? NO WAY! > The problem is, to determine if I must load a new address I must know > if it is the ALE cycle: > > if rising_edge (CLOCK) then > if (ALE = '1') then -- problem > ADDRESS_REG <= DTADD; > else > ADDRESS_REG <= ADDRESS_REG+1; > end if; > end if; > > But the clock is a delayed version ALE, READ# and WRITE#, so the > setup/hold times will no be met! > > What's the best way of doing this? Use a clean clock (from a XO or so) to clock the FPGA logic. Not clock gating etc.! Build text book style FSMs to contol the BRAM and generate appropiate signals for your external SRAM. Than it will work fine. Hint. Register at least WRITE# to the SRAM, so it will not glitch. > But now I have two clock sources/nets (CLOCK and ALE)! No, you have just one system clock, that generates all other signals. A clean 1 clock design. Just too easy ;-) Regards FalkArticle: 110022
On 9 Oct 2006 11:57:12 -0700, "KJ" <Kevin.Jennings@Unisys.com> wrote: >In any case, nobody has articulated yet the application that really >does require specified reset behaviour PRIOR to the clock starting thus >requiring use of the async reset (with the exception of the reset >signal synchronizer flip flop itself). Uh, I did. Took me 20 minutes to type it up, too. I'm not exactly sure what the disagreement is: if you have FFs controlling TriState enables, you should initialize them asynchronously. Whether that's done by an end-of-config reset or some other reset signal doesn't really matter--you need the asynchronous reset. And I didn't even get to the open-the-bomb-bay-doors and throw-the-countermeasures-out-the-back-of-the-plane and start-radiating-the-patient signals. Proper design etiquette demands that they be initialized immediately, too. (Yes, those signals go through other interlocks, but as soon as you rely on redundancy, it ceases to exist.) Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 110023
quartus_stp.exe is an executable file, not a TCL package. This executable provides a TCL shell environment that loads a number of TCL packages. When you click on the insystem_memory_edit package in the TCL API Help window which is started up by quartus_sh --qhelp, you will read this information: "This package is loaded by default in the following executable: quartus_stp". That means that you can run TCL commands in this package using quartus_stp.exe. "update_content_to_memory_from_file" command in the insystem_memory_edit package is likely what you want. Saving the example usage in that command's help topic into a file, example.tcl. For example, # Initiate a editing sequence begin_memory_edit -hardware_name "USB-Blaster \[USB-0\]" -device_name "@1: EP1S25/_HARDCOPY_FPGA_PROTOTYPE (0x020030DD)" # Write memory content using the hex memory file update_content_to_memory_from_file -instance_index 0 -mem_file_path "image_8x1024.hex" -mem_file_type hex # End the editing sequence end_memory_edit Customized the file based on your environment. Then, you can run that TCL script in command line as "quartus_stp.exe -t example.tcl" Hope this helps, Subroto Datta Altera Corp. On Oct 6, 8:03=C2=A0am, "david" <1024.da...@gmail.com> wrote: > this is a good idea, thanks > i am trying to load the quartus_stp package, the file exist in the > qurtus/bin libarry > =C2=A0but i can't load it, i am not using external logic analyzer > how can i load the file? all the commands that belong to the in memorry > edit is not available > so' how can i load it? > > thank you very much > david > > SubrotoDatta =D7=9B=D7=AA=D7=91: > > > > > Hello David, > > > You can use the TCL interface to automate the memory update. =C2=A0Use > > quartus_sh --qhelp to get the help on the "insystem_memory_edit" TCL > > package. =C2=A0This package is only available in the shell provided by > > quartus_stp.exe. > > > If you are using an external logic analyzer, you can install the free > > small standalone programmer > > (https://www.altera.com/support/software/download/programming/quartus2.= .=2E) > > with SignalTap II on the logic analyzer. =C2=A0This package includes the > > quartus_stp.exe executable. =C2=A0If you are using SignalTap II Logic > > Analyzer, the acquisition can be started in quartus_stp.exe as well > > using the TCL command from the "stp" package. > > > Hope this helps, > >SubrotoDatta > > Altera Corp. > > > On Oct 5, 1:54=C2=A0am, "david" <1024.da...@gmail.com> wrote: > > > hello > > > thank you for your replay > > > > we allready tried this option before, but we have a problam, because = we > > > need to modify the data in the memory while the system is runing ( the > > > in system memory size is to small for ower application), every 512 > > > clock cycles. > > > can we update the memory automaticly with new data from predefine fil= es > > > (hex files) while the system is runing? (it's not practiclly to rewri= te > > > manually every 512 clocks cycles, we need the system to run at least > > > for 32768 clock cycles continusly, we can spend clock cycles as need = to > > > rewrite the content of the memory) > > > > thanks > > > david > > > >SubrotoDatta =D7=9B=D7=AA=D7=91: > > > > > It is definitely possible to update the memory and constants in a p= rogrammed > > > > device from Quartus using the In System Memory Content Editor. Deta= ils can > > > > be found at: > > > > >http://www.altera.com/literature/hb/qts/qts_qii53012.pdf > > > > > You can use this in conjunction wiith SignalTap II Embedded logic a= nalyzer > > > > to debug your work. > > > > > Hope this helps, > > > >SubrotoDatta > > > > Altera Corp. > > > > > "david" <1024.da...@gmail.com> wrote in message > > > >news:1159976602.300018.42380@e3g2000cwe.googlegroups.com... > > > > > hello > > > > > i am a student, working on development kit nios 2 cyclone edition. > > > > > i want to use the logic analyzer to import data to the fpga from = the > > > > > logic analyzer, can i do it?- Hide quoted text -- Show quoted tex= t -- Hide quoted text -- Show quoted text -Article: 110024
Deleting the "db" subdirectory is a good point to start... Thomas www.entner-electronics.com "Frank van Eijkelenburg" <someone@home.com.invalid> schrieb im Newsbeitrag news:452AA48C.2020108@home.com.invalid... > Ben Twijnstra wrote: >> Frank van Eijkelenburg wrote: >> >>> How can I do a "clean up project" with Quartus II 6.0? >> >> What do you mean with "clean up Project"? Remove unreferenced source >> files >> from the project? Remove unwanted settings? Or so? >> >> Best regards, >> >> >> Ben >> > > Generated netlists etc. All file which are generated from synthesis till > assembler phase. In ISE it is an option in one of the menus, in Quartus I > can't find it. > > Frank
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