Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 110625

Article: 110625
Subject: DDR access for multiple procs on a ML310 (Virtex-II Pro)
From: "Stevo_V2pro" <HEEEY.STEVE@gmail.com>
Date: 18 Oct 2006 17:06:16 -0700
Links: << >>  << T >>  << A >>
Does anyone know if it is possible to have mutltiple processors be able
to access the DDR memory in an ML310 board(Virtex-II Pro)?  Currently I
am experimenting with 2 PowerPC cores, but I am also looking into using
a single PPC core and a single microblaze core.  I'm intending to run a
seperate operating system on each of the cores and would like each to
have access to a fast and decent sized amount of RAM.  I've seen guides
using shared BRAMS for having two procs accessing the same memory for
data sharing, but BRAMs are relatively small.  I'm not looking to share
data between the procs.  Essentially, I want both processors to be able
to use RAM, but have separate memory spaces within that RAM.  If this
is not possible, is it possible for the two procs to have access to the
same memory space, but to avoid collisions by assigning each operating
system a spearate portion of that memory space to use?   I would assume
that both processors need to be on the same bus as the memory
controller, and some sort of bus arbitration mechanism would be needed.
 Any help that anyone can provide would be greatly appreciated.

Thanks, 
Steve


Article: 110626
Subject: Re: OpenCores.org's I2C: Clock Stretching Support
From: "rickman" <gnuarm@gmail.com>
Date: 18 Oct 2006 17:25:02 -0700
Links: << >>  << T >>  << A >>
markus wrote:
> Hi,
>
> I'm currently working with the I2C core supplied by OpenCores.org. I
> have successfully got the design to work in an FPGA.
>
> However, all of the slave device I used may not have the clock
> stretching feature implemented. As a result, I am not sure if this I2C
> core uses the included clock stretching feature correctly. I tried
> looking at the code, but could not find any code that implies clock
> stretching logic. The documentation for this core also lacks
> information regarding the clock stretching. Has anyone used this core
> with a slave that  performed clock stretching?
>
> If you're familiar with this core, my control logic for this core
> simply sends the instructions that's required for read/write and waits
> for interrupts, ack/nack, and TIP logic to assert/deassert. Do I need
> to add logic to detect clock stretching?

I am not familiar with the I2C core you are using, but in order to
stretch the clock, it will have to pull the clock line low.  You should
be able to start at the IO signal for the clock, find the output side
and trace it back to the controlling logic.  If you don't see a signal
that drives the clock signal as an output, then they have not
implemented clock stretching.


Article: 110627
Subject: Re: Cheapest FPGA board to study VHDL on
From: Mark McDougall <markm@vl.com.au>
Date: Thu, 19 Oct 2006 10:30:52 +1000
Links: << >>  << T >>  << A >>
samiam wrote:

> Ideally Id like an FPGA based board with a few inputs (dip
> switches,toggles?), some outputs (parallel or serial connector, some
> leds) < $100

Altium LiveDesign (USD$99)

<http://www.altium.com/Products/AltiumDesigner/LiveDesign/>

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 110628
Subject: Re: FIR filter fpga help
From: "Matthew Hicks" <mdhicks2@uiuc.edu>
Date: Wed, 18 Oct 2006 19:58:17 -0500
Links: << >>  << T >>  << A >>
You probably have ruled out IIR filters already, but I thought I'd mention 
them just in case.


---Matthew Hicks


"cutemonster" <ckh827@hotmail.com> wrote in message 
news:9qKdnRAOY6vpx6vYRVn_vA@giganews.com...
>
> Hi all, I'm new to the Xilinx FPGA FIR filter and would like to ask for
> help.
> I have two (X and Y) channels and their frequency is about 10Mhz.
> Using 2 14-bits ADC with sampling 50Mhz.
> I have my Xilinx clock about 50Mhz.
>
> How many taps for each channel is necessary for doing a cutoff frequency
> of 10MHz?
>
> How many bits should the coefficients length is?  how to do a optimal
> design?
>
> I have to use FIR because my moving avaraging doesn't solve the problem.
>
> What other terms I need to consider?
>
> is my Spartan 3 xcs3s400 enough? 16 multipliers.
> is that 1 tap require 1 multiplier.  If so, I would get a virtex II pro.
> board.
>
> At last, I want to say thank you for looking at my thread and I hope you
> can answer my questions.
>
> thanks again,
> Kenny,
> 



Article: 110629
Subject: Re: echo $LM_LICENCE_FILE not working
From: "Kevin" <kevin.hoyt@latticesemi.com>
Date: 18 Oct 2006 18:04:06 -0700
Links: << >>  << T >>  << A >>
If you have multiple paths to license files defined in your
LM_LICENSE_FILE variable you could have problems.  You mentioned that
you had 2 versions of ispLEVER on your system, one with a valid license
and one with an expired license.  Depending on the ordering of the
paths pointing to the 2 license.dat files in the environment variable,
flexLM may be finding the feature line in the expired license and
generating an error without even looking at the valid license.  FlexLM
can be configured to search the license files until it finds a license
file that includes the feature line it is looking for, and either
starting the software when a valid license is found or generating a
license error when an expired license is found, either way stopping the
search as soon as it finds the feature line.  FlexLM can also be
configured to continue searching for a valid license feature even after
it has found an invalid feature.  The original software vendors, Mentor
Graphics in the case of ModelSim, configuration of the license
generation software, determine all this.  I have always found that
regardless of the software tools and licenses adding all licenses into
one file and having a single path defined in the LM_LICENSE_FILE
variable is the best way to avoid these issues.


Article: 110630
Subject: Re: Cheapest FPGA board to study VHDL on
From: Donald <donald@dontdoithere.com>
Date: Wed, 18 Oct 2006 20:30:02 -0600
Links: << >>  << T >>  << A >>
Mark McDougall wrote:
> samiam wrote:
> 
> 
>>Ideally Id like an FPGA based board with a few inputs (dip
>>switches,toggles?), some outputs (parallel or serial connector, some
>>leds) < $100
> 
> 
> Altium LiveDesign (USD$99)
> 
> <http://www.altium.com/Products/AltiumDesigner/LiveDesign/>
> 
> Regards,
> 

http://www.knjn.com/ShopBoards_Parallel.html

Article: 110631
Subject: Re: Scoreboard and Checker in Testbench?
From: "Alex" <agnusin@gmail.com>
Date: 18 Oct 2006 19:35:25 -0700
Links: << >>  << T >>  << A >>
Hi, Nigel.
Thanks for clarifications.
Please see my comments below.

NigelE wrote:

> Alex, I think you need to be careful not to confuse the generic use of
> terms like entities (things) in the AVM cookbook with VHDL key words.

This may be not a problem : I am pure Verilog coder ;)

> I agree it is difficult to tie down a definition of a transaction, as
> transactions can be different things to different people
> eg a h/w designer may want to identify individual transfers of data on
> a bus as a transaction, while someone viewing the design at a higher
> level is more interested in frames or packets, while at a system level
> it may be a message between s/w on different processors.
> All are valid transactions.

That's sound like a problem. Transaction definition is too broad to be
useful. To clarify things, different companies developed their own
understanding of transaction. (see link to the article below).

> In terms of the AVM, the basic TLM communication mechanism is based on
> the semantics of the OSCI TLM, implemented in SystemC and/or
> SystemVerilog.

OSCI definition of transaction also seems too broad to be useful:

"OSCI seems to have the most liberal interpretation. OSCI includes
several levels of abstraction under TLM, including Programmer's View
(PV), which contains no timing; Programmer's View with Timing (PVT),
which adds timed protocols and can analyze latency or throughput; and
Cycle Accurate, which is accurate to the clock edge but does not model
internal registers.

>From an OSCI point of view, pretty much everything above RTL can be
considered TLM, said Pat Sheridan, OSCI executive director and the
director of marketing at CoWare Inc. But the way most users think of
TLM appears to include just the untimed (PV) and cycle-approximate
(PVT) styles of modeling."

http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=181503693&printable=true


> This defines the use of put(), get() and peek() function/task calls to
> transfer a transaction from one component to another.

Which means that it is possible to use these convenient functions for
transaction communication. But, it is also possible to connect bus
master with the bus slave - they will also communicate with
transactions through the signal-level interface. And this is
transaction-level modeling too.

> Both these languages support a component calling the tasks/functions of
> another component (using classes and/or interfaces). Thus my monitor
> can call the write() function of my scoreboard without needing to what
> it does. This allows me to change the scoreboard without effecting the
> monitor, provided the new scoreboard also implements a function called
> write().

There may be different methods for transaction communication for reuse.
For example, there are strong arguments against AVM method, where
monitor code has to be modified in order to communicate with specific
checking component. Since monitor is protocol-specific
(design-independent), it is usualy more reusable then design-specific
checker/scoreboard. Then, it may be a better idea for monitor to simply
"present" transaction without calling some external functions. Then, it
will be the task of checking component to grab needed data from needed
monitors when they are signalling about "transaction completion". This
make monitors to be independent from the "external world" and thus
highly reusable between the projects.

In any case, functions/tasks presented by OSCI do not clarify the
meaning of transaction, but rather provide some implementational
details.

> This is the basis for verification component reuse in the AVM (and
> other transaction based verification methodologies.)
>
> So in the AVM, a transaction is most commonly just a function/task call
> between verification components, thus the third definition.

I agree. In this case, AVM may contain only third transaction
definition. This will greatly clarify the meaning of transaction in the
context of AVM.

Regards,
-Alex


Article: 110632
Subject: Learner
From: "Raghu" <thota.raghavendrarao@gmail.com>
Date: 18 Oct 2006 22:20:10 -0700
Links: << >>  << T >>  << A >>

Hi all,

       I am learner in FPGA design. You could send any tutorials or
some information regarding this.

Thamks all.


Article: 110633
Subject: Meeting Timing Constraint
From: "Roger" <hpsham@gmail.com>
Date: 18 Oct 2006 22:41:20 -0700
Links: << >>  << T >>  << A >>
A design is built to work at 50MHz, but the deisgn when tested works
only at 48MHz. What
should we do to make the design meet specific timing constraint .i.e.
to make the design to make it work at 50 MHz? 
Thanks


Article: 110634
Subject: Re: Cheapest FPGA board to study VHDL on
From: "David M. Palmer" <dmpalmer@email.com>
Date: Wed, 18 Oct 2006 23:43:43 -0600
Links: << >>  << T >>  << A >>
In article <vHsZg.77479$p86.25317@fe05.news.easynews.com>, samiam
<samiamSPAMTHIS@spamalert.com> wrote:

> Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga)
> 
> Whats the cheapest board to study VHDL on?
> 
> Ideally Id like an FPGA based board with a few inputs (dip 
> switches,toggles?), some outputs (parallel or serial connector, some
> leds) < $100

Digilent has a $59 board with a 100k-gate FPGA, switches, port
connectors, LEDs etc.
http://digilentinc.com/Products/Detail.cfm?Prod=BASYS
And check out their other boards to see how much more you can get with
further increments of money.

As it says, the board costs less than the textbook.

http://www.fpga4fun.com/ and the affiliated store http://www.knjn.com
also has a variety of lost-cost FPGA boards.

I think that seeing something work in reality is an important part of
learning, even though simulators give you more insight into what's
happening.  Otherwise you get to your first real design after a few
years of learning VHDL and then you ask 'what does non-synthesizable
mean?'

After all, if you never intend to implement your design on an FPGA,
what's the point in learning VHDL?

-- 
David M. Palmer  dmpalmer@email.com (formerly @clark.net, @ematic.com)

Article: 110635
Subject: Re: Cheapest FPGA board to study VHDL on
From: "Don" <no_email_plz@no_email_plz.com.xxx>
Date: 19 Oct 2006 06:12:33 GMT
Links: << >>  << T >>  << A >>
On Wed, 18 Oct 2006 16:33:31 +0000, samiam wrote:

> Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga)
> 
> Whats the cheapest board to study VHDL on?
> 
> Ideally Id like an FPGA based board with a few inputs (dip 
> switches,toggles?), some outputs (parallel or serial connector, some
> leds) < $100
> 
> I am looking on ebay now, and I see one or two boards well above $100.
> Any suggestions?
> 
> Thanks in advance

I pretty sure that xilinx has some spartan 3 starter boards for $100 too.
Look on their estore.

Article: 110636
Subject: Re: Learner
From: "John Adair" <g1@enterpoint.co.uk>
Date: 18 Oct 2006 23:34:09 -0700
Links: << >>  << T >>  << A >>
Some useful links to resources here
http://www.enterpoint.co.uk/techitips/techitips_useful_things.html.

John Adair
Enterpoint Ltd.

Raghu wrote:
> Hi all,
>
>        I am learner in FPGA design. You could send any tutorials or
> some information regarding this.
> 
> Thamks all.


Article: 110637
Subject: Re: buying xilinx spartan 3E kit just for EDK ?
From: "David M. Palmer" <dmpalmer@email.com>
Date: Thu, 19 Oct 2006 00:39:43 -0600
Links: << >>  << T >>  << A >>
In article <1161105997.328051.17820@i42g2000cwa.googlegroups.com>,
ScottNortman <scott.nortman@gmail.com> wrote:

> I recently purchased the sp3e starter to teach myself VHDL, and later
> realized that the EDK came with the pacakge.  I then started to use the
> EDK and I am very happy with the tool.   I've implemented the Micoblaze
> processor and I've started using it with uClinux and FreeRTOS.

The EDK included is only an evaluation version.

When I got my SP3E starter kit, it came with disks helpfully labelled
something like Embedded Development Kit (EDK) and ISE.    The ISE disk
contains the webpack and evaluation versions of Foundation and
Chipscope.

Webpack, according to the disk package materials, is the free and most
complete easy-to-use software solution to complete a Xilinx CPLD or
FPGA design.  Foundation is the world's easiest to use and top-rated
PLD design environment.  The EDK description was less specific.

I wanted to start by teaching myself VHDL.  Based solely on the
information above, could you figure out which things to install and
activate immediately and which to wait until later for?

Anyway, the EDK is a system for embedding soft processors, ethernet
drivers, memory interfaces, and other system components into an FPGA. 
The 'evaluation version' means that it is usable for only a limited
length of time after activation.  'Limited length of time' is 'Less
than it takes to get really comfortable with VHDL when teaching it to
yourself evenings and weekends on a hobby basis'.

I still don't know what Foundation is.

Just so you know.  You ought to not activate the EDK until you have
learned VHDL and are ready to start building systems for only the next
90 days.  I have pragmatic reasons for wanting to go open source in my
designs (e.g. opencores.org) so the wasted activation was no great loss
for me.

-- 
David M. Palmer  dmpalmer@email.com (formerly @clark.net, @ematic.com)

Article: 110638
Subject: Re: Meeting Timing Constraint
From: "John Adair" <g1@enterpoint.co.uk>
Date: 18 Oct 2006 23:39:56 -0700
Links: << >>  << T >>  << A >>
Not an un-common problem. Try just set the constraint slightly tighter.
Often P&R tools just try to achieve what is requested and if you set it
a bit tighter, say for 55 MHz, you will probably get a design that
actually works at 50 MHz.

The root of this issue is that the speed files, used by the tools,
don't match the silicon exactly. If you are not on the latest version,
or service pack, of software it is usually worth getting the latest.

John Adair
Enterpoint Ltd.

Roger wrote:
> A design is built to work at 50MHz, but the deisgn when tested works
> only at 48MHz. What
> should we do to make the design meet specific timing constraint .i.e.
> to make the design to make it work at 50 MHz? 
> Thanks


Article: 110639
Subject: Re: Meeting Timing Constraint
From: "Amontec, Larry" <laurent.gauch@ANTI-SPAMamontec.com>
Date: Thu, 19 Oct 2006 09:05:15 +0200
Links: << >>  << T >>  << A >>
Roger wrote:
> A design is built to work at 50MHz, but the deisgn when tested works
> only at 48MHz. What
> should we do to make the design meet specific timing constraint .i.e.
> to make the design to make it work at 50 MHz? 
> Thanks
> 
Maybe update your P&R (place and route) software ?

Laurent
http://ww.amontec.com

Article: 110640
Subject: Re: Cheapest FPGA board to study VHDL on
From: Paul Burke <paul@scazon.com>
Date: Thu, 19 Oct 2006 08:05:39 +0100
Links: << >>  << T >>  << A >>
Mike Treseler wrote:

> To learn vhdl, all you need is a simulator
> to verify your uut and testbench code
> and quartus or ise to view the rtl schematic.
> 

That's true, but it's not much fun.

> A board is of little value until
> the code is complete and tested.
> 

You don't need a lot to get the code complete and compiled. You can 
learn a lot about testing by comparing what you meant it to do with what 
actually happens in the real world. And acquiring the skills of using 
the scope to debug hardware is a useful exercise in itself, if the OP 
doesn't know it already. And it's fun.

These people do some low- cost FPGA boards. You can probably get the 
VHDL stuff free from the FPGA vendor.

Paul Burke

From henrik.kirneh@gmail.com Thu Oct 19 00:08:27 2006
Path: newssvr13.news.prodigy.com!newsdbm04.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!pd7cy3no!shaw.ca!nx02.iad01.newshosting.com!newshosting.com!newsfeed.kamp.net!newsfeed.kamp.net!newsfeed.freenet.de!feeder.news-service.com!216.196.110.148.MISMATCH!border1.nntp.ams.giganews.com!nntp.giganews.com!uio.no!news.banetele.no!dotsrc.org!filter.dotsrc.org!news.dotsrc.org!not-for-mail
Message-Id: <4537246b$0$49202$14726298@news.sunsite.dk>
From: Henrik Pedersen <henrik.kirneh@gmail.com>
Subject: Re: WebPack on Linux
Newsgroups: comp.arch.fpga
Reply-To: henrik.kirneh@gmail.com
Date: Thu, 19 Oct 2006 09:08:27 +0200
References: <4533cbef$0$49200$14726298@news.sunsite.dk> <pan.2006.10.16.22.59.58.430093@polybusPleaseDontSPAMme.com> <45353150$0$49200$14726298@news.sunsite.dk> <pan.2006.10.17.19.51.33.988757@polybusPleaseDontSPAMme.com> <45365e1c$0$49209$14726298@news.sunsite.dk> <pan.2006.10.18.17.09.42.134573@polybusPleaseDontSPAMme.com>
User-Agent: KNode/0.10.4
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7Bit
Lines: 12
Organization: SunSITE.dk - Supporting Open source
NNTP-Posting-Host: 217.116.244.170
X-Trace: news.sunsite.dk DXC=W`[FmW3\dd`5kL0JZ2<WfiYSB=nbEKnkkl68mc>]X9OmYDoQ\kQ?kDd^PgABlB42EoIHQFW\gATbk1VYSn^jGTgdGX_hS]faD:ccQch5PSlkYl
X-Complaints-To: staff@sunsite.dk
Xref: prodigy.net comp.arch.fpga:121593

Josh Rosen wrote:

> set path = (${path} $XILINX/bin/lin)
> setenv LD_LIBRARY_PATH ${LD_LIBRARY_PATH}:${XILINX}/bin/lin:${XILINX}/lib
> setenv LMC_HOME ${XILINX}/smartmodel/lin/installed_lin
> setenv NPX_PLUGIN_PATH ${XILINX}/java/lin/jre/plugin/i386/ns4

Heureka !!!!
Thank you so very, very much.
Now i can get a bit further with my projects.

Henrik

Article: 110641
Subject: Re: Cheapest FPGA board to study VHDL on
From: Al <alessandro.basili@cern.ch>
Date: Thu, 19 Oct 2006 09:23:02 +0200
Links: << >>  << T >>  << A >>


David M. Palmer wrote:
> 
> I think that seeing something work in reality is an important part of
> learning, even though simulators give you more insight into what's
> happening.  Otherwise you get to your first real design after a few
> years of learning VHDL and then you ask 'what does non-synthesizable
> mean?'
> 
> After all, if you never intend to implement your design on an FPGA,
> what's the point in learning VHDL?
> 

I think that Andy got exactly the point:
> Unless you are trying to interface to something else, and need to prove
> that what you designed can talk to it, a simulator will "show" you much
> more than you will ever see from an FPGA board.

As far as I understood we are talking about "learning VHDL" (as samian 
asked), not implementing a project which will have an interface with 
some other stuff.
The only limitation in simulation is to think about all the cases your 
hardware will run through and this is where hardware is most probably 
needed, just because you missed to simulate a rare (but possible) case.
But on a stand alone project I think that an evaluation board is even 
less needed (even because most of the time you will not implement on 
evaluation board, but on custom made boards or some others "standard 
programmable" boards).
This will save you money and will let you concentrate on the most 
important point (to me) at the very beginning: functional vhdl verification.

Mike Treseler:
> To learn vhdl, all you need is a simulator
> to verify your uut and testbench code
> and quartus or ise to view the rtl schematic.
> 

and I totally agree.


-- 
Alessandro Basili
CERN, PH/UGC
Hardware Designer

Article: 110642
Subject: Re: Cheapest FPGA board to study VHDL on
From: fpga_toys@yahoo.com
Date: 19 Oct 2006 00:30:36 -0700
Links: << >>  << T >>  << A >>

samiam wrote:
> Whats the cheapest board to study VHDL on?
>
> Ideally Id like an FPGA based board with a few inputs (dip
> switches,toggles?), some outputs (parallel or serial connector, some
> leds) < $100

Any of the Digilent boards are great resources, and there are lots of
Univ classes designed around them.

They are all very affordable.

If you are a Univ student, I'd suggest getting the XUP-V2PRO board ...
best value on the planet, and amazing resale value :)

If you want to build projects which are FPGA based, I'd suggest
something like one of the Spartan boards ... combined with a proto
board. Get one with more gates than you need, don't skimp ... as most
of the MicroCore projects are fun later.


Article: 110643
Subject: Re: ANNC: Open Source, Free 32-bit soft processor webcast
From: pbdelete@spamnuke.ludd.luthdelete.se.invalid
Date: 19 Oct 2006 07:49:39 GMT
Links: << >>  << T >>  << A >>
In comp.arch.fpga bart <bart.borosky@latticesemi.com> wrote:
>pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote:

>> Specificly what kind of license is used..?, and what are the terms?

>For the LatticeMico32 there is an Open IP Core Licensing Agreement.
>This license lets you freely mix proprietary with open code and freely
>distribute hardware (FPGAs) without license documentation. This Open IP
>Core Licensing Agreement applies to the generated microprocessor HDL
>code and selected peripheral components HDL code.

>Click here to see the license:
>http://www.latticesemi.com/dynamic/view_document.cfm?document_id=21674

Could you release the document without login..?


Article: 110644
Subject: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
From: Zara <me_zara@dea.spamcon.org>
Date: Thu, 19 Oct 2006 09:50:03 +0200
Links: << >>  << T >>  << A >>
This is not strictly a call for help, it is more of a warning to
everyone.

Yesterday, I tried to upgrade from ISE/EDK 8.1 to ISE/EDK 8.2, and
also change from Xilinx Paralllel IV (it always worked as PC III) to
USB Platform cable

Steps:

1) Uninstall all older versions. Easy, it works nice.

2) Install ISE 8.2 and all upgrades/sp's. Slow (lots of mb), but it
works.

3) Import old CPLD project, rebuild it and dowload it via USB cable.
pretty fine, no retires, no problems. Using USB21

4) Install Modelsim XE 6.1e with new USB dongle. After 4 retrials I
finally noticed that when plugging the dongle on my XPPro machine,
some drivers were being loaded that disabled the possibility to load
the drivers coming with Modelsim, so that the dongle was not
recognised and I could not register it. Apparently, the solution is:
        4.a) Install Modelsim first time
        4.b) Plugin USB dongle, and let OS do all the driver selection
        4.c) Open device manager: right-click on  MyPC, select Manage,
on emerging window select something that should read device
manager/hardware manager or anything of the sort, I have an spanish
version of XPPro, and this is only a translation.
        4.d) Uninstall Aladdin USB Key under USB controllers
        4.e) Go to root folder of your modelsim installation, enter
drivers folder, double click on flexid.exe.
       4.f) On device manager, search for new hardware. It will
install the new drivers for dongle
       4.g) Reinstall Modelsim, and tell it that you have a Dongle but
you *don't* want to install new drivers (That should be a "no" button
on the fiirst dialog after installing, with a lot of lilterature over
it)
       4.h) Typically, you will have  now a good license request wtith
yoyr FLEX-ID=9-xxxxxx option right. If it is not so, reply to this
POST with your solution, it might help other users!

5) Install EDK and SP. After that, open an 8.1 project. It tells me
that it is upgrading some peripherals, but *not* microblaze and
bram_if_ctrlr. Well, I suppose everything should be fine...

6) Clean all files, and rebuild system. No complains from
synthsis/transalet/map/par/libgen/gcc.

7) Download contenst to FPGA through USB cable. No problems, using
USB21, it gets downloaded but... it is not working. I know it, because
the programa for the microblaze will switch on and off some leds, and
there is not such event happening.

8) Well let's debug it. Launch XMD, it seems to connect using USB22,
but it takes a long time to show the prompt (Warning!)

9) Launch MB_GBD. It will not connect to XMD


10) OK, maybe it is a problem with USB cable (have you noted that
discrepancy between USB21 and USB 22?), so I plug my good old slow PC4
cable (remember: it is unable to work better than a PC3 cable!). It
does not work either.

11) Oh, so the project is FUBAR: unsistall 8.2, restore backups,
reinstall 8.1. Fine.

12) I will reinstall 8.2 *without* uninstalling 8.1, and work over
copies of 8.1 projects to see where is the catch.

Followups expected (from me, certainly, from anyone else they are
welcome...).

Regards

Zara

Article: 110645
Subject: How to avoid negative slack.
From: "himassk" <himassk@gmail.com>
Date: 19 Oct 2006 00:52:55 -0700
Links: << >>  << T >>  << A >>
Hi,
The static timing analysis report for my design is as follows:

From: DAT_FSM/FULL_TEMP:CLK
To: DAT_FSM/count[10]:D
data required time		14.609
data arrival time		15.146
slack			-0.537

Could any one please suggest me the techniques to avaoid negative
slack.
Please let me know the relavent material available.

Thanks in advance.

Regards,
HimaSSK.


Article: 110646
Subject: Re: 64 bit division compensate NCO
From: "Ulrich Bangert" <df6jb@ulrich-bangert.de>
Date: Thu, 19 Oct 2006 10:14:09 +0200
Links: << >>  << T >>  << A >>
Luca,

perhaps you can elaborate a bit more on what it is all good for? I am asking
this because the parts that you are playing  with seem not to fit each other
very well: Using a 64 bit NCO seems to indicate an EXTREME need for
precision while the idea to simply divide the counter results in order to
get a new delta phase value for the NCO sounds more like a LOW fidelity
frequency locked loop.

Nevertheless, the most basic question that you should care about is the
resolution of the counters. This being so because the resolution of the
counters limits the precision with that you may know the input values of
your control loop.

Let us first consider the case that Count1 and Count2 are integer values
(i.e. they are really simply the counted values for a given timebase). In
this case the typical +/-1 digit error of a measurement like that is the
limiting factor in resolution. Under the very optimistic assumption that
your clocks are in the range of 1 GHz (and that your fpga can handle clocks
like that) then at a timebase of 1.6 ms you end up with count rates in the
order of 1.6E6. At count rates like that the +/- 1 digit error produces an
6.25E-7 relative statistic error. This relative error will increase with
decreasing clock frequencies.

With the 64 bit NCO the resolution of the lest significant bit is in the
order of 5.4E-20 !!!!! Clearly you will not be able to compute a result with
that precision with input values having a relative error of 6.25E-7 or even
more. In this case you are well served with a 32 bit division which will
provide more than enough bits. If you want to stay with the 64 bit NCO then
you change only the upper 32 bit and let the rest stay at zero.

Things may look a bit different if your counters are not simply "counters"
but sophisticated frequency measurement devices. With sub clock
interpolation schemes you may get down to a relative error of 2E-11. Where
this number comes from is a bit OT. The dynamic range that is necessary to
handle this is more than is available with 32 bits and you would indeed need
a >32 bit computation.

In general, a good control loop will need some more computations than simply
the frequency ratio, for example integrations and low pass filtering. Stuff
that is not so easily done in VHDL etc. So, the question whether you should
try the "all hardware" approach or make use of an fpga embedded processor
depends a bit on what development environment you have available. There are
systems out that may translate complete DSP based models into VHDL for you
that you put into the fpga. A system like that will address all VHDL
generation problems on its own and take a lot of complexity out of your
project. If you have no such system at hand the embedded processor variant
may be the more easy one. Most of the modern compilers for 32 bit embedded
processors handle 64 bit integers as well as 64 bit floating points with
ease. The fact that the fpga emdedded processor may take use of fpga
hardware multipliers makes floating point operations a matter of
microseconds and not of milliseconds even without a dedicated floating point
unit. So speed should not be a problem.

In any case you should search for a technical solution that enables you to
measure the frequency error with more resolution&precision than you have
now. A DIRECT phase comparison between the two oscillators and so a PLL may
be more appropiate to the problem.

Best regards
Ulrich Bangert

<luca_grossi@hotmail.com> schrieb im Newsbeitrag
news:1161151712.672647.312730@m7g2000cwm.googlegroups.com...
> Hi everyone,
> I'm currently using a vitex-II pro FPGA, I've implemented an NCO
> frequency generator, which is supplied with a 64bit init & delta phase
> value. I'm currently using a local oscillator to clock the NCO ( must
> use specific local oscillator) but this does contain a margin of offset
> and drift thus influencing output frequency of NCO. A compensation
> circuit which includes another stable clock is used to correct the
> drift and offset by using a frequency counter on both clocks then
> calculating appropriate delta phase to compensate. My problem is that
> my equation to calculate adjusted delta which requires a 64 bit
> division
>
> Delta2 = (count2/count1) * delta1
>
> Delta2 = new delta phase with correction
> Count2 = frequency counter for Local Oscillator
> Count1 = frequency counter for external Oscillator
> Delta1 = Original calculated delta phase to product output frequency
>
> What would be the most appropriate way of doing this calculation,
> especially with the division? also time constraints, everyone 1.6ms
> roughly this will occur.
> Maybe this could be done differently? Ideas I've been thinking about
> are on the lines of, Maybe reduces the counting resolution ? use
> internal PPC (CPU)
>
> Any advice would be appreciated :)
> Cheers Luca
>



Article: 110647
Subject: Re: ANNC: Open Source, Free 32-bit soft processor webcast
From: "Peter Dickerson" <first{dot}surname@tesco.net>
Date: Thu, 19 Oct 2006 08:30:12 GMT
Links: << >>  << T >>  << A >>
"Eric" <englere_geo@yahoo.com> wrote in message
news:1161195789.664495.67840@m7g2000cwm.googlegroups.com...
>
> bart wrote:
> > Lattice is holding a webcast tomorrow Wednesday, October 18, "Embedded
> > Design with LatticeMico32 Open, Free 32-bit Soft Processor."
>
> I couldn't turn-in, but I'd like to hear comments from people who did!
> It sounds interesting.

The webcast was a little dry. I'm not sure that it said anything new. The
estimated price is $0.80-$2.00 for the cpu part of the FPGA in large volumes
and depending on the FPGA and CPU options. I'm a relatively low-volume sort
so the numbers probably don't mean much for me. However, these sorts of
things are of interest because we have lots of messy I/O.

The do keep pushhing the point that the HDL is open source and not directly
tied to Lattice. You can take the code and synth for another vendor or ASIC.

Peter



Article: 110648
Subject: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
From: Zara <me_zara@dea.spamcon.org>
Date: Thu, 19 Oct 2006 10:33:07 +0200
Links: << >>  << T >>  << A >>
On Thu, 19 Oct 2006 09:50:03 +0200, Zara <me_zara@dea.spamcon.org>
wrote:

>This is not strictly a call for help, it is more of a warning to
>everyone.
<...>


UPS cable will not work with EDK 8.1. Although impact correctly uses
it as USB21, XMD tries to use it as USB22 and finds tha JTAG chain
devices, but not the microblaze within a FPGS. Will file a WebCase
later, if I donīt find some solution. meanwhile, I will install 8,.2
as alternative to 8.1.

Followups will certainly be coming soon.

Zara

Article: 110649
Subject: Re: Problema when upgrading from Xilinx 8.1 to Xilinx 8.2
From: Zara <me_zara@dea.spamcon.org>
Date: Thu, 19 Oct 2006 10:46:24 +0200
Links: << >>  << T >>  << A >>
On Thu, 19 Oct 2006 10:33:07 +0200, Zara <me_zara@dea.spamcon.org>
wrote:

>On Thu, 19 Oct 2006 09:50:03 +0200, Zara <me_zara@dea.spamcon.org>
>wrote:
>
>>This is not strictly a call for help, it is more of a warning to
>>everyone.
><...>
>
>
>UPS cable will not work with EDK 8.1. Although impact correctly uses
>it as USB21, XMD tries to use it as USB22 and finds tha JTAG chain
>devices, but not the microblaze within a FPGS. Will file a WebCase
>later, if I donīt find some solution. meanwhile, I will install 8,.2
>as alternative to 8.1.
>
>Followups will certainly be coming soon.
>
 Pretty soon, really.

If I download the FPGA contents with impact through USB, and then I
try to run XMD, it identifies the JTAG chain but not the jtag_mdm.

If I download the FPGA contents with impact through PC4(3), and then I
try to run XMD, it identifies the JTAG chain, the jtag_mdm, the
Microblaze... everything works fine.

Maybe there is some compatibility problem between impact and xmd? I
suppose so, as there have always been intermittent problems with them
when I switch from one program to the other for debugging purposes.

... to be continued...

Zara



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search