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Mike Treseler wrote: > vasile wrote: > > > - which is the most common configuration methode you'll choose for a > > Stratix II > > It depends what else is on the board. There is a DSP and a parallel flash memory used for DSP bootloader or program holder (and a lot of other stuff). Sharing the same Flash memory between the FPGA and DSP is a hard task because on FPGA initialisation the bus must be released by DSP. > If there is a cpu and flash file system, > loading the fpga image is just one of > many initialization tasks, and I can > ftp an fpga image file directly to > the embedded kernel whenever I like. > > > - how you'll choose the input and output ports (regarding to banks and > > quadrants) > > I like to write and sim the hdl code first > and then let place and route take the first > cut at picking pins. But if this job will be done by someone else ? Thx Mike, VasileArticle: 111076
Hi George, burn....@gmail.com wrote: (snip) >> And I am still waiting for the source code so I can form my own opinion. Jawbreaker wrote: (snip) > don't have time for people who troll newsgroups instead of offering >constructive feedback. > >Be clear, respectful and specific with your questions and feedback, do >your homework and have something to offer. Sorry if it sounded that way, I wasn't out to troll or offend anyone. And I don't have had any "homework" to do the past 10 years, and even if I did, I am not sure how the PhoenixSID could help me cheating. Jan used your project to promote MyHDL. We have all tested the led-blink stuff in MyHDL, what we would like to see more of is a real-world project that shows us how MyHDL scales and deals with real-world problems. For your information, there are many SID clones out there, some public but many more private. I even know a musician who while working as a VLSI engineer "smuggled" a _very_ authentic SID and a simplified 6502 into an ASIC/FPGA project (when they only needed a "beeping" sound). I know it is hard to believe, but I have the prototype board running on my desk, playing old C64 songs. Now, I understand that PhoenixSID is important to you. And I am not underestimating the amount of work you had to put on it. However, if I express my wish to see the code, it does not automatically mean I am trolling or trying to "steal" your code. hope I didn't offend you again, -burns (who writes HDL for living and have multiple open source projects on SourceForge and soon also on OpenCores.org).Article: 111077
Rob wrote: > I see the same thing you do within the editor, master and slave pads. Both > pads have an IO standard of LVDS_25. I have nothing else in my UCF file > pertaining to these pins. > > >> "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message > >> news:12k1op3ddh0iea@corp.supernews.com... > >>> Can anyone tell me what I need to drive a Camera Link > >>> output directly from a V4? I have tried LVCMOS25 and I > >>> can see differential signals at the outputs but at the > >>> end of a 2 meter cable I see only DC differential levels > >>> as if the signals are dampened somehow. Brad, It is a good idea to explicitly call out IO standards in the UCF. I am a fan of determinism. The LVCMOS25 default for a differential pair *might* have to do with these signals being on low capacitance pins (denoted "_LC_" in the pinout table) which do not support LVDS outputs. If you call out LVDS in the UCF you *should* get an error if these are the type of IO pins that your signals are attached to. N.B. This is all conjecture, with the exception of the fact that the low capacitance pins do not support LVDS outputs. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.comArticle: 111078
Brad Smallridge wrote: > Can anyone tell me what I need to drive a Camera Link > output directly from a V4? I have tried LVCMOS25 and I > can see differential signals at the outputs but at the > end of a 2 meter cable I see only DC differential levels > as if the signals are dampened somehow. I'm assuming that you meant the LVDS_25 driver. Don't forget the LVDSEXT_25, which is meant for longer cable driving. --- Joe Samson Pixel VelocityArticle: 111079
MM wrote: > I am getting from time to time garbage (all signals high) displayed in the > Chipscope after successful triggering (which would not have happened if all > the signals were indeed high). The debugger (gdb) seems to indicate that the > transaction was in fact successful... So, I was wondering if anyone else has > seen this problem and whether it has anything to do to the fact that I am > using the same JTAG port for both? I run xmd and chipscope together all the time on the same JTAG port. In fact, recently I was debugging 2 different systems simultaneously with one JTAG cable. I'd plug into one system and do some xmd commands, unplug the flying leads, plug into the other board and trigger chipscope. Nither was confused. Did you have any timing errors after routing the chip with the chipscope inserted? That might cause errors in the ChipScope display. --- Joe Samson Pixel VelocityArticle: 111080
Yipes, duh. My problem is that I don't understand this cable and my lines are mirrored. Thanks, though, for all your help. I am sure it will work when I connect the right signals. Say, I was getting good results from a double edge clock input circuit and a single DCM generating 140 MHz (40MHz xclk). The trick was to select a shifted output depending on the fast clock. I was unable, however, to use a double edge clock circuit on the output. The OSERDES does not have a 7x option and when you try 8x you get 8x data bits no matter how you drive the clkdiv input. Do you have anysuggestions here? Brad Smallridge aivision "Erik Widding" <widding@birger.com> wrote in message news:1162047692.852989.299520@h48g2000cwc.googlegroups.com... > Rob wrote: >> I see the same thing you do within the editor, master and slave pads. >> Both >> pads have an IO standard of LVDS_25. I have nothing else in my UCF file >> pertaining to these pins. >> >> >> "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message >> >> news:12k1op3ddh0iea@corp.supernews.com... >> >>> Can anyone tell me what I need to drive a Camera Link >> >>> output directly from a V4? I have tried LVCMOS25 and I >> >>> can see differential signals at the outputs but at the >> >>> end of a 2 meter cable I see only DC differential levels >> >>> as if the signals are dampened somehow. > > Brad, > > It is a good idea to explicitly call out IO standards in the UCF. I am > a fan of determinism. The LVCMOS25 default for a differential pair > *might* have to do with these signals being on low capacitance pins > (denoted "_LC_" in the pinout table) which do not support LVDS outputs. > If you call out LVDS in the UCF you *should* get an error if these are > the type of IO pins that your signals are attached to. > > N.B. This is all conjecture, with the exception of the fact that the > low capacitance pins do not support LVDS outputs. > > > Regards, > Erik. > > --- > Erik Widding > President > Birger Engineering, Inc. > > (mail) 100 Boylston St #1070; Boston, MA 02116 > (voice) 617.695.9233 > (fax) 617.695.9234 > (web) http://www.birger.com >Article: 111081
vasile wrote:
> There is a DSP and a parallel flash memory used for DSP bootloader or
> program holder (and a lot of other stuff).
> Sharing the same Flash memory between the FPGA and DSP is a hard task
> because on FPGA initialisation the bus must be released by DSP.
I would use a few ports bits from the DSP
to load the FPGA. No need to share the bus.
>> I like to write and sim the hdl code first
>> and then let place and route take the first
>> cut at picking pins.
> But if this job will be done by someone else ?
I would wait until that "someone else" had
working code before I started a circuit board.
-- Mike Treseler
Article: 111082Hi All, What is the easiest/best approach to attach Wifi to Virtex-4 (using from Linux)? Id' like to use some longer range/higher rate wifi module (eg. atheros). Any suggestions/ideas/eval boards? Regards, ZoltanArticle: 111083
Davy wrote: > Hi all, > > IMHO, there is something compare the golden output and DUT output in > testbench (I call it Checker). But in verification book, there is both > Scoreboard and Checker. Are they similar? Scoreboard is mainly used to check the functional property correctness of a DUT. eg. whether a certain functional algorithm of the DUT works correctly. Checker is used to verify the protocol on the DUT interface output. ie. whether the timing of certain transactions are correct or not. Mainly it is used to verify whether the output signals of the DUT confiorm to a specific protocol eg. Ambd AXI. Hope this is a clear definition. I would have checkers in my testbench to flag an error on protocol error before the scoreboard checks the actual output of the DUT. Don > > Please recommend some reading on it.Thanks! > > Best regards, > DavyArticle: 111084
I am not sure what you mean but a Pentium or even the new PIV can run old programs well. i486 is backward compatible means that new processors will support older chips as well. Unless you want to just change the chip and KEEP rest of the remaining circuit. In that case I suggest you decouple the mainboard from the system and replace it with a new board. There are still boards running i486 for SBC.. john On 24 Oct 2006 00:17:53 -0700, enavacchia@virgilio.it wrote: >enavacchia@virgilio.it ha scritto: >> >> Any suggestions? >> >Thank you all for your extensive explanations and suggestions! >The i486 constraint comes from the main specification to not modify any >part of the operating system. I've the complete source code (written >many years ago in PL/M386), but we decided that porting to another >platform or re-validate another core (pentium, transmeta, via, geode >...) is not possible... Maybe we'd better reconsider the >specifications! > >I think we'll use FPGA for glue logic, ram interfacing and dual port >ram emulation, and leave the processor as an off the shelf device... > >Regards, >Eugenio.Article: 111085
Peter Alfke wrote: > Well, in the beginning of my professional life, I built flip-flops out > of two Ge transistors, 8 resistors, two diodes and two capacitors. > Remember, the term J-K flip-flop comes from a standardized sinle-FF > pc-board where the connector oins were labeled A-Z, and the set and > reset inputs were on the adjacent central pins J and K. > Not a joke... > Peter Alfke > > On Oct 27, 4:53 pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > >>PeteS wrote: >> >>>Jim Granville wrote: >> >>>>PeteS wrote: >> >>>>>I have had *true* metastable problems (where an output would float, >>>>>hover, oscillate and eventually settle after some 10s of >>>>>*milliseconds*), but those I have seen recently don't qualify :) >> >>>>Can you clarify the device/process/circumstances ? >> >>>>-jg >> >>>This was a discrete design with FETs that I was asked to test (at a >>>customer site). The feedback loop was not particularly well done, so >>>when metastability did occur, it was spectacular.Do you mean they built a D-FF, using discrete FETS ?! >> >>I have seen transistion oscillations (slow edges) cause very strange >>effects in Digital Devices, but I'd not call that effect metastability. >> >>-jg > > Amusing I too have made flip flops from discrete parts in the distant past. The metastable problem I encountered was due to slow rising inputs on pure CMOS (a well known issue) and was indeed part of the feedback path. I remember making a D FF using discrete parts only a few years ago because it had to operate at up to 30VDC. I had to put all the usual warnings on the schematic page about setup/hold times etc. There are times when the knowledge of just what a FF (be it JK, D or M/S) is comes in _real_ handy. Cheers PeteSArticle: 111086
Mike Treseler" <mike_treseler@comcast.net> wrote in message news:4qhgliFn7pbaU1@individual.net... > vasile wrote: > >>> I like to write and sim the hdl code first >>> and then let place and route take the first >>> cut at picking pins. > >> But if this job will be done by someone else ? > > I would wait until that "someone else" had > working code before I started a circuit board. > Hi Guys, FWIW, here's my 2 cents. I prefer to let the PCB layout person decide the detailed pinout. One reason I do this is because the routing resource in the FPGA is cheaper than on the PCB. Also, I find that signal integrity can be compromised by having to route PCB signals according to the P&R method. So, I tend to place the major components on my PCB, use that to guide on which banks I have which signals, but then let the exact pinout be decided by the PCB routing requirements. Then start my RTL design while someone is making the boards. HTH, Syms.Article: 111087
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:12k72t98o3ahrcc@corp.supernews.com... > > I was unable, however, to use a double edge clock circuit > on the output. The OSERDES does not have a 7x option and > when you try 8x you get 8x data bits no matter how you > drive the clkdiv input. Hi Brad, (You can now spend all evening wondering where I know you from...) I can't shed any light on your Virtex problems, but I am interested as to what leads you to bother with trying to do CameraLink with an FPGA, rather than just using the appropriate NatSemi ChannelLink chip (I'm too lazy to look up the number, but you know the one I mean.) When everything about CameraLink is designed around those interface chips, it has always seemed to me like unnecessarily hard work to reimplement their behaviour elsewhere. Is it cost, space or a sense of adventure which pushes you away from them in this design? Cheers, WillArticle: 111088
We had a discussion at lunch, about the future when us dinosaurs are gone. Who will then understand those subtleties, only the tiny cadre of IC designers? Many new college graduates' eyes glaze over when I ask them about the way a flip-flop works, and how it avoids a race condition in a shift register. And clock skew and hold-time issues. Hard-earned "wisdom"... Peter Alfke On Oct 28, 12:02 pm, PeteS <peter.smith8...@ntlworld.com> wrote: > Peter Alfke wrote: > > Well, in the beginning of my professional life, I built flip-flops out > > of two Ge transistors, 8 resistors, two diodes and two capacitors. > > Remember, the term J-K flip-flop comes from a standardized sinle-FF > > pc-board where the connector oins were labeled A-Z, and the set and > > reset inputs were on the adjacent central pins J and K. > > Not a joke... > > Peter Alfke > > > On Oct 27, 4:53 pm, Jim Granville <no.s...@designtools.maps.co.nz> > > wrote: > > >>PeteS wrote: > > >>>Jim Granville wrote: > > >>>>PeteS wrote: > > >>>>>I have had *true* metastable problems (where an output would float, > >>>>>hover, oscillate and eventually settle after some 10s of > >>>>>*milliseconds*), but those I have seen recently don't qualify :) > > >>>>Can you clarify the device/process/circumstances ? > > >>>>-jg > > >>>This was a discrete design with FETs that I was asked to test (at a > >>>customer site). The feedback loop was not particularly well done, so > >>>when metastability did occur, it was spectacular.Do you mean they built a D-FF, using discrete FETS ?! > > >>I have seen transistion oscillations (slow edges) cause very strange > >>effects in Digital Devices, but I'd not call that effect metastability. > > >>-jgAmusing > > I too have made flip flops from discrete parts in the distant past. The > metastable problem I encountered was due to slow rising inputs on pure > CMOS (a well known issue) and was indeed part of the feedback path. > > I remember making a D FF using discrete parts only a few years ago > because it had to operate at up to 30VDC. I had to put all the usual > warnings on the schematic page about setup/hold times etc. > > There are times when the knowledge of just what a FF (be it JK, D or > M/S) is comes in _real_ handy. > > Cheers > > PeteSArticle: 111089
Peter Alfke wrote: > We had a discussion at lunch, about the future when us dinosaurs are > gone. > Who will then understand those subtleties, only the tiny cadre of IC > designers? > Many new college graduates' eyes glaze over when I ask them about the > way a flip-flop works, and how it avoids a race condition in a shift > register. And clock skew and hold-time issues. > Hard-earned "wisdom"... > Peter Alfke > > On Oct 28, 12:02 pm, PeteS <peter.smith8...@ntlworld.com> wrote: > >>Peter Alfke wrote: >> >>>Well, in the beginning of my professional life, I built flip-flops out >>>of two Ge transistors, 8 resistors, two diodes and two capacitors. >>>Remember, the term J-K flip-flop comes from a standardized sinle-FF >>>pc-board where the connector oins were labeled A-Z, and the set and >>>reset inputs were on the adjacent central pins J and K. >>>Not a joke... >>>Peter Alfke >> >>>On Oct 27, 4:53 pm, Jim Granville <no.s...@designtools.maps.co.nz> >>>wrote: >> >>>>PeteS wrote: >> >>>>>Jim Granville wrote: >> >>>>>>PeteS wrote: >> >>>>>>>I have had *true* metastable problems (where an output would float, >>>>>>>hover, oscillate and eventually settle after some 10s of >>>>>>>*milliseconds*), but those I have seen recently don't qualify :) >> >>>>>>Can you clarify the device/process/circumstances ? >> >>>>>>-jg >> >>>>>This was a discrete design with FETs that I was asked to test (at a >>>>>customer site). The feedback loop was not particularly well done, so >>>>>when metastability did occur, it was spectacular.Do you mean they built a D-FF, using discrete FETS ?! >> >>>>I have seen transistion oscillations (slow edges) cause very strange >>>>effects in Digital Devices, but I'd not call that effect metastability. >> >>>>-jgAmusing >> >>I too have made flip flops from discrete parts in the distant past. The >>metastable problem I encountered was due to slow rising inputs on pure >>CMOS (a well known issue) and was indeed part of the feedback path. >> >>I remember making a D FF using discrete parts only a few years ago >>because it had to operate at up to 30VDC. I had to put all the usual >>warnings on the schematic page about setup/hold times etc. >> >>There are times when the knowledge of just what a FF (be it JK, D or >>M/S) is comes in _real_ handy. >> >>Cheers >> >>PeteS > > Well, I am not an IC designer (well, not regularly). Perhaps the answer is education - real education. The new crowd doesn't seem to understand the fundamentals that are key to successful design of any type be it IC, board level or any other. Like the other dinosaurs, I've seen and done things most youngsters don't even consider, but the youngsters that have been around when *I did them* were awed, and they wanted to learn, so I think there's hope. I am sure the youngsters that were around when *you* have done astounding things (to them) were awed too. Perhaps it's a matter of making sure they understand the limitations of their current knowledge :) It's different in a way - we were *figuring out* what made things work; nowadays it's taken for granted. We need to make sure the kids understand that this knowledge is key to successful design. Cheers PeteSArticle: 111090
Peter Alfke wrote: > We had a discussion at lunch, about the future when us dinosaurs are > gone. > Who will then understand those subtleties, only the tiny cadre of IC > designers? > Many new college graduates' eyes glaze over when I ask them about the > way a flip-flop works, and how it avoids a race condition in a shift > register. And clock skew and hold-time issues. > Hard-earned "wisdom"... > Peter Alfke > > On Oct 28, 12:02 pm, PeteS <peter.smith8...@ntlworld.com> wrote: > >>Peter Alfke wrote: >> >>>Well, in the beginning of my professional life, I built flip-flops out >>>of two Ge transistors, 8 resistors, two diodes and two capacitors. >>>Remember, the term J-K flip-flop comes from a standardized sinle-FF >>>pc-board where the connector oins were labeled A-Z, and the set and >>>reset inputs were on the adjacent central pins J and K. >>>Not a joke... >>>Peter Alfke >> >>>On Oct 27, 4:53 pm, Jim Granville <no.s...@designtools.maps.co.nz> >>>wrote: >> >>>>PeteS wrote: >> >>>>>Jim Granville wrote: >> >>>>>>PeteS wrote: >> >>>>>>>I have had *true* metastable problems (where an output would float, >>>>>>>hover, oscillate and eventually settle after some 10s of >>>>>>>*milliseconds*), but those I have seen recently don't qualify :) >> >>>>>>Can you clarify the device/process/circumstances ? >> >>>>>>-jg >> >>>>>This was a discrete design with FETs that I was asked to test (at a >>>>>customer site). The feedback loop was not particularly well done, so >>>>>when metastability did occur, it was spectacular.Do you mean they built a D-FF, using discrete FETS ?! >> >>>>I have seen transistion oscillations (slow edges) cause very strange >>>>effects in Digital Devices, but I'd not call that effect metastability. >> >>>>-jgAmusing >> >>I too have made flip flops from discrete parts in the distant past. The >>metastable problem I encountered was due to slow rising inputs on pure >>CMOS (a well known issue) and was indeed part of the feedback path. >> >>I remember making a D FF using discrete parts only a few years ago >>because it had to operate at up to 30VDC. I had to put all the usual >>warnings on the schematic page about setup/hold times etc. >> >>There are times when the knowledge of just what a FF (be it JK, D or >>M/S) is comes in _real_ handy. >> >>Cheers >> >>PeteS > > There was a TV show perhaps 20 years ago the name of which I do not remember. In it, the computer that ran the spacecraft (named Mentor because the female of the group had thought the name) refused to give information about using the transporter system. It said 'Wisdom is earned, not given' Cheers PeteSArticle: 111091
> Lattice offer Soft CPUs like the Mico8 and they need to store the > Opcodes in ROM. That means there must be an Opcode-> ROM pathway, for > their parts ( ie using BRAM as ROM ). > Why not look at the Mico8 flows for that, and put your > Serial#/Calibration infos into the psuedo ROM space ? No where close to enough space. The largest XO2280 has only 3 block rams. I have to burn two of those just for my 32 bit dual port ram. The 3rd one gets used to hold 512 instructions for the CPU, and that may not even be enough instructions. I need 16k bits more for my other app data storage. No where to put it. Chris.Article: 111092
scott moore wrote: > rponsard@gmail.com wrote: >> is that a known bug ? >> >> ISE 8.2 / win XP seems to freeze while synthesing design (no more mouse >> or menu/button action event response... looks like a threading bug) >> >> at the end of computation, it comes back to normal execution. >> > > If it completes the operation, its a feature, not a bug. Many, or even > MOST windows apps don't multithread their user interface. In fact, > Windows isn't particularly good at it, there are known issues with two > threads trying to access the GUI at once. > > Scott Moore Quite true. I have written some multi-threaded programs that had more than one thread accessing GUI elements and avoiding crashes/hangs requires a fair amount of fancy footwork. In the end, I gave up on accessing the GUI directly and settled on building futex-protected event lists and posting triggers on the message queue whenever I wanted the GUI to process a given list. The major down-side of this method is the sequential nature of the message queue that may stall the GUI for quite a while, it very much defeats bothering with threads in the first place. Since some libraries and APIs require that the caller be a GUI-bound thread, things tend to get weird, unelegant and inefficient. I wish OSes, GUIs and apps would go all-asynchronous-IO (with zero-copy) and multi-threaded faster. This would reduce the amount of stalling we see every day and improve overall system efficiency by a nice margin... but that is not going to happen until enough coders manage to undo 10+ years of bad coding habbits and effectively apply contemporary IO models/APIs. In any case, I am not doing much PC programming anymore and when I think about how few significant changes in software models I have seen over the last ~10 years, I am glad I chose to go with hardware back then. Hardware platforms renew themselves every 2-5 years but OSes, their APIs and software using them have not really renewed themselves in over 20 years... they're only expanding, building up bloat and overhead. With multi-CPU computing becoming a home desktop reality, all serious software programmers will have to get up to speed with and apply HPC-style programming techniques. This could be the most interesting evolution in software development since multitasking OSes. Let's hope some of this will eventually filter through Xilinx's software people and produce smoother and faster-riding ISEs in the (preferably near) future. -- Daniel Sauvageau moc.xortam@egavuasd Matrox Graphics Inc. 1155 St-Regis, Dorval, Qc, Canada 514-822-6000Article: 111093
Chris wrote: >> Lattice offer Soft CPUs like the Mico8 and they need to store the >>Opcodes in ROM. That means there must be an Opcode-> ROM pathway, for >>their parts ( ie using BRAM as ROM ). >> Why not look at the Mico8 flows for that, and put your >>Serial#/Calibration infos into the psuedo ROM space ? > > > No where close to enough space. The largest XO2280 has only 3 block rams. > I have to burn two of those just for my 32 bit dual port ram. The 3rd one > gets used to hold 512 instructions for the CPU, and that may not even be > enough instructions. I need 16k bits more for my other app data storage. > No where to put it. Hmm, 16k is quite a lot more than I expected for the statement "need to store serial numbers and calibration data on the product somewhere." It's also likely to be more than a CPLD vendor will put in the corner "for free", so at that level you will have to use an off chip EE (SOT23?) solution, or a small uC as a "smarter EE" -jgArticle: 111094
Jon Elson <jmelson@artsci.wustl.edu> writes: > Signetics N3002 or something like that. Signetics was a second source of the Intel 3001 and 3002 bit slice components. > Made the AMD 29xx > series of bit slices look as well planned as the IBM 360 or something, > by comparison. Yes. Much easier to deal with than the 3001/3002 parts. The AMD 2901 4-bit part was based on the MMI 5701/6701 bit slice design. Reportedly one of the engineers left MMI to work for AMD, and AMD managed to get the very similar but not 100% compatible 2901 design to market first. Raytheon second-sourced it (as did National Semiconductor later), and it took off for military applications due to the availability of a second source (an absolute requirement back then). > I had some kind of disk controller that used them, I think. Intel used the 300x parts in their own disk controllers, naturally. For instance, they had the iSBC 201 and iSBC 202 floppy disk controllers for Multibus, which each consisted of a channel board and an interface baord. The channel board had the 300x components and was the brains of the controller as well as a DMA engine. The 300x were probably also used in Intel's hard drive controllers of that era (back when the hard drives were 8-inch or 14-inch, before the new-fangled 5.25-inch stuff). I'm not familiar with any other 300x based disk controllers, but there probably were some. There were many vendors with 290x-based disk controllers, and also many using the Signetics 8X300 or 8X305 (10 MHz bipolar microprocessor, but not a bit-slice).Article: 111095
Will, > Is it cost, space or a sense of adventure which pushes you away from them > in this design? I know you addressed this to Brad, but my answer would be all of the above. I would counter your question with: if your design necessiates an FPGA, and that FPGA is capabable of performing the deserialization, why would you use the National chips? It might be more involved than letting the National chips do it for you; but the big players in the FPGA market have prebuilt modules fitted to the most standard Camera Link/Channel Link type interfaces. Sure, if you have to build your own, it can get tricky with setup/hold times, jitter, skew, and clock phasing--but what's life w/o challenges? Best regards, Rob "Will Dean" <will@nospam.demon.co.uk> wrote in message news:4543c522$0$624$bed64819@news.gradwell.net... > "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message > news:12k72t98o3ahrcc@corp.supernews.com... >> >> I was unable, however, to use a double edge clock circuit >> on the output. The OSERDES does not have a 7x option and >> when you try 8x you get 8x data bits no matter how you >> drive the clkdiv input. > > Hi Brad, (You can now spend all evening wondering where I know you > from...) > > I can't shed any light on your Virtex problems, but I am interested as to > what leads you to bother with trying to do CameraLink with an FPGA, rather > than just using the appropriate NatSemi ChannelLink chip (I'm too lazy to > look up the number, but you know the one I mean.) > > When everything about CameraLink is designed around those interface chips, > it has always seemed to me like unnecessarily hard work to reimplement > their behaviour elsewhere. > > Is it cost, space or a sense of adventure which pushes you away from them > in this design? > > Cheers, > > Will > > >Article: 111096
David R Brooks <davebXXX@iinet.net.au> writes: > To split the difference, you could use Motorola's 14500 1-bit > CPU. Yes, this is/was a real product! Yes, a one-bit CPU. It contains all of eight flip-flops, and a little bit of combinatorial logic. It does not contain a program counter; the user is expected to provide one, and a stack if desired. There's a completely untested VHDL model at http://www.brouhaha.com/~eric/retrocomputing/motorola/mc14500b/mc14500b.vhdl It synthesizes to use 14 macrocells of an XC9536. It would probably fit in a 22V10 or maybe even a 20V8. If anyone needs such a thing commercially, my arm could be twisted into verifying the model against the actual part.Article: 111097
There is a difference, 60 years ago, a curious kid could at least try to understand the world around him/her. Clocks, carburators, telephones, radios, typewriters, etc. Nowadays, these functions are black boxes that few people really understand, let alone are able to repair. Youngsters today can breathe life into a pc by hitting buttons in mysterious sequences... Do they really understand what they are doing or what's going on? "If the engine stalls, roll down the window" :-) Here is a simple test, flunked by many engineers: How can everybody smoothely adjust the heat of an electric stove, or a steam iron ? Hint: It is super-cheap, no Variac, no electronics. Smoke and mirrors? Answer: it's slow pulse-width modulation, controlled by a self-heating bimetal strip. Cost: pennies... Well, the older generation has bemoaned the superficiality of the younger generation, ever since Socrates did so, a hundred generations ago. Maybe there is hope... Peter Alfke On Oct 28, 3:24 pm, PeteS <peter.smith8...@ntlworld.com> wrote: > Peter Alfke wrote: > > We had a discussion at lunch, about the future when us dinosaurs are > > gone. > > Who will then understand those subtleties, only the tiny cadre of IC > > designers? > > Many new college graduates' eyes glaze over when I ask them about the > > way a flip-flop works, and how it avoids a race condition in a shift > > register. And clock skew and hold-time issues. > > Hard-earned "wisdom"... > > Peter Alfke > > > On Oct 28, 12:02 pm, PeteS <peter.smith8...@ntlworld.com> wrote: > > >>Peter Alfke wrote: > > >>>Well, in the beginning of my professional life, I built flip-flops out > >>>of two Ge transistors, 8 resistors, two diodes and two capacitors. > >>>Remember, the term J-K flip-flop comes from a standardized sinle-FF > >>>pc-board where the connector oins were labeled A-Z, and the set and > >>>reset inputs were on the adjacent central pins J and K. > >>>Not a joke... > >>>Peter Alfke > > >>>On Oct 27, 4:53 pm, Jim Granville <no.s...@designtools.maps.co.nz> > >>>wrote: > > >>>>PeteS wrote: > > >>>>>Jim Granville wrote: > > >>>>>>PeteS wrote: > > >>>>>>>I have had *true* metastable problems (where an output would float, > >>>>>>>hover, oscillate and eventually settle after some 10s of > >>>>>>>*milliseconds*), but those I have seen recently don't qualify :) > > >>>>>>Can you clarify the device/process/circumstances ? > > >>>>>>-jg > > >>>>>This was a discrete design with FETs that I was asked to test (at a > >>>>>customer site). The feedback loop was not particularly well done, so > >>>>>when metastability did occur, it was spectacular.Do you mean they built a D-FF, using discrete FETS ?! > > >>>>I have seen transistion oscillations (slow edges) cause very strange > >>>>effects in Digital Devices, but I'd not call that effect metastability. > > >>>>-jgAmusing > > >>I too have made flip flops from discrete parts in the distant past. The > >>metastable problem I encountered was due to slow rising inputs on pure > >>CMOS (a well known issue) and was indeed part of the feedback path. > > >>I remember making a D FF using discrete parts only a few years ago > >>because it had to operate at up to 30VDC. I had to put all the usual > >>warnings on the schematic page about setup/hold times etc. > > >>There are times when the knowledge of just what a FF (be it JK, D or > >>M/S) is comes in _real_ handy. > > >>Cheers > > >>PeteSThere was a TV show perhaps 20 years ago the name of which I do not > remember. In it, the computer that ran the spacecraft (named Mentor > because the female of the group had thought the name) refused to give > information about using the transporter system. > > It said 'Wisdom is earned, not given' > > Cheers > > PeteSArticle: 111098
Hello, all -- I'm beginning to do some work in the efficient mapping of intensive algorithms (high orders of complexity) into hardware. I was hoping that some of you with similar experience may be able to suggest some resources -- textbooks, journals, websites -- of particular interest. Your input is greatly appreciated. Sincerely, Julian KainArticle: 111099
Zoltan For a hardware platform our Broaddown4 product fitted with a CFCARD Wi-Fi module is one possible way if you are using MicroBlaze. If you want PowerPC then we have some other options coming very shortly. If you are interested in the other options and you can wait a few weeks then contact me for more details. John Adair Enterpoint Ltd. zcsizmadia@gmail.com wrote: > Hi All, > > What is the easiest/best approach to attach Wifi to Virtex-4 (using > from Linux)? Id' like to use some longer range/higher rate wifi module > (eg. atheros). > > Any suggestions/ideas/eval boards? > > Regards, > > Zoltan
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