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Antti wrote: >PS I an I almost had some experiene with 2 bit processors, >dont recall the part type any more but I had some of them >in my hands. Well didnt ever make a PCB for them. Was >some funky military 2 bit wide bit-slice thing. > > Signetics N3002 or something like that. Made the AMD 29xx series of bit slices look as well planned as the IBM 360 or something, by comparison. I had some kind of disk controller that used them, I think. Jon > >Article: 110926
Dave Pollum schrieb: > Antti wrote: > > Dave Pollum schrieb: > > > > > Antti wrote: > > > > > > > > I had cold recently too. > > > > But I am serious about designing and soft-core that uses 0 slices, 0 > > > > luts and 0 FF's :) > > > > > > > And this design has no inputs, outputs, or clocks, either? > > > -Dave > > Why? > > > > it is a clocked desing with lots of inputs and outputs, > > no problems with them at all. > > > > it is really doable and fun thing to design. > > > > Antti > > Hmmm....I wasn't sure if you were joking when you said "0 slices, 0 > luts and 0 FF's". I assumed that there was nothing left. I'm guessing > that I/O buffers, clock logic, and interconnect circuitry would be left > (I'm faimiliar with CPLDs, but I'm still learning about FPGAs). > -Dave Pollum no, I wasnt joking. meaning a design that yields to "0 slice" report those 0 luts and 0 FF in slices. there aredifferent other resources to use, well depends on target family of course AnttiArticle: 110927
Hi all, After some hardware problems with our protoype I have been advised to use a board. But I cannot find one with all the features. 1) VGA in and out ports 2) SDR SDRAM. I have looked at digilentinc and xess but these people dont have any that fits all requirements. I have the XUP V2P board with the video capture card and 256MB DDR SDRAM. How difficult will it be for me to use the DDR SDRAM. Can I try to use the DDR SDRAM as an SDR SDRAM? Any suggestions are appreciated. Thanks Subhasri.KArticle: 110928
Subhasri krishnan schrieb: > Hi all, > After some hardware problems with our protoype I have been advised to > use a board. But I cannot find one with all the features. > 1) VGA in and out ports > 2) SDR SDRAM. > I have looked at digilentinc and xess but these people dont have any > that fits all requirements. I have the XUP V2P board with the video > capture card and 256MB DDR SDRAM. How difficult will it be for me to > use the DDR SDRAM. Can I try to use the DDR SDRAM as an SDR SDRAM? > Any suggestions are appreciated. > Thanks > Subhasri.K 1 SDR and DDR memories require different controller ip-cores 2 there is no FPGA board with VGA input, its quite complicated, there are 3 companies producing VGA digitizer, 2 of them dont sell in less 30,000 pcs/year customers. So the only one chip available is averlogic AL875 that requires extra PLL to work. 3 VGA out is simple AnttiArticle: 110929
Based on the info posted on the web: http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/advantages/memory_interfaces.htm http://www.xilinx.com/products/design_resources/mem_corner/index.htm The number of data pins is over 400 for RLDRAM II: 259Gbps/600bps/pin = 432. HTH, Jim http://home.comcast.net/~jimwu88/tools/ Your name wrote: > Hi there, > > I'm trying to decide on which FPGA vendor to use for a project out of > Xilinx and Altera. The one we chose will depend on a certain memory > bandwidth being met so I'm interested in the maximum supported bus widths. > > I'm currently heading down the RLDRAM route and have been trying to figure > out how many devices are supported on the larger Virtex-4 devices. Does > anyone have any experience of implementing this memory on Xilix? I've > searched through the Xilinx doco and have come up with nothing concrete at > all. The Altera doco clearly states the number of devices supported for > each device and is generally much better quality. > > Any help appreciated. SJ. > > -- > Posted via a free Usenet account from http://www.teranews.comArticle: 110930
It happens in a Virtex-E There's a 1M cycles test pattern on a 10 bit data bus with an ENABLE signal (high for 1 M cycles) indicates data valid. The pattern is clocked at 40 MHZ (0_degree) The data & enable is then fed into an accumulator with input registered. The ACC does the sum for exact 1M cycles. The ACC and its input register is clocked with the 90 degree phase shift The 0_degree and 90_degree clocks are DLL outputs (please dont ask why it has to cross to the 90 degree). DLL has been locked long time before ACC start (enbale high) PAR post timing well passes the 40 MHz constraint Here's what happens The accumulator once a while (about 1 out of 100) gives a random wrong result. If I put another 90 degree clocked register before the ACC, it fixes the problem. it seems not the setup time violation since 25/4 = 6.25ns is much longer than the requirementArticle: 110931
Jon Elson schrieb: > Antti wrote: > > >PS I an I almost had some experiene with 2 bit processors, > >dont recall the part type any more but I had some of them > >in my hands. Well didnt ever make a PCB for them. Was > >some funky military 2 bit wide bit-slice thing. > > > Signetics N3002 or something like that. Made the AMD 29xx > series of bit slices look as well planned as the IBM 360 or something, > by comparison. I had some kind of disk controller that used them, > I think. > > Jon > what I had was K589 IK 2, see here http://www.stepp-ke.de/geschichte/microproc_SU.htm its 3002 compatible, so you guessed right :) the 589 was boring, but some 583 family was in real beatiful rose ceramic with golden leads AnttiArticle: 110932
Have a look at the ADV7202 that we support as an add-on for our boards. I think that can be used to do the VGA input digitising and the opposite on the way out. I think we can do something on the SDR too but I will have to check release dates for that one. John Adair Enterpoint Ltd. Subhasri krishnan wrote: > Hi all, > After some hardware problems with our protoype I have been advised to > use a board. But I cannot find one with all the features. > 1) VGA in and out ports > 2) SDR SDRAM. > I have looked at digilentinc and xess but these people dont have any > that fits all requirements. I have the XUP V2P board with the video > capture card and 256MB DDR SDRAM. How difficult will it be for me to > use the DDR SDRAM. Can I try to use the DDR SDRAM as an SDR SDRAM? > Any suggestions are appreciated. > Thanks > Subhasri.KArticle: 110933
John Adair schrieb: > Have a look at the ADV7202 that we support as an add-on for our boards. > I think that can be used to do the VGA input digitising and the > opposite on the way out. John, ADV7202 supports NTSC/PAL/SECAM input, not VGA input, there are very chips that do VGA input they are moslty used in LCD monitors AnttiArticle: 110934
But you can digitise it. Antti wrote: > John Adair schrieb: > > > Have a look at the ADV7202 that we support as an add-on for our boards. > > I think that can be used to do the VGA input digitising and the > > opposite on the way out. > > John, > > ADV7202 supports NTSC/PAL/SECAM input, not VGA input, > there are very chips that do VGA input they are moslty used > in LCD monitors > > AnttiArticle: 110935
Your name schrieb: > Hi there, > > I've recently installed the Xilinx ISE toolset so that I can play with the > Memory Interface Generator. I followed the readme and installed ISE 8.1i, > 8.1i_SP3 and then MIG 1.6. When I open CORE Generator and select MIG from > the drop down list nothing happens. I get the "Customise" and "View Data > Sheet" links but when I click on them nothing happens. > > Is there another download that I've missed or is the Xilinx software just > flaky? > > Thanks. > browse where the mig is installed, somewhere deep deep you find some batch files, those start MIG OK, but you may need to modify the .in files to get the projects settings right fromt the coregen gui mig 1.6 doesnt want to start :( AnttiArticle: 110936
While I am playing Altera support ;-) Since there inevitably will be either 1 or 2 (never more) rising clock edges during the pulse, just put a 2-input AND gate in front of the D-input, and feed it with the pulse, and on its other input with the inverted Q. That means, once set, the flip-flop will inevitably be reset on the next clock edge. Peter Alfke On Oct 25, 11:45 am, Ben Twijnstra <btwijns...@gmail.com> wrote: > Ben Twijnstra wrote:Hmmm... Seem to have forgotten the bits where snagged is set to '0' again - > I'll trust everyone's intelligence to add the appropriate two statements. > > Best regards, > BenArticle: 110937
Peter Alfke schrieb: > While I am playing Altera support ;-) so it looks! BTW, there is an "A" in your name too ;) uups in mine too AnttiArticle: 110938
Peter Alfke wrote: > ...Through the XC3000 and XC4000 generations, I put together > every databook, from deciding the format and pagination to writing much > of the text, to negotiating the detailed descriptions and even the > parameter values. It was pretty much a one-man show. But the parts were > simple... > Then Xilinx got bigger and various people had to share the "fun"....>>> I met you in 1999, Peter. I won't say where, lest I reveal my identity. You bragged about how Xilinx "..doesn't have technical writers. Our engineers do our writing...>>> Quite frankly, sir, it shows.Article: 110939
Whatever it is, it ain't metastability! Peter Alfke On Oct 25, 12:53 pm, "Marlboro" <cco...@netscape.net> wrote: > It happens in a Virtex-E > > There's a 1M cycles test pattern on a 10 bit data bus with an ENABLE > signal (high for 1 M cycles) indicates data valid. The pattern is > clocked at 40 MHZ (0_degree) > > The data & enable is then fed into an accumulator with input > registered. The ACC does the sum for exact 1M cycles. The ACC and its > input register is clocked with the 90 degree phase shift > > The 0_degree and 90_degree clocks are DLL outputs (please dont ask why > it has to cross to the 90 degree). DLL has been locked long time > before ACC start (enbale high) > > PAR post timing well passes the 40 MHz constraint > > Here's what happens > > The accumulator once a while (about 1 out of 100) gives a random wrong > result. If I put another 90 degree clocked register before the ACC, > it fixes the problem. it seems not the setup time violation since 25/4 > = 6.25ns is much longer than the requirementArticle: 110940
John Adair schrieb: > But you can digitise it. > NOPS, ASFAIK you cant use ADV7202 to digitize VGA input signals I have studied the subject. the only obtainable chip that can digitize VGA inputs is AL875 from averlogic, and it requires external genlock chip, the datasheet says it has internal PLL but that doesnt work actually AnttiArticle: 110941
Marlboro wrote: > It happens in a Virtex-E > > Here's what happens > > The accumulator once a while (about 1 out of 100) gives a random wrong > result. If I put another 90 degree clocked register before the ACC, > it fixes the problem. it seems not the setup time violation since 25/4 > = 6.25ns is much longer than the requirement 'it seems not the setup time....' is not very convincing....you've got a timing problem. Check your constraints, validate that they are correct and redo your timing analysis....that's my suggestion. KJArticle: 110942
I was right 7 years ago, and it showed then :-) Unfortunately, not everything got better during the past 6 years, but it got much (much!) more complicated. One might be nostalgic for the good old simple days, but then who wants to be without the Virtex and Spartan features and their software? But we do try improve the writing, we are just not perfect... Peter On Oct 25, 1:32 pm, "Mark van Wyk" <wtmale...@charter.net> wrote: > Peter Alfke wrote: > > ...Through the XC3000 and XC4000 generations, I put together > > every databook, from deciding the format and pagination to writing much > > of the text, to negotiating the detailed descriptions and even the > > parameter values. It was pretty much a one-man show. But the parts were > > simple... > Then Xilinx got bigger and various people had to share the "fun"....>>>I met you in 1999, Peter. > > I won't say where, lest I reveal my identity. > > You bragged about how Xilinx "..doesn't have technical writers. Our > engineers do our writing...>>> > > Quite frankly, sir, it shows.Article: 110943
what about using dvi input or output straightway? are there peripheral boards that can support this with a decoder like TI TFP 401A? Antti wrote: > John Adair schrieb: > > > But you can digitise it. > > > > NOPS, ASFAIK > you cant use ADV7202 to digitize VGA input signals > I have studied the subject. > > the only obtainable chip that can digitize VGA inputs is AL875 from > averlogic, and it requires external genlock chip, the datasheet says it > has internal PLL but that doesnt work actually > > > AnttiArticle: 110944
I have to make a quick fix to get OPB_UARTLITE fifo larger seems like simple thing, just replace the fifo, but xilinx coregen is not able to create a FIFO with first word fall-through so there latency on read and data from uart seems like delayed. the FIFO has to use BRAM, I was hoping that coregen is easy way but it doesnt look like. sure its not so complicated to write it from scratch but its really boring thing todo, there should be some ready solutions also? target device is S3e so I cant use the V4-V5 FIFO16 that has first word fall-through option AnttiArticle: 110945
Subhasri krishnan schrieb: > what about using dvi input or output straightway? are there peripheral > boards that can support this with a decoder like TI TFP 401A? > surprise surprise - DVI input is simpler than VGA input! there are some boards with DVI input available but not very cheap Hitech tech global has some listed for sure AnttiArticle: 110946
Dave Pollum wrote: > Antti wrote: > >>Dave Pollum schrieb: >> >> >>>Antti wrote: >>> >>>>I had cold recently too. >>>>But I am serious about designing and soft-core that uses 0 slices, 0 >>>>luts and 0 FF's :) >>>> >>> >>>And this design has no inputs, outputs, or clocks, either? >>>-Dave >> >>Why? >> >>it is a clocked desing with lots of inputs and outputs, >>no problems with them at all. >> >>it is really doable and fun thing to design. >> >>Antti > > > Hmmm....I wasn't sure if you were joking when you said "0 slices, 0 > luts and 0 FF's". I assumed that there was nothing left. I'm guessing > that I/O buffers, clock logic, and interconnect circuitry would be left > (I'm faimiliar with CPLDs, but I'm still learning about FPGAs). > -Dave Pollum > There are still memories and DSP48's if this is V4, or MULTs if many other families. You can make a microcoded state machine with just a BRAM.Article: 110947
Thanks for the inputs so far! Here's the code that's giving me greif:
architecture inside of stepmachine is
type pulsestate is (IDLE, PAUSE, OUT1, OUT2, OUT3);
signal currentstate, nextstate : pulsestate;
signal stretched : std_logic;
begin
process(CLOCK, RESET)
begin
if(RESET = '1') then
currentstate <= IDLE;
elsif(CLOCK'event and CLOCK = '1') then
currentstate <= nextstate;
end if;
end process;
process(currentstate, pulse)
begin
case currentstate is
when IDLE =>
stretched <= '0';
if (pulse = '1') then
nextstate <= PAUSE;
end if;
when PAUSE =>
stretched <= '0';
nextstate <= OUT1;
when OUT1 =>
stretched <= '1';
nextstate <= OUT2;
when OUT2 =>
stretched <= '1';
nextstate <= OUT3;
when OUT3 =>
stretched <= '1';
nextstate <= IDLE;
when others =>
stretched <= '0';
nextstate <= IDLE;
end case;
end process;
Article: 110948Xntti, Mr Xlfke, > While I am playing Altera support ;-) You've got a definite knack for it - maybe you should apply for a job in Altera apps - I think they would be most happy to receive you ;-) > Since there inevitably will be either 1 or 2 (never more) rising clock > edges during the pulse, just put a 2-input AND gate in front of the > D-input, and feed it with the pulse, and on its other input with the > inverted Q. > That means, once set, the flip-flop will inevitably be reset on the > next clock edge. Well, what I've written pretty much does this (once you've added the "else snagged <= '0';" in the appropriate spot), except that it's one FF level deeper in order to really really really get around metastability, setup&hold violations etc. FF2 is the value of FF3's D input and FF3 is, well, FF3's Q output. This should result in an equation saying something like snagged.D = FF2 & !FF3; snagged.CLK = CLK; or so. Best regards, BenArticle: 110949
David Ashley wrote: > gen_vlsi wrote: >> Hi, >> >> Can anyone suggest a good stream cipher algorithm for hardware >> implementation. >> > > I'd think AES would be a good choice. > But AES is a block cipher, not a stream cipher. Yes, it can be used in a stream mode, but something else might be better. Questions to the OP: What level of security do you need (ie how well resourced & patient is your adversary)? How much hardware resources can you devote to this function? How fast must it run?
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