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in an EDK project, is it possible (as with ISE) to verify vhdl syntax of one file, before a long long make that abort complaining that syntax of a user_logic.vhdl is missing some ; or ' ... batch compilation would be a mustArticle: 110201
Hi, Virtex-4 has many new things, one of them is access to CCLK as output after configuration. CCLK control is required to readback data from XCF devices, this approuch is described in Xilinx Application note XAPP482. Until today I did live in believe that this was the reason why startup primitive was modified in Virtex-4, but today I was about to check the pinout for XCF data read able design, and uuuuups - CCLK access is added in Virtex-4 but at the same time input access to DIN has been removed!? Or at least I cant see how to read the DIN pin from FPGA fabric. So if for Spartan-3 the XAPP482 solution suggested a FPGA I/O pin to be routed parallel to CCLK, then well this wire is not required in Virtex-4, but now we need another FPGA I/O to be routed to DIN because DIN is no longer accessible? I cant belive this to be true ! But I also fail to see any other solution for XCF data read with Virtex-4. Of course a solution would be using Virtex-5 where the DIN is again made accessible with the modified again STARTUP primitive. I am too glad that I did not trust me belives that the CCLK fix in the Virtex-4 fixed the additional wiring requirement as per XAPP482 and checked the design before submitting to PCB fabrication. I wish Xilinx would update XAPP482 with wiring diagram for all families. The DIN no access thing was really an almost unbelivable surprise for me :( AnttiArticle: 110202
rpons...@gmail.com schrieb: > in an EDK project, is it possible (as with ISE) to verify vhdl syntax > of one file, before a long long make that abort complaining that syntax > of a user_logic.vhdl is missing some ; or ' ... > > batch compilation would be a must you can setup and ISE project or batch file for this there is IMHO no other solution at the moment AnttiArticle: 110203
Torben =C6gidius Mogensen schrieb: > "shidan" <shidan@gmail.com> writes: > > > Are there any functional languages that can be compiled to hardware at > > the same or greater level of abstraction than languages like Mitrion-C > > and Handel-C. Is it all research or is there anything that is practical? > > You could take a look at Lava (http://www.cs.chalmers.se/~koen/Lava/), > which is a hardware description language based on Haskell. > > Torben Lava was purchased buy Xilinx (and killed later). Or is there still a way to get to the Lava downloads? AnttiArticle: 110204
colin wrote: > Austin > > I have just pulled up my copy of IEEE1149.1 to check my terminology > > The proper name for a scan cell is "boundary scan register cell" and > this is almost allways shortened to scan cell. > Your CPLDs have them at every IO pin (and also some which drive > programming). They are what is shifted out on TDO if your TAP > controller (which is what can be placed wherever is convenient) has > been placed into the correct state. > If the input to the scan cell is before the VREF comparator then > clearly I can only do CMOS levels, if it is after the VREF comparator > then hopefully I can boundary scan with sstl. A better question might be to ask if the cell IO config fuses apply to/during the boundary scan - and also specify the CPLD device exactly, as Antii's reply suggests the answer depends on family.. -jgArticle: 110205
Jim I'm using a coolrunner II (which I said in my first email). I think they are the only CPLDs that support SSTL but if anyone knows of another familly then I'd love to take a look. I'm fairly certain that the IO config isn't removed during boundary scan because I can read the functional state of pins using JTAG and so can chipscope for FPGAs. Colin Jim Granville wrote: > colin wrote: > > Austin > > > > I have just pulled up my copy of IEEE1149.1 to check my terminology > > > > The proper name for a scan cell is "boundary scan register cell" and > > this is almost allways shortened to scan cell. > > Your CPLDs have them at every IO pin (and also some which drive > > programming). They are what is shifted out on TDO if your TAP > > controller (which is what can be placed wherever is convenient) has > > been placed into the correct state. > > If the input to the scan cell is before the VREF comparator then > > clearly I can only do CMOS levels, if it is after the VREF comparator > > then hopefully I can boundary scan with sstl. > > A better question might be to ask if the cell IO config fuses apply > to/during the boundary scan - and also specify the CPLD device exactly, > as Antii's reply suggests the answer depends on family.. > > -jgArticle: 110206
Hi
> Virtex-4 has many new things, one of them is access to CCLK as output
> after configuration. CCLK control is required to readback data from XCF
> devices, this approuch is described in Xilinx Application note XAPP482.
> Until today I did live in believe that this was the reason why startup
> primitive was modified in Virtex-4, but today I was about to check the
> pinout for XCF data read able design, and uuuuups - CCLK access is
> added in Virtex-4 but at the same time input access to DIN has been
> removed!? Or at least I cant see how to read the DIN pin from FPGA
> fabric. So if for Spartan-3 the XAPP482 solution suggested a FPGA I/O
> pin to be routed parallel to CCLK, then well this wire is not required
> in Virtex-4, but now we need another FPGA I/O to be routed to DIN
> because DIN is no longer accessible?
>
> I cant belive this to be true ! But I also fail to see any other
> solution for XCF data read with Virtex-4. Of course a solution would be
> using Virtex-5 where the DIN is again made accessible with the modified
> again STARTUP primitive.
>
> I am too glad that I did not trust me belives that the CCLK fix in the
> Virtex-4 fixed the additional wiring requirement as per XAPP482 and
> checked the design before submitting to PCB fabrication.
>
> I wish Xilinx would update XAPP482 with wiring diagram for all
> families. The DIN no access thing was really an almost unbelivable
> surprise for me :(
Isn't this what the USE_ACCESS_VIRTEX4 is for ?
Sylvain
Article: 110207> Isn't this what the USE_ACCESS_VIRTEX4 is for ? sorry, it's USR_ACCESS_VIRTEX4 (typo)Article: 110208
avionion@gmail.com wrote: > Hi Antti > i am unable to get any download from lattice website and get the > following message: > "The file you have attempted to retrieve is not available at this time. > > We apologize for the inconvenience. > > If you continue to experience this difficulty, please contact the > Webmaster" > i have an account with lattice website as well. i am unable to download > any zip or exe file but pdf files open correctly. anyone else facing > this problem? any solution to it? The file you download is a tar.bz2, not zip or exe. You need to extract it with: tar xjf src.tar.bz2 Cheers, JonArticle: 110209
Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > > Isn't this what the USE_ACCESS_VIRTEX4 is for ? > > sorry, it's > USR_ACCESS_VIRTEX4 > (typo) No. USR_ACCESS is nice thing but has nothing todo with missing access to DIN pin on V-4 AnttiArticle: 110210
Antti schrieb: > Sylvain Munaut <SomeOne@SomeDomain.com> schrieb: > > > > Isn't this what the USE_ACCESS_VIRTEX4 is for ? > > > > sorry, it's > > USR_ACCESS_VIRTEX4 > > (typo) > > No. > USR_ACCESS is nice thing but has nothing todo with missing access to > DIN pin on V-4 > > Antti Hm after thininking - well USR_ACCESS doesnt allow direct access to the DIN, but if the configuration memory has appended a specially formatted bitstream block with USR ACCESS commands in it, then seeking the memory to correct position and toggling the CCLK with the help of STARTUP_V4 then the data from configuration memory will appear on USR_ACCESS outputs (And that data comes from DIN). But this indirect way is not useable in the current design. AnttiArticle: 110211
Jon Beniston schrieb: > avionion@gmail.com wrote: > > Hi Antti > > i am unable to get any download from lattice website and get the > > following message: > > "The file you have attempted to retrieve is not available at this time. > > > > We apologize for the inconvenience. > > > > If you continue to experience this difficulty, please contact the > > Webmaster" > > i have an account with lattice website as well. i am unable to download > > any zip or exe file but pdf files open correctly. anyone else facing > > this problem? any solution to it? > > The file you download is a tar.bz2, not zip or exe. You need to extract > it with: > > tar xjf src.tar.bz2 > > Cheers, > Jon Jon, I think the Lattice web has at least sporadic issues with the download there are several people complaining about the downloads not starting, so I dont it the issue of not being able to uncompress .bz2 AnttiArticle: 110212
"backhus" <nix@nirgends.xyz> wrote in message news:egkn36$647$1@news.hs-bremen.de... > shidan schrieb: >> Are there any functional languages that can be compiled to hardware at >> the same or greater level of abstraction than languages like Mitrion-C >> and Handel-C. Is it all research or is there anything that is practical? >> > Hi shidan, > You can use Matlab. > but it is mostly limited to DSP Design and only available for XILINX There is also Catalytic-MCS which feeds straight into Catapult-C (output is RTL so can target any FPGA/ASIC). http://www.catalyticinc.com/product-mcs.html http://www.mentor.com/products/c-based_design/catapult_c_synthesis/index.cfm Hans www.ht-lab.com > FPGAs. Follow this link for more Information: > http://www.xilinx.com/ise/optional_prod/system_generator.htm > > Also there are HDCaml and Confluence. And it seems they are open source. > http://www.confluent.org/ > > have a nice synthesis > EilertArticle: 110213
rponsard@gmail.com wrote: > in an EDK project, is it possible (as with ISE) to verify vhdl syntax > of one file, before a long long make that abort complaining that syntax > of a user_logic.vhdl is missing some ; or ' ... > > batch compilation would be a must > You can place your user designed logic at the top of the .mhs file. In this case it is the first block which is synthesized. FrankArticle: 110214
Hi,
i try to implement the Aurora Example Design to a Virtex-4FX20 device
on the ML405 Evaluation Board from Xilinx. I generate the core with
the "Core Generator" and with the following settings:
Aurora Lanes: 1
Lane width: 2 bytes
Interface: Framing
Duplex-Mode
Native Flow Control: Immediate Mode
User Flow Control
Line Rate: 2.5 Gbps
REF-CLK: 125 MHz
Col. 0 Clock: REF_CLK_1
MGT 105B Position: Y0X0
On the ML405 Board the TX and RX Pins of the MGT 105B are connected
together so i have a external loopback. The Example Design includes a
frame generator and a frame checker.
To run the Aurora Example Design on the Virtex device i edit the
aurora_sample.ucf file to the correct io-pins for the ML405 Board. I
believe thats all i have to do, but it doesn't work. The CHANNEL_UP
signal doesn't assert but there is no error indicated. I don't know
what went wrong.
Can someone help me?????????
Article: 110215
Frank Leischnig wrote
> Do you mean something like:
>
> clk_n <= not clk;
> inst_ramb : RAMB16
> port map (
> clkb => clk_n,
This saves a bit of typing/declaration stuff:
clkb => "not"(clk),
Article: 110216Bitec are pleased to announce the introduction of a series of modules to assist in the development of FPGA + DSP image processing. A 5.2 Megapixel CMOS sensor module provides cost-effective FPGA based real-time high-resolution camera development. It is a low cost daughtercard module for the ALTERA range of FPGA development boards. To compliment the camera, Bitec also offer a DVI input and output module to aid the development of image processing using DVI signals. The products are intended for researchers and developers in the field of Machine vision HDTV development Video phone Remote image sensing Surveillance systems Biometrics Image recognition, filtering and compression Video streaming Stand-alone vision systems Net connected smart camera VoIP projects For more information visit www.bitec.ltd.uk or email info@bitec.ltd.ukArticle: 110217
Hi, I'm exploring partial reconfiguration and I'm trying to find an example design sucessfully implemented using the XUP2VP board with ISE 8.1 with or without Plan Ahead. Designs from the V2P from previous versions of ISE might also be helpful. Please let me know if you have anything you could share. Thanks for you help, DavidArticle: 110218
We might have something that would provide a platform in a few weeks. It is a design that has a lot of other things on it but we might be able to part populate and give you about 88 i/o. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "rickman" <gnuarm@gmail.com> wrote in message news:1158431313.359654.152550@e3g2000cwe.googlegroups.com... >I am looking at using the XPLA3 in a new design and am having trouble > finding an evaluation board. So I started looking around and see that > Xilinx seems to be severely curtailing support of these parts. There > Xilinx no longer offers evaluation boards and I can't find many third > party boards that are still offered. > > On the bright side, when I did a search at Nuhorizons for XCR3128, I > got lots of hits. That alone would not give me confidence, but not > only did I get the XCR3128XL that I need to use, I found the XCR3128 > without the XL which is an even older part. If they are still selling > those parts, I guess I can expect to see the XCR3128XL around for quite > a while. > > The Coolrunner II may be a bit lower power, but the XPLA3 parts are > nearly as low power for our application and only require a single power > voltage. That makes them *more* power efficient. I just wish Xilinx > provided as much support for the XPLA3 parts as they do for the > Coolrunner II. > > Are there any advantages of the Coolrunner II parts that I am missing? > I see they have input hysteresis, but otherwise they seem pretty much > the same as the Coolrunner XPLA3. >Article: 110219
icegray@gmail.com wrote: > Hi everbody, > I wanna implement VGA core at 1024x768x75Hz (15" LCD Monitor) on > Spartan3E starter kit. I have got a few question. I have tried to find > some detialed documents for VGA timing But I can't. There are 640x480 > and 800x600 but there is no document for more resolution and refresh > rate. > - Front porch time, back porch time, and sync pulse times are same at > every resolution (I think it's standard because VGA cards can change > resulation and refresh rate for every value and every monitor??? But > There are different values for 640x480 and 800x600 on the documents???) > - What is hsync and vsync polarisation? What must I do if it's negative > or positive? (invert the sync signal???) Why it is different for > different resolution? > - Any body can give me timing values or recommend any source? ( I can't > a right document on the Vesa web page) > > Thanks Google "video timing calculator"Article: 110220
i would like to know how much time it would take for the spartan 3 fpga to get configured after power onArticle: 110221
ann schrieb: > i would like to know how much time it would take for the spartan 3 fpga > to get configured after power on this is easy to answer: anywhere between 10ms and eternity depending the configuration method. sorry there is no direct answer - it all depends what configuration method and settings are used. AnttiArticle: 110222
Is anyone using linux 2.4 with the plb_temac? And what about EDK 7.1? I am having difficulty finding a linux driver for the plb_temac with 2.4. Rimas, when you say that you used the xilinx_gige driver, will that work for the plb_temac? What about the xparameters*.h defines where they use _XTEMAC_ rather than _XGEMAC_? -cy funkrhythm wrote: > i used the branch of the ppc kernel mentioned here > > http://www.stanford.edu/~malechen/linux_on_fpga.htm > > and copied over the files from the BSP > > then what i did was to edit the Makefile in the drivers/net directory > and change the references from xilinx_enet to xilinx_gige, and select > the regular xilinx driver in the menuconfig > > -rimas > > p.s. if the PVR (processor version register) in your mini-module is > 0x20011430 make sure you apply patches to turn off caching or you will > have problems. more info here: > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=20658&BV_SessionID=@@@@0781667753.1159381366@@@@&BV_EngineID=ccccaddimemlhmicefeceihdffhdfjf.0 > > Benedikt Wildenhain wrote: > > Hello, > > > > On Wed, Sep 13, 2006 at 05:15:24PM -0700, funkrhythm wrote: > > > Benedikt Wildenhain wrote: > > > > Now I want to try sending some IP packets accross the wire, but both > > > > xilnet and lwip insist on using either opb_ethernet or -lite. Are there > > > > any adjusted versions for one of these? > > > don't know about that, i am running linux on the V4FX12 and the EDK > > > generates an ethernet driver (xilinx_gige) that works with the > > > PLB_TEMAC > > How did you compile a matching kernel? I tried to compile a 2.4 kernel > > (I tried several branches, but finally got farest with the branch from > > bee2.eecs.berkeley.edu as it already has integrated the xilinx_gige > > driver) with the BSP for Montavista Linux 3.1. As (menu|x)config doesn't > > offer my board I set CONFIG_MEMEC_2VPX=y, tried to compile it with > > support for uartlite (for the serial console) and xilinx_gige, but > > linking the kernel fails with > >Article: 110223
Sylvain is right. In Virtex-4 the user can control CCLK and the Done pin through the STARTUP block. This feature was added in combination with the USR_ACCESS_VIRTEX4 port. The combination allows for uniform access to data appended to the configuration bitstream in all configuration modes (master/slave serial/selectmap and JTAG). Independent of the configuration mode the data will always show up the exact same way which makes it much easier for a user to use. XAPP719 explains how that feature can be used to configure the PPC caches from a Platform Flash. However, that's only one possible use case. Other use case do not involve the PPC but are for loading persistent user data. - Peter Sylvain Munaut <SomeOne@SomeDomain.com> wrote: > Hi > > >>Virtex-4 has many new things, one of them is access to CCLK as output >>after configuration. CCLK control is required to readback data from XCF >>devices, this approuch is described in Xilinx Application note XAPP482. >>Until today I did live in believe that this was the reason why startup >>primitive was modified in Virtex-4, but today I was about to check the >>pinout for XCF data read able design, and uuuuups - CCLK access is >>added in Virtex-4 but at the same time input access to DIN has been >>removed!? Or at least I cant see how to read the DIN pin from FPGA >>fabric. So if for Spartan-3 the XAPP482 solution suggested a FPGA I/O >>pin to be routed parallel to CCLK, then well this wire is not required >>in Virtex-4, but now we need another FPGA I/O to be routed to DIN >>because DIN is no longer accessible? >> >>I cant belive this to be true ! But I also fail to see any other >>solution for XCF data read with Virtex-4. Of course a solution would be >>using Virtex-5 where the DIN is again made accessible with the modified >>again STARTUP primitive. >> >>I am too glad that I did not trust me belives that the CCLK fix in the >>Virtex-4 fixed the additional wiring requirement as per XAPP482 and >>checked the design before submitting to PCB fabrication. >> >>I wish Xilinx would update XAPP482 with wiring diagram for all >>families. The DIN no access thing was really an almost unbelivable >>surprise for me :( > > > Isn't this what the USE_ACCESS_VIRTEX4 is for ? > > Sylvain >Article: 110224
Hi all, backhus <nix@nirgends.xyz> writes: > shidan schrieb: > > Are there any functional languages that can be compiled to hardware at > > the same or greater level of abstraction than languages like Mitrion-C > > and Handel-C. Is it all research or is there anything that is practical? > > > Hi shidan, > You can use Matlab. > but it is mostly limited to DSP Design and only available for XILINX > FPGAs. Follow this link for more Information: > http://www.xilinx.com/ise/optional_prod/system_generator.htm Technically, this is Simulink - it's *very* low-level to use in most cases - you might as well be writing HDL in most cases - you#'re instatiating adders, registers etc. Also, The Mathworks are doing their own simulink to FPGA product, which I presume would mean vendor independance... I have no idea how abstract this lets you get. AccelDSP on the other hand works directly on M-files and gives you lots of feedback about how many bits you should put in each variable etc. > > Also there are HDCaml and Confluence. And it seems they are open source. > http://www.confluent.org/ > In my experience, these are also pretty low-level - again more like RTL (with generate on steroids). Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
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