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Messages from 97525

Article: 97525
Subject: From ASM to verilog Code
From: prasunp@gmail.com
Date: 23 Feb 2006 09:07:18 -0800
Links: << >>  << T >>  << A >>
Hello:

Does anyone know of any good examples showing the design flow from
algorithm to ASM to coding of control and datapath?


Article: 97526
Subject: Re: Checkpointing PPC Smartmodels in ModelSim 6.0b Issues
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 23 Feb 2006 17:50:15 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 22 Feb 2006 16:30:02 -0800, "Nju Njoroge" <njoroge@stanford.edu>
wrote:

>Hello,
>
>I have set-up checkpointing in ModelSim 6.0b (also using EDK 7.1 SP2).
>ModelSim complains that "two foreign architectures are missing save and
>restore callbacks" when I checkpoint. These "foreign architectures"
>happen to be the PPC swift models. When I restore the checkpoints, the
>waveforms are fully restored. However, I cannot continue the simulation
>because it makes the following complaint:
>
># ** Fatal (SmartModel):
>#    SWIFT protocol:
>#    The first call to lsm_Model_DCEvaluate must occur at time 0.
>#    Time: 424875000 ps
>Instance:/system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst
># ** Fatal: Foreign module requested halt.
>#    Time: 424875 ns  Iteration: 0  Foreign Process:
>/system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst/SmartModel
>File: Foreign
># Fatal error at an unknown location
>#
>
>Anyone encountered this issue?

Not quite; but I am having problems AT time 0ps; with the message 

# ** Fatal (SmartModel):
#    SWIFT protocol:
#    Call to lsm_Model_DCEvaluate must be preceded by a call
#    to lsm_Model_SetSimTimeUnit.

May be related; I don't have any answers yet. (I have had other projects
simulate correctly with SwiftModels; but this is my first of any
complexity, as opposed to EDK projects with one toplevel ISE module)

- Brian


Article: 97527
Subject: Re: altera max 7128s blanking
From: "Noway2" <no_spam_me2@hotmail.com>
Date: 23 Feb 2006 10:18:21 -0800
Links: << >>  << T >>  << A >>
I am not entirely certain what you mean by "blocked ISP.  The ISP port
is set off."

The Max7128 can be programmed (modified) through the JTAG port.  You do
not need to use Altera's programming tool, though I always have for
this purpose.  One person I know made up their own JTAG programmer and
used that.  You do not even need to use their programming software as
long as the tool you are using supports the proper file format.


Article: 97528
Subject: Re: need byteblaster II source code
From: "Noway2" <no_spam_me2@hotmail.com>
Date: 23 Feb 2006 10:21:56 -0800
Links: << >>  << T >>  << A >>
You don't need Altera's source code to create a programmer.

What you do need to do is understand and utilize the timing and
waveform diagrams for the mode of progamming you are attempting to use
(JTAG, Acitve Serial, or Passive Serial).  I believe these diagrams are
available in their configuration manuals.  Once you have this
information, you can write your own source code to implement the proper
logic.


Article: 97529
Subject: How to use a .coe file for rom/ram in system generator
From: "Glenn" <glenn.christian@gmail.com>
Date: 23 Feb 2006 10:23:28 -0800
Links: << >>  << T >>  << A >>
I want to use SysGen to implement a lookup table from a ROM block. I
can include the values for the lut in the 'initial value vector' field
for the block, but when the table will become large I want to load the
values in from an external file. I know that in coregen, for example,
the coefficients can be stored in a .coe file, does anyone know how to
do this in System generator/simulink?

Many thanks,

Glenn.


Article: 97530
Subject: Re: 8051 IP core with JTAG debugger for FPGA?
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 23 Feb 2006 19:39:36 +0100
Links: << >>  << T >>  << A >>
"Pszemol" <Pszemol@PolBox.com> schrieb im Newsbeitrag 
news:dtk2h7.b44.0@poczta.onet.pl...
> Anybody here with experiences with syntetising some 8051 core
> with JTAG debugger in FPGA ? What core can you recommend ?

there is no standard JTAG debug for 8051 core,
quickcores had some 8051 ipcore and jtag debug interface
but quickcores is dead, so you cant obtain that source any more

I bet any other available 8051 does not include jtag debugger
and even it would there is no debug software that supports that
so you would end up writing the debugger and jtag unit yourself
anyway

easiest is to take some 8051 core and just connect chipscope
ILA's onto the bussses, that sufficent for many cases

Antti 



Article: 97531
Subject: Re: News from Embedded World in Nurnber
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 24 Feb 2006 08:10:23 +1300
Links: << >>  << T >>  << A >>
Antti Lukats wrote:

>>SiLabs
>>======
>>5) CP2201 Evalution Kit, no info ??? what is it?
> 
> 
> CP2201 is Ethernet MAC+PHY, packaged in QFN28, TQFP32
> 2 different parallel interfaces, will be officially launched on March 6th.

This is now released, and on their web site.
Interesting device, 5mm package, with a small amount (8K) of flash.
Has (slowish) parallel bus, with Intel MUX'd option that opens into
256 registers, and the FIFOS/SRAM/FLASH are then accessed off that,
with AutoINC modes on the streaming access.

Missing is a SPI port option - would have been a low cost option ?
-jg


Article: 97532
Subject: Re: altera max 7128s blanking
From: djanisz@et.put.poznan.pl
Date: 23 Feb 2006 11:11:54 -0800
Links: << >>  << T >>  << A >>
If you use Altera parallel programmer (APU), yo can use ISP pins like
normal i/o pins. In this case you treat 7128S as MAX without JTAG (7128
without S).

For other MAXs with S sign and Cyclone I use Quartus II with Byte
Blaster II.
When I connect "blocked ISP" MAXs to BB and try to write code (sof), I
get the answer: ''Unable to scan device chain''.

Noway2 napisal(a):
> I am not entirely certain what you mean by "blocked ISP.  The ISP port
> is set off."
>
> The Max7128 can be programmed (modified) through the JTAG port.  You do
> not need to use Altera's programming tool, though I always have for
> this purpose.  One person I know made up their own JTAG programmer and
> used that.  You do not even need to use their programming software as
> long as the tool you are using supports the proper file format.


Article: 97533
Subject: using evaluated ip core with edk 7.1 i
From: "chhavi" <akki_ani1@yahoo.com>
Date: Thu, 23 Feb 2006 13:14:04 -0600
Links: << >>  << T >>  << A >>
Hi All...
i'm quite new to EDK, I want to use the evaluated version of HDLC IP Core
with spartan 3 kit..can anyone suggest me how do i do that...

i'm able to add the obp_hdlc by using add core..but how do i decide the
ports and parameters...
also i hav got the c-code from xilinxipprocessor/drivers...but when i add
this c-code as an application, i'm not able to run it...

Moreover how do i interface with IPIF, using opb...
any kind of help is appreciated..

thanx in advance..

Chhavi




Article: 97534
Subject: Re: 8051 IP core with JTAG debugger for FPGA?
From: "Robert F. Jarnot" <jarnot@mls.jpl.nasa.gov>
Date: Thu, 23 Feb 2006 11:23:11 -0800
Links: << >>  << T >>  << A >>
quickcores has become SiliconLaude -- www.siliconlaude.com -- and 
interesting 8051 cores with real-time JTAG debug are available.

Antti Lukats wrote:
> "Pszemol" <Pszemol@PolBox.com> schrieb im Newsbeitrag 
> news:dtk2h7.b44.0@poczta.onet.pl...
> 
>>Anybody here with experiences with syntetising some 8051 core
>>with JTAG debugger in FPGA ? What core can you recommend ?
> 
> 
> there is no standard JTAG debug for 8051 core,
> quickcores had some 8051 ipcore and jtag debug interface
> but quickcores is dead, so you cant obtain that source any more
> 
> I bet any other available 8051 does not include jtag debugger
> and even it would there is no debug software that supports that
> so you would end up writing the debugger and jtag unit yourself
> anyway
> 
> easiest is to take some 8051 core and just connect chipscope
> ILA's onto the bussses, that sufficent for many cases
> 
> Antti 
> 
> 

Article: 97535
Subject: Re: 8051 IP core with JTAG debugger for FPGA?
From: "Pszemol" <Pszemol@PolBox.com>
Date: Thu, 23 Feb 2006 13:24:48 -0600
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@openchip.org> wrote in message news:dtkvl4$ent$1@online.de...
> "Pszemol" <Pszemol@PolBox.com> schrieb im Newsbeitrag 
> news:dtk2h7.b44.0@poczta.onet.pl...
>> Anybody here with experiences with syntetising some 8051 core
>> with JTAG debugger in FPGA ? What core can you recommend ?
> 
> there is no standard JTAG debug for 8051 core,
> quickcores had some 8051 ipcore and jtag debug interface
> but quickcores is dead, so you cant obtain that source any more
> 
> I bet any other available 8051 does not include jtag debugger
> and even it would there is no debug software that supports that
> so you would end up writing the debugger and jtag unit yourself
> anyway

There are companies like Cast/Evatronix or Digital Core Design
who make 8051 with JTAG supported by Keil tools but their core
is bloody expensive... the prices go into range of over 25000
USD if you want to use core in more than one project...
 
> easiest is to take some 8051 core and just connect chipscope
> ILA's onto the bussses, that sufficent for many cases

I was talking about source-level debugging like it is supported by
some silicon manufacturers like Silicon Labs CYGNAL C80F330 Cpu.

Article: 97536
Subject: Variables in VHDL and simulation
From: Fabio Rodrigues de la Rocha <frr@uiuc.edu>
Date: Thu, 23 Feb 2006 13:27:23 -0600
Links: << >>  << T >>  << A >>
  Hello,

  I have two some basic questions about the use of variables inside 
processes in VHDL and about the processes execution.

   I would like to know if the variables will keep the last value each 
time a process is executed. During the simulation this is the normal 
behavior, however, I would like to know if the same will happen inside 
the FPGA device. I have read contradictory opinions about this topic on 
the Internet..

   Also, I would like to confirm if when the FPGA starts all my 
processes will execute once and then each time an event occurs on any 
signal in their sensitivity list.

   Thank you very much,
        Fabio


Article: 97537
Subject: Re: OpenRisc 1200 on Spartan 3 - problems with stability and enabling
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Thu, 23 Feb 2006 19:42:24 +0000
Links: << >>  << T >>  << A >>
Thomas,

please try to add some constraints, something like 50 Mhz on your clk, 
to give a good reason to P&R to improve the placement, and to see is 
something has  changed in the erratic behaviour of your system, but I 
think is very unlikely to be a tool issue (but not imposible)
anyway if you can get 50Mhz to place & route at least will tell you that 
the timing is not marginal for your design.

Aurash

Thomas Oehme wrote:
> Aurelian,
> 
> thanks for your reply. Of corse i did a look to the timing report. I 
> have no timing constraints specified, but i am using a system clock
> (25 MHz), which is clearly lower than the maximum clock period from the 
> report(36,2 MHz).
> 
> 
> Aurelian Lazarut schrieb:
> 
>>
>> instead of guessing take look to the timing report, do you have any 
>> timing constraints? does it fail on timing?
>> by looking into the timing report you can identify the critical path, 
>> and you'll be able to judge yourself if is a design isssue (to many 
>> levels of logic) or an implementation issue (poor placement)
>>
>> Have fun,
>> Aurash
>>
> 

Article: 97538
Subject: Re: Variables in VHDL and simulation
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 23 Feb 2006 12:04:31 -0800
Links: << >>  << T >>  << A >>
Fabio Rodrigues de la Rocha wrote:

>   I would like to know if the variables will keep the last value each 
> time a process is executed.

Yes for variables declared in a process.
No  for variables declared in a procedure.

> During the simulation this is the normal 
> behavior, however, I would like to know if the same will happen inside 
> the FPGA device.

Yes. For example, see the waveforms here:
http://home.comcast.net/~mike_treseler/

>   Also, I would like to confirm if when the FPGA starts all my processes 
> will execute once and then each time an event occurs on any signal in 
> their sensitivity list.

Yes, in the sense that the synthesis
netlist simulates the same as the process model.
FPGAs contain gates and flops, not processes.

            -- Mike Treseler

Article: 97539
Subject: Re: fix: Xilinx USB Platform Cable on linux 2.6
From: "Stefan" <google.com@bugs.nl>
Date: 23 Feb 2006 12:06:33 -0800
Links: << >>  << T >>  << A >>
Current work around, that actually works:
1. Turn on XUP board.
2. Plug in to USB
3. Wait 10 seconds
4. Unplug and reconnect USB

And it should work.


Article: 97540
Subject: Re: How to make Customized IP which connected with Microblaze through
From: Ivan <gmivan@terra.es>
Date: Thu, 23 Feb 2006 20:09:20 GMT
Links: << >>  << T >>  << A >>
fpga wrote:
> Hello, Ivan:

Hi,

> In your case, how do you deal with the contension when MB and the
> Coprocessor to the BRAM?

I used one "BRAM memory" to write data from MB (PORT A) to coprocessor 
(PORT B) and another to write data from the coprocessor (PORT A) to MB 
(PORT B).

> And I don't understand why do you use FSL interface to connect the BRAM
> but not OPB?

If you need to share data from BRAM, you can use the OPB bus (as you 
propose). However, FSL is faster than OPB, and if you only need to share 
data between the MB and the coprocessor, this solution is more 
efficient. Of course, you need to develop the "FSL-BRAM interfaces" and 
the "BRAM-Coprocessor interfaces".

Each approach is correct, it depends of your performance/operation 
requirements.

> Thank you very much for your help.
> I want to build a system as the following. So the OPB arbitrator can
> deal with the contension when both MB and Coprocessor access the same
> address in BRAM at same time.
> MB(M1)<--->FSL Interface<--->Coprocessor(M2)
> |                                          |
> |                                          |
> |---OPB(with arbitrator)-----------|----------------->BRAM
> 

Regards,

Ivan

Article: 97541
Subject: Re: 8051 IP core with JTAG debugger for FPGA?
From: "Pszemol" <Pszemol@PolBox.com>
Date: Thu, 23 Feb 2006 14:36:34 -0600
Links: << >>  << T >>  << A >>
"Robert F. Jarnot" <jarnot@mls.jpl.nasa.gov> wrote in message news:dtl22v$73q$1@nntp1.jpl.nasa.gov...
> quickcores has become SiliconLaude -- www.siliconlaude.com -- and 
> interesting 8051 cores with real-time JTAG debug are available.

I have just visited their website and could not find IP cores available.
Instead they offer radiation-hardened silicon...
I am looking for an IP core to be put into a generic FPGA device.

Article: 97542
Subject: Re: Is FPGA code called gateware?
From: fpga_toys@yahoo.com
Date: 23 Feb 2006 12:39:58 -0800
Links: << >>  << T >>  << A >>

Nial Stewart wrote:
> > I think what is suprising to some, is that low level software design is long gone,
> No-one ever programs in assembly language any more then?

When I started doing systems programming in the late 1960's, everything
core system important was written in assembly language on big IRON
IBM's - 1401's, 1410's, 360's, with applications in RPG, COBOL, and
Fortran. Pretty much was the same when I started programing
minicomputers, DG's, DEC's, and Varian's, except some flavor of Basic
was the applications language of choice.

99% of systems code - operating system, utilities, compilers, linkers,
assemblers, ... etc was assembly language.

I suspect that number is less than a very small fraction of a percent
today, that is new designs.

> >  and low level hardware design is soon to be long gone for all the
> > same reasons of labor cost vs. hardware cost.
> Where price, performance and power consumption don't matter a higher
> level language might become more prevalent.

The power argument is moot, as the difference between power for a good
C coder and a good asm coder, is probably less than a fraction of a
percent.  Ditto for performance. The only case I can think of, is using
the wrong compiler for the job, such as using an ANSI 32bit compiler on
a micro that is native 8 or 16 bits, rather than downsizing to a subset
compiler which was designed to target that architecture. And there are
a lot of really good subset 8/16 bit compilers for micros,
and it only takes a man week or two to adapt SmallC/TinyC derivatives
to a new architecture.

Cost on the other hand, I believe is strongly in favor of using C or
some other low level HLL instead of assembly. When the burdened cost of
good software engineers is roughly $200-250K/yr and the productivity
factor between asm and HLL's is better than a factor of 3-10 over the
lifecycle of the product, it's nearly impossible to make up the
difference in volume.

Usinging junior labor that chooses the wrong tools and botches the
design is a management problem. There are plenty of good HLL coders
that can do low level software fit to hardware, and get it right.  And
it only takes a good person a few weeks to train an experienced coder
how to do it when experienced low level guys are in high demand.

> I think we'll always
> need to be able to get down to a lower level hardware description
> to get the best out of the latest devices, stretch the performance
> of devices or squeeze what needs to be done into a smaller device.

Yep ... but coding C other other systems class HLL line for line as
asm, the fraction of a percent gained by coding more than a few lines
of asm is quickly lost in time to market, labor cost, and ability to
maintain the product long term, including porting to a different mirco
to chase the low cost components over time.

> I also wonder if price/performance/power consumption will become much
> less important in the future, as it has with software. These days
> you can assume application software will be run on a 'standard'
> sufficiently powerful PC. It won't be the case that at the start of
> every hardware project that you can assume you have a multi million
> gate FPGA (or whatever) at your disposal.

Today, the price difference between low end FPGA boards and million
gate boards is getting pretty small, with megagate FPGAs in high
volume. Five, or even two years ago, was pretty different.

The real issue is that FPGA's with CPU's and softcore CPU's allow you
to implement the bulk of the software design on a traditional
sequential architecture where performance is acceptable, and push the
most performance sensitive part of the design down to using raw logic.

The Google description for this group is: Field Programmable Gate Array
based computing systems, under Computer Architecture FPGA.  And, after
a few years, I think we are finally getting there .... FPGA based
coputing instead of CPU based computing.

The days of FPGA's being only for hardware design are slipping away.
While this group has been dominated by hardware designers using FPGA's
for hardware designs, I suspect that we will see more and more
engineers of all kinds here doing computing on FPGA's, at all levels.


Article: 97543
Subject: Raggedstone1 - New Worldwide postage
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Thu, 23 Feb 2006 21:28:37 -0000
Links: << >>  << T >>  << A >>
The commonist question we have about Raggedstone1 is "have you got cheaper
postage". So we have done something about it. Our US courier rate (normally
next day) has dropped today to GBP 20 (US$ 36 approx). More interesting
possibly for you all is the worldwide rate GBP10 (E15, US$18) low cost 
carriage rate we can
now offer. This is normally a within 7 days service and  but better than 
that in
most cases. We are also clarifying duties and taxes and some more on that 
now on
the Raggedstone1 webpage. And not to forget our local customers UK carriage
is now 7.05 inc VAT for usually next day delivery.

We will be looking to extend these rates to our other products as well in
the coming weeks.

John Adair
Enterpoint Ltd. - Home of Raggedstone1 - The US$90 Spartan-3 Board.
http://www.enterpoint.co.uk




Article: 97544
Subject: Re: Combinatorial Division?
From: Eric Smith <eric@brouhaha.com>
Date: 23 Feb 2006 13:32:53 -0800
Links: << >>  << T >>  << A >>
logjam wrote:
> Now on to my question.  Is there a simple combinatorial design for
> division?

No that I've ever heard of.  If there was, everyone would be using it.

All of the conventional division algorithms (hardware or software) are
sequential, producing one or more bits of result per cycle.  For one bit
per cycle, a simple shift-and-subtract method is easy.  Beyond that,
typically a small ROM is involved.

Some high-speed dividers work by instead multiplying by the reciprocal,
presumbaly because a high-speed reciprocal unit is a either easier to
build or faster than a high-speed divider.  But it still only gets you
a few bits of your result every cycle.

There are a lot of books on computer arithmetic, and a lot of published
papers.

Article: 97545
Subject: Re: 8051 IP core with JTAG debugger for FPGA?
From: "Robert F. Jarnot" <jarnot@mls.jpl.nasa.gov>
Date: Thu, 23 Feb 2006 13:33:10 -0800
Links: << >>  << T >>  << A >>
Pszemol wrote:
> "Robert F. Jarnot" <jarnot@mls.jpl.nasa.gov> wrote in message 
> news:dtl22v$73q$1@nntp1.jpl.nasa.gov...
> 
>> quickcores has become SiliconLaude -- www.siliconlaude.com -- and 
>> interesting 8051 cores with real-time JTAG debug are available.
> 
> 
> I have just visited their website and could not find IP cores available.
> Instead they offer radiation-hardened silicon...
> I am looking for an IP core to be put into a generic FPGA device.

I suggest that you send them an e-mail.  The radiation-hardened devices 
are implementations of the quickcores IP in radiation-hardeneded FPGAs, 
the only signficant changes being that the external memory interfaces 
have been modified to operate with radiation-hardened magnetic RAM.  I 
have found them to be helpful in my interactions with them in the past.

Article: 97546
Subject: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
From: "fpga" <hy34@njit.edu>
Date: 23 Feb 2006 13:51:22 -0800
Links: << >>  << T >>  << A >>
Thanks a lot.


Article: 97547
Subject: Re: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
From: "fpga" <hy34@njit.edu>
Date: 23 Feb 2006 13:54:59 -0800
Links: << >>  << T >>  << A >>
Thanks.


Article: 97548
Subject: Re: 8051 IP core with JTAG debugger for FPGA?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 24 Feb 2006 10:55:32 +1300
Links: << >>  << T >>  << A >>
Robert F. Jarnot wrote:
> quickcores has become SiliconLaude -- www.siliconlaude.com -- and 
> interesting 8051 cores with real-time JTAG debug are available.

I wondered where thay had gone...

Quickcore had some nice examples, and seemed to offer a Multi-core 
80C51, into generic FPGAs, and working on Std EVAL boards.

Does anyone know what's happened to that side of their operation ?

-jg



Article: 97549
Subject: Re: Input stage for VHF frequency counter in an FPGA?
From: LenAnderson@ieee.org
Date: 23 Feb 2006 14:54:43 -0800
Links: << >>  << T >>  << A >>
From: cs_posting@hotmail.com on Wed, Feb 22 2006 7:01 pm

>The other day I found myself needing a short gate time ~200 mhz
>frequency counter for an automated test, and since I had an FPGA board
>on hand I whipped one up quickly.  Getting it reading and reporting to
>my computer was the easy part.
>
>Ah, the input stage....
>
>I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p
>or a little more if it's high-Z.  The output of the device under test
>has a transformer and then a series cap to create an unbalanced output.

                   <snip>

   If you want some good results, use a high-speed comparator
   device.  The Maxim MAX9010 family of comparators is fast
   (5 nSec propagation delay) and it works into a TTL load.

   At 1 V p-p you've got the input overdrive to insure fast
   rise and fall times of the output.  Note:  200 MHz (if that
   is really what you wanted to write) has a period of 5 nSec
   so even this very fast comparator is going to be pushed for
   a good output.  On the other hand it is STABLE and won't
   "go into oscillation with no input."

      http://www.maxim-ic.com

   Samples are available.  One in the family is in a SOT23
   package, the rest smaller.


>If ordering things, what would be a good default low supply voltage
>HF/VHF gain component to have on hand?  I seem to recall lots of
>last-millenium ham designs using the MC1350P video IF amp, but what
>would make sense today?

   The MC1350P is second-sourced by Lansdale.  It is still a very
   good differential in/out building block with good AGC control.
   The MC1349P is a pin/function equivalent and can be ordered from
   Dieter Gentzow's PartsAndKits.com at 3 for $3.  Same place is a
   good source of small-quantity toroidal cores.  Both ICs are
   called out with 12 VDC supplies but they will work down to
   9 VDC with little degredation.  Open-collector outputs, constant
   5 KOhm || 5 pFd input, AGC control down to 60 db (if needed).

   LenAnderson@ieee.org




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