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fpga_toys@yahoo.com wrote: >IE for >every dollar of revenue, testing costs are maybe a penny (or two). I used to work for a semiconductor company. Test costs were sometimes very significant, as the test equipment was expensive. Some complex logic parts had long test times, and for one part I worked on the test cost was roughly a quarter of the selling price, and roughly half of the total cost. Of course, this was an extreme example, and this was decades ago. I'm sure the business has changed. Still, I'm not convinced that test costs are quite as low as you assume. -- Phil HaysArticle: 98776
I want a board with a few of the largest Spartan3e chips, a little SRAM, and a PCIExpress 8x slot and controller for under $300. Until that happens, FPGAs are not in the consumer market in my opinion. All the current consumer boards lack one necessary feature for general purpose acceleration and coprocessing: datastream bandwidth. Tinkering with gates (like one would do with current Digilent starter kits) should not be considered a consumer product; that is in the hobbiest arena. I've worked with the FPGAs in the military some. They use it mostly for image de/compression and de/encryption -- the obvious uses for them. Bandwidth is a huge concern on every FPGA application I've ever worked with, especially with the military. I just wish that thinking would propagate down to the consumer level. Somehow the graphics card companies seem to have a grip on it, while other general coprocessing hardware seems to have been skipped over lightly.Article: 98777
George, If you would let me know exactly what you need, I may be able to help. Please email me directly so we can establish communications on the issue. Austin George wrote: > Hi, I'm looking for a way to purchase V-4 (more specifically V4FX20 and V4FX40) at very low quantities (4-5 devices). It is for research and educational reasons, still the XUP(Xilinx University Program) does not offer devices. Does anyone know where I could buy from in such quantities? > > Thank you, GeorgeArticle: 98778
Nick, Yes, and no. That is not what we do. We take the customer's bit pattern, and use proprietary software to create a complete set of tests that test to a quality factor that is much better than we can for a generic FPGA, and far better than any ASIC test program can test for. And yes, you figured it out: the yield for EasyPath(tm) is better. AustinArticle: 98779
John, Not true. Test costs are not a red herring. Look at the time spent in the socket of the tester, both at wafer sort, and at packaged parts. Look at the cost of the tester (which is in the millions of $). We are not talking about a second of time here, we are talking about running 'zillionz' (actual numbers are proprietary) of patterns at both wafer sort and more at packaged parts to get the quality factor that our generic FPGA customers demand. Remember each test pattern is a configuration, which on a large part, takes time. The actual running of the pattern is insignificant to the time it takes to load. Compare that with only a handful (again proprietary, but the image is entirely appropriate and accurate) of tests, which actually test to a better quality factor (coverage) for that application because the design is known, and only those resources used are tested. That, and yield are the two factors which contribute to the cost savings to Xilinx that we can pass on to customers in the form of a lower price. It is also the reason why we have no small parts in EasyPath(tm): small parts have far less test time, and they also have extremely good yield even for the generic versions. AustinArticle: 98780
See the First Quarter XCell article "Capturing Data from Gigasample Analog-to-Digital Converters" for an excellent example by Ian King showing how to read a pair of 1.5 Gsps ADCs into directly into an LX15. maxascent wrote: > I am considering trying to interleave two 250MS/s ADCs. Would this be a > good idea? possible? or too much trouble? > > Cheers > > JonArticle: 98781
Hi Friends Friends, i have been struggling for 1.5 months on a problem.Let me explain u a little bit. I am working on FPGA implementation of Dijkstra's Shortest Path Algorithm on XILINX 7.1 ISE.Now I hav implemented the code in verilog.The Number of nodes in my case is 256(IF U REQUIRE MY CODE I WILL SEND IT).The tragedy is that the code is working fine but when i m synthesizing it it is giving the following error which i am unable to resolve. The error is " Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 1869512 kb. Memory problems may require a simple increase in available system memory, or possibly a fix to the software or a special workaround. To troubleshoot or remedy the problem, first: Try increasing your system's RAM. Alternatively, you may try increasing your system's virtual memory or swap space. If this does not fix the problem, please try the following: Search the Answers Database at support.xilinx.com to locate information on this error message. If neither of the above resources produces an available solution, please use Web Support to open a case with Xilinx Technical Support off of support.xilinx.com. As it is likely that this may be an unforeseen problem, please be prepared to submit relevant design files if necessary. ERROR: XST failed" My verilog code consists of following operations: 1)Calulating the adjecancy Matrix and Path Matrix. 2)Recursive Algorithm using Task (Palnitkar says that Task and Function is Synthesizable). Also let me inform u that my code is 100% behavorial. While synthesizing It shows "Enabling Task " for 8 hrs and then shows above error. If u know anything about the above error please tell me as the deadline is approaching fastly for project submission. Looking for ur help Thanx Saroj mail me at:coolsaroj@gmail.comArticle: 98782
Hi all, I am having problems debugging my memory controller. My initial idea is to capture a frame and display the same frame continuously. But I see problems in the pattern captured (some spots with colours that arent expected to be there). When I simulate the controller it works as it is expected. I understand that the timing has to be right and I modified everything so that its alright. The input pattern is a simulated timing generator to generate vga timing (640 x 480 @ 60Hz). I think that the problem lies with an asynchronous fifo used to buffer data at 25Mhz. The controller can take data from here at 100Mhz and write into memory. Can anyone see a potential problem with this? I use an async fifo for output buffering and there is no problem here. Also can i use 2 clocks in the same module? some 'always' loops operating at 1 clock and the others at another clock? Can someone think of a test that I do to figure out the problems? I tried using different lenght fifos, with and without fifo and digging into memory location and can do some minor corrections but I am not able to spot any major mistake. Any help is greatly appreciated. Thanks Subhasri.KArticle: 98783
John C, Automotive is happening (big) right now. Latest (can't say which) luxury car has 10+ Xilinx FPGAs in it. One car. 10+ FPGAs. Replaced all the microcontrollers. Why? Because the microcontrollers can not be maintained for ten years, whereas the car maker can always buy any future version of our FPGA, and put their old VHDL/verilog into it. Maintaining stock for all cars sold for replacement assemblies for ten years was driving the maker broke (pun intended). Consumer is going gangbusters. LCD TV's, plasma panel TV's. Why? Because ASICs are a bad investment. The actual number of TVs sold for each country is small compared to the overall numbers. Each country is just slightly different. The TVs change every six months. So making TVs for Taiwan, China, Japan, Korea, Vietnam, Cambodia, Thailand, etc. etc. is a huge headache. And if the ASIC doesn't work, the risk is enormous. PC's? Already there, but it is small compared to everything else. We are in video display cards (I have one in my home PC, which can drive two displays at once, and the mouse will go from one to the next...). We are in high end accelerator cards, instrumentation cards, etc. Still like to see more business here, and it will happen with PCI express which is just starting to ramp now. Military/Aerospace Huge growth here. Why? Because ASICs are really pretty much dead for this market. Not because of cost (which helps), but because of reprogramability. The "mission" changes, and thus if the entire jet fighter is "soft" or "firm" it can be reprogrammed... And there is the software defined radio retrofit of all military forces for all allies and their partners (read the whole world, pretty much) and the homeland security need to retrofit all public safety (police fire medical) radios to interoperate with the military... Embedded systems Everywhere there is a processor + stuff. A 20 billion $ market, which we are able to contribute to. More than 40% of it is Power PC based. So we play well here, and add a lot of value with our EMACs, APU interface, 405PPC, and thousands of programmable CLBs. 'Extreme' DSP Anytime you can't solve the problem with a DSP processor. Or when you need peripherals for a DSP processor (you then use a FPGA instead). Another 20 billion $ market which we play in the top end of. Cell phone base stations, medical scanners, so on and so forth. Looks like there is growth (for us), and lots of it, in our future. Of course, that is our perspective, which is from where we sit, and what we see happening. Others will have their view. AustinArticle: 98784
Sorry for the trouble. I have solved the problems. I havn't instantiate the DCM correctly. Now the maximum freqency of CLk is 1/3 of CLKx3.Article: 98785
Phil Hays wrote: > Of course, this was an extreme example, and this was decades ago. I'm > sure the business has changed. Still, I'm not convinced that test > costs are quite as low as you assume. >From the 2005 annual report 36.6% of revenues are cost of sales, of about $576M. There are a few direct costs listed in that same report which probably are just under half of that which are fixed costs for buildings, IP, and other payments, dropping the remaining direct costs per dollar under $0.25. Not included are labor costs, or direct wafer cost payments, etc to be taken out of that 25 cents. I strongly suspect from that, testing isn't as much as a penny or two. So, we know from the gross margins of the annual report, that testing isn't 50% or even 25% as you may have experienced in the past. I suspect the big changes over the last couple decades are investments like BIST style testing to facilitate screening without expensive testers driving full test coverage as we saw in the 1980's. Two years ago, the marketing spin was "The Virtex-II EasyPath solution offers a 25% to 80% cost reduction with production quantity deliveries (thousands of units) in as little as 8-10 weeks". That level of discount based on test costs alone doesn't play with the numbers reported by the annual report. Most of that discount has to be single piece to volume discounts, or other incentives - not testing costs.Article: 98786
Austin, you mentioned a patent on Easypath, I went to look for it, but couldn't find anything. Do you know if the patent has been approved and published yet? It normally takes some time to get it out..... On Thu, 16 Mar 2006 08:07:14 -0800, Austin Lesea <austin@xilinx.com> wrote: >Nick, > >Yes, and no. That is not what we do. > >We take the customer's bit pattern, and use proprietary software to >create a complete set of tests that test to a quality factor that is >much better than we can for a generic FPGA, and far better than any ASIC >test program can test for. > >And yes, you figured it out: the yield for EasyPath(tm) is better. > >Austin >Article: 98787
laura_pretty05@yahoo.com.hk wrote: > I mean how can I connect the sensor to the FPGA board, how to connect > the pin on FPGA board? Thanks. (I am not shure, if I understand you right.) Most UP2 Education Boards are shipped with no pins at the FLEX_EXPAN_X connectors. You have to solder some by yourself. RalfArticle: 98788
Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote: > I forgot to add that these links are also in the pinout section (Module > 4) of both the Spartan-3 and Spartan-3E data sheets. If you're not using Spartan 3, you can generate .pkg files using partgen.exe partgen -i -v will generate files for all installed packages (this can be a lot of files). or just type partgen at a command prompt for program usage. The data is columnar but separated by (multiple) spaces rather than commas. With a little editing you can generate csv files from these text files. Hope this helps, GaborArticle: 98789
coolsaroj@gmail.com wrote: > The error is " > Portability:3 - This Xilinx application has run out of memory or has > encountered a memory conflict. Current memory usage is 1869512 kb. ... > While synthesizing It shows "Enabling Task " for 8 hrs and then shows > above error. Try to brake your design into smaller parts. Synthesize every part alone. Try to find the point, where to problem source is located. RalfArticle: 98790
pd.... -snip- >>Automotive I guess is coming, as is aerospace. You could put the two >>together, as control electronics. Both there now. Account for them as you will. We have a Aerospace/Defense/Automotive Division today. > Aerospace posses issues with ionizing radiation. Which is why we offer the QPro series, and have onging research into solving all the problems in these applications. -snip again- > When there's an advantage of reconfiguration ability over static asic > massproduced at low price. A possible app could be builtin reciever for > television, modem etc.. that can be adapted fast to new codecs > post manufacture. Already in them. The sets are programmed just as they are leaving (for country, etc.). AustinArticle: 98791
Consumer items do have the advantage of volume manufacture and recovery of development costs on a few hundred board does tend to make them dearer than that market never mind thge dearer manufacture costs. Wait a long while and maybe and our Raggedstone2 will bring what you want but don't expect it this side of Christmas. It's on the roadmap but not for a long long time yet. Broaddown3 when it releases will have some what you want and probably dearer than you want to pay. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Low Cost Spartan-3 Development Board. http://www.enterpoint.co.uk "Brannon" <brannonking@yahoo.com> wrote in message news:1142524628.903506.159270@v46g2000cwv.googlegroups.com... >I want a board with a few of the largest Spartan3e chips, a little > SRAM, and a PCIExpress 8x slot and controller for under $300. Until > that happens, FPGAs are not in the consumer market in my opinion. All > the current consumer boards lack one necessary feature for general > purpose acceleration and coprocessing: datastream bandwidth. Tinkering > with gates (like one would do with current Digilent starter kits) > should not be considered a consumer product; that is in the hobbiest > arena. > > I've worked with the FPGAs in the military some. They use it mostly for > image de/compression and de/encryption -- the obvious uses for them. > Bandwidth is a huge concern on every FPGA application I've ever worked > with, especially with the military. I just wish that thinking would > propagate down to the consumer level. Somehow the graphics card > companies seem to have a grip on it, while other general coprocessing > hardware seems to have been skipped over lightly. >Article: 98792
John, The annual report includes CPLDs, FPGAs (all sizes), services, and storage. Devil is in the details. AustinArticle: 98793
using tasks and recursion in FPGA sounds seeking for trouble - its never a good idea to use what some HDL "should" be able to support, but only features that are really supported by the tools you are using. try synplify - XST fails to synthesize Lattice ispTracy core where recursion is used. but way better NO RECURSION unless you really know what you are doing (and that the tools support it, and that the result is reasonable)Article: 98794
hello everyone..iam newbie to the world of fpga's..can anyone suggest something frm where i can start my foray in to this field..iam exactly looking to implement a risc processor in the altera board..i need to program this thing in to the board using the quartus software...does anyone of you have any hands on experience on this topic.. And what do you guys suggest is it better to use verilog or vhdl code to implement this..Article: 98795
Hi All, I would like to know when should I use the IEEE 1532 files. I found that "Users will now be able to program chains of ISC PLDs, from multiple vendors using the same third-party software tools and the same Boundary Scan interface. Users will no longer be required to have vendor-specific programming support or knowledge". But if I want to program a device I use the SVF files, so what makes me need the 1532? Where can I find detailed information about the way of use it and the sofware for this? Thanks for your attention.Article: 98796
Austin Lesea wrote: > pd.... > > -snip- > >> Aerospace posses issues with ionizing radiation. > > Which is why we offer the QPro series, and have onging research into > solving all the problems in these applications. > I'm surprised you didn't mention that quite a few FPGAs, including Xilinx FPGAs, have been roaming around the surface of Mars for the past two years. And while a few mechanical parts are starting to wear out, the FPGAs are still going strong.Article: 98797
In message <ifmi1218qkjo36fnvf3mk21p6n2k4mv39m@4ax.com>
John C <brakepiston@yahoo.co.uk> wrote:
> Reading the LSI Strucutred ASIC fiasco thread has made me think.
> People are saying the FPGA revenues are going to grow, so....
>
> Which markets are FPGA heading into?
>
> I mean, at the moment there's Comms, Medical, Military, Consumer.
>
> Where are they going next?
>
> Automotive I guess is coming, as is aerospace. You could put the two
> together, as control electronics.
>
> How about seeing them in a PC?
See http://www.microdigital.info
Altho the company seems to have ceased trading, there are a few of us who
have units.
It uses Spartan xc2s200's, one to implement a northbridge and one as a
memory controller and graphic engine. A xc95144 is used to boot them and
provide memory control.
NOTE this is not a windows machine, but is a RISCOS (http://www.riscos.com)
machine with an ARM based processor.
>
> What are your views on the matter?
--
webmaster@tankstage.co.uk
Iyonix PC
Article: 98798Hello grps, Can you tell me what is the basis for selecting the DDR controller? For example i have a micron DDR SDRAM and i have to see if it compatible with the DDR controller which is within network processor. Wht all parameter should i check? Please let me know that Regards PraveenArticle: 98799
Duane, Yes! Exciting, but not very high volume. 12 XCV1000's. Times 2. Austin Duane Clark wrote: > Austin Lesea wrote: > >> pd.... >> >> -snip- >> >>> Aerospace posses issues with ionizing radiation. >> >> >> Which is why we offer the QPro series, and have onging research into >> solving all the problems in these applications. >> > > I'm surprised you didn't mention that quite a few FPGAs, including > Xilinx FPGAs, have been roaming around the surface of Mars for the past > two years. And while a few mechanical parts are starting to wear out, > the FPGAs are still going strong.
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Compare FPGA features and resources
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