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John, Stop playing the fool. If one memory bit is bad, out of 20 million, then that FPGA can not be used for the general public. But if you don't use that one bit in your patern, then that chip is perfect for you. One bit. That is all we are talking about here. That is EasyPath(tm). One bit. The majority of faults that prevent a FPGA from being perfectly good, are just that, one fault, one bit. One path missing (metal is open). One bit that won't write. One bit that won't read. One LUT bit that can't be set. One IO standard that isn't there. Maybe you should go take a course on semiconductor manufacturing? Go actually learn something? Since we can't educate you, and you are unwilling to listen to us, maybe you should go talk to someone you trust, and will listen to? AustinArticle: 98876
pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: > > Aerospace posses issues with ionizing radiation. Xilinx has their QPRO line which is radiation tolerant for this market. Aerospace was actually one of the earlier adopters of FPGAs for DSP applications. I've built my business around this market and have completed several designs specifically intended for low earth orbit insertion. QPRO is not new, it has been around for close to a decade.Article: 98877
Jim Granville wrote: > Austin Lesea wrote: > > -jg > I suspect the truth is closer to being able to customize the FPGA at the time of application rather than at the time of purchase. That means they can get more commonality, so that the spares inventory is much smaller.Article: 98878
Good day to one and all! Does anyone know of any freeware that essentially dumps out the vhdl code of digital filters? Particurlarly IIR filters. Basically, I imagine it will prompt you for the tap values and filter order and .... You get the idea. -RogerArticle: 98879
fpga_toys@yahoo.com wrote: > on a $100 wafer with 100 parts, Wafer costs for leading edge processes were way over $100 in the 1980's when I was working in the semiconductor manufacturing business. A quick google gets me: http://www.icknowledge.com/economics/WaferCosts2005.html Making leading edge chips is not cheap. -- Phil HaysArticle: 98880
Austin Lesea wrote: > John, > > Stop playing the fool. If Ford decided to dump perfectly good Lincon's at 80% quoting they were saving QC costs for the occasional scratch or miss alighed seat frame, or what ever ... defectives ... we would laugh our heads off and realize that it was a marketing ploy to dump product below market. If they were laughing that they were driving a competitor out of business by that businesss tactic at the same time we would call it dumping, anti competitive, and a lot more ... If any of the Asians were dumping Silicon product in the US with the weak claim some are slightly flawed, the dumping howl wouldn't stop... Choosing NOT to test on dies that have statistically good yields, in order to dump product below Structured ASIC's pricing, and then start this thread howling about driving them out of business? So, if you want to be a Tin Aus ... by calling me a fool and raising this to very personal attacks ... then lets get with it. The foolish part here is gutting competitors with absolute glee, and then getting upset when someone questions that. I don't buy dumping X percent of your statisicly good known chips below market is a wise business decision, any more than I would buy Ford dumping Lincons to drive a competitor out of business by "saving QC costs". That die is expensive, has real value, particularly the percentage of them that are statistically perfect. There are people that will buy hard drives with errors, and map them out ... practically the entire industry. There are people that will buy FPGA's with a few bad bits too ... at significant value, and map them out too. Or test, screen, and bin them as the easy path program, and not use them for certain designs that are affected, or roll a second bit stream to work on a bin selected group with mapped failures (as easypath program suggests). So you want to call me a fool ..... I hope there is someone in your company that has a LOT more sense ....Article: 98881
Phil Hays wrote: > fpga_toys@yahoo.com wrote: > > > on a $100 wafer with 100 parts, > > Wafer costs for leading edge processes were way over $100 in the > 1980's when I was working in the semiconductor manufacturing business. > A quick google gets me: > > http://www.icknowledge.com/economics/WaferCosts2005.html > > Making leading edge chips is not cheap. We all know that ... I choose a nice round number to do math with ... that's all ... The whole point is that perfectly good FPGA's aren't cheap ... and to dump them without testing them at 80% off, is dumping high value product below it's full value.Article: 98882
Hello,Everbody!!! I'm working with the spartan3 starter kit,I want to use the on-board sram for temporary data storage,so I hope to find the simulation model of the sram(ISSI61LV25616-10T) for function and timing simulation .Please! Somebody tell me where I can find the simulation model,or anybody provided me some suggestions about how to verify the timing.Thank you!!!!Article: 98883
Leow Yuan Yeow wrote:
> Hi, I was doing that before but I found that each + that I use generates a
> 32-bit adder under the synthesis report which increases the LUT usage by
> quite a fraction. After that I tried to multiplex them to a addsub component
> and the LUT usage went down from 90+% to 80+% (I'm using the old RC100 board
> with spartan II so I have limited resources :( ).
It may be that the rest of your design precludes resource sharing.
Every time I've needed an adder or subtractor, I write code similar to
what Weng describes.
For example, the following code will create only one adder:
if (add) then
result <= a + b;
else
result <= a - b;
end if;
> I was wondering if there are any other components that I can instantiate for
> comparators as well?
Why instantiate?
-a
Article: 98884austin wrote: > If you buy Froto's uP, they make a new one every year, and you have no > choice but to switch to the new unit, or stock enough of the old units > to serve your entire replacement need. > > So, the car company goes to Froto, and say "Froto: attention! We want > the same uP guaranteed for a long time." > > and Froto says: "huh? did you hear anything? did someone say > something?"..."nope, must have been the wind..." Do you really believe that? Do you really have any evidence to back up this claim? I would imagine that if Ford or GM or Chrysler tells Motorola (or whomever) that they will need however-many-million microcontrollers/microprocessors each year for the next five, six, ten years, Motorola will continue to make them. Why wouldn't they? Guaranteed orders, especially since the parts are often customer-specific. Maybe the imaginary Froto Company tells a major customer, "sorry, we're not interested." Anyways, one would imagine that replacements for existing chips would be upgrades--more memory, more features, faster, whatever--that are code-compatible. Why throw away the investment in software development? -aArticle: 98885
Antti <Antti.Lukats@xilant.com> wrote: > ok, jokes beside I have implemented a SATA OOB circuitry with NO > external circuitry with V2Pro rocketio > it worked with some Silicon image SATA bridge, eg i monitored the link > to come up > eg the in band signalling started and MGT got locked I read somewhere that using another serdes-IC would do the trick with the V2Pro? Or are you saying that creating a fully SATA-compatible datalogger just isn't doable? Another thing is the ability to connect a SATA-device to the Virtex-II Pro for use with linux running on the embedded PowerPC-core. -- ThomasArticle: 98886
I *sincerely* appreciate the well delivered post by JJ and the continuing push for professionalism from others like Mr. Alfke. JJs post expressed well the opinions of the "ignorant, sneezing, bunch of fools" that will have the opportunity to employ you in the future. "Chauhan" <coolsaroj@gmail.com> wrote in message news:1142596822.415346.183540@e56g2000cwe.googlegroups.com... > Jhon has added another dimension to fpga.You once again proved that > Birds of a feather flock together.This is the characteristic to hide > your ignorance and prooving what you know about. Sneezing > unnecessarily is not going to help you man.And as you and your fellow > partners showed that what a big fuss a bunch of fools can make to a > FPGA problem.Forthcoming friends will always remember your contribution > to this post. >Article: 98887
<fpga_toys@yahoo.com> wrote in message news:1142614872.436320.327150@p10g2000cwp.googlegroups.com... <snip> > If they were laughing that they were driving a competitor out of business > by that businesss tactic at the same time we would call it dumping, > anti competitive, and a lot more ... > > If any of the Asians were dumping Silicon product in the US with the > weak claim some are slightly flawed, the dumping howl wouldn't stop... "dumping" is selling something below cost, not taking a lower margin than premium, "perfect" products. <snip> > So, if you want to be a Tin Aus ... by calling me a fool and raising > this to very personal attacks ... then lets get with it. He doesn't have to call you anything - you make it rather obvious. <snip> > I hope there is someone in your company that has a LOT more sense .... ...as I hope you have access to professionals with more sense to help smooth out your rough edges.Article: 98888
John_H wrote: > "dumping" is selling something below cost, not taking a lower margin than > premium, "perfect" products. By their own statements, they do not screen the good parts first, so depending on the wafer yield, a reasonable percentage of those are parts ARE premium, "perfect" products being sold as low as 20% of the normal price.Article: 98889
<fpga_toys@yahoo.com> wrote in message news:1142618945.752008.15170@i40g2000cwc.googlegroups.com... > > John_H wrote: >> "dumping" is selling something below cost, not taking a lower margin than >> premium, "perfect" products. > > By their own statements, they do not screen the good parts first, so > depending on the wafer yield, a reasonable percentage of those are > parts ARE premium, "perfect" products being sold as low as 20% of the > normal price. > Again, selling below MSRP is *not* dumping! Dumping is selling parts below cost. We're talking negative margin here. When xilinx writes a PO for 100k devices _from_the_fab_ at $N per device, it's dumping if they sell that device for less than $N.Article: 98890
John_H wrote: > "dumping" is selling something below cost, not taking a lower margin than > premium, "perfect" products. Do the math ... if the typical product margin is above 60%, and the typical costs of sales is some 36.6% of revenue, then dumping at 80% discount, is recovering 20%, and well below 36.6% the typical cost. When some percentage of those sales are statistically perfect yield parts, that they decided not to screen I'm pretty sure any sane person would agree that perfect parts sold at half normal "cost" is just that. If the yield cleans up to 50-80% good parts, then program is clearly dumping. Now, if the offical word is that they test every part completely, and pull the perfect parts then you would be correct. The whole program would make sense if they were selling known rejects. In fact, there are a number of people that would probably stand in line for parts with a one bit error as Austin says. Bin them into sixteen subquadrants and people would eagerly purchase them in volume avoiding that 1/16th of the chip with par for entire production runs. We've heard a lot of whining about dropping non-profitable support ... how long is a program going to last that ships as many perfect parts as very slightly flawed parts?Article: 98891
John_H wrote: > When xilinx writes a PO for 100k devices _from_the_fab_ at $N per device, > it's dumping if they sell that device for less than $N. if they were selling bare die, then $N would be correct. They are however selling packaged and tested parts, so all standard burdens, labor, buildings, IP, etc apply to the cost -- not just die cost from the fab.Article: 98892
I am quite happy with my flock too, although I fear some regulars have already strayed away due to the trending down. When we are young, we think we know everything esp we know more than our elders. When we are older, we just know better. Anyway google will remember this contribution, not so sure if my memory will!Article: 98893
Peter Alfke wrote: > Isn't that obvious? No, I don't think it was at all obvious that Xilinx would be willing to sell its IP for half price.Article: 98894
<fpga_toys@yahoo.com> wrote in message news:1142619972.463368.89120@i40g2000cwc.googlegroups.com... <snip> > We've heard a lot of whining about dropping non-profitable support ... > how long is a program going to last that ships as many perfect parts as > very slightly flawed parts? When the incremental sales are significant for a small percentage of Xilinx customers, this program should have a long, happy existence. Oh, and your flawless understanding of market dynamics has convinced me that Xilinx is a bad investment. Yeah.Article: 98895
John_H wrote: > When the incremental sales are significant for a small percentage of Xilinx > customers, this program should have a long, happy existence. > > Oh, and your flawless understanding of market dynamics has convinced me that > Xilinx is a bad investment. Yeah. The Emperor's New Clothes ... even without clothes, he's still the Emperor. I assume that last straw of a jab, means that you decided that an 80% discount is actually below cost. Can I take my Devils Advocate hat off now?Article: 98896
fpga_toys@yahoo.com wrote: > We've heard a lot of whining about dropping non-profitable support ... > how long is a program going to last that ships as many perfect parts as > very slightly flawed parts? Conversely, what really happens to the devices not originally allocated to easypath which have single errors. Are they crushed and returned to the sandbox? Or do they get a second chance at proving their worth, on the easypath tester?Article: 98897
Leow Yuan Yeow wrote:
> Does resource sharing also apply for a + sign in different states? It
> appears the synthesizer doesn't like my code then.
If you want to share an adder,
it is best to describe exactly how in your code.
Resource sharing by synthesis requires
duplicated descriptions or a selection
that can be made either by muxing
inputs or outputs, like this:
if op1 then
q_v := A + B;
else
q_v := C + D;
end if;
I might duplicate a register description by mistake and
be happy about a silent band-aid from synthesis.
Or I might prefer just a warning so I can clean up my code.
Then again, I might duplicate a register just to buffer the signal
and prefer that synthesis keeps hands off.
-- Mike Treseler
Article: 98898almost everything is doable. the question is what is reasonable. you could be lucky and get v2pro serdes working with SATA too with some limitations and with huge amount of work. as of using external SATA PHY well that would work, but the problem is that SATA PHY is pretty much not available at all, you are welcome to try find one, but I am 99.99% sure you will not get any. OK, that was situation a year ago, maybe its little easier today. sure using v2pro serders and ppc-linux would realy COOL, too bad it doesnt work out that way :( AnttiArticle: 98899
Andy, The only proof is in the orders, and the shipments, and what I was told. That you, and others do not believe me is just fine. I didn't need your approval to ship the parts. Does anyone honestly think I am making this up? I have no time for fantasies: I have real work to do. The announcement was made (and the part briefly shown at the press conference) for 65 nm. Busy doesn't really describe my shop right now. 'Frantic' is more accurate. A very happy, and pleasing kind of frantic. Austin
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z