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sure they would, but have you tried to purchase them !? AnttiArticle: 98926
Hi All, I was able to get a bunch of Xilinx XC3042 FPGAs from a dealer and am trying to find if there is any support software out there still for the chip. I looked at the current ISE offerings from Xilinx, but none state they support the XC3042. Does anyone know of anything for the XC3042? Thanks, J SilvermanArticle: 98927
Peter Alfke wrote: > Without EasyPath any production device with any known defect (that is > not covered by an errata note) goes into the garbage can. > That has been and will remain our policy, and I assume the policy of > any reputable IC manufacturer. Dodging the question. What happens to devices run through the full (general application) test program, which turn out to have single errors? Are they retested for easy path use? or are they destroyed?Article: 98928
Phil Hays wrote: > It seems to me that testing by loading BIST designs still makes a lot > of sense. Using a BIST design, the RAMs, multipliers, LUTs and > registers can be tested quickly. This is the easy part of testing a > FPGA. There would be little gain in customizing these tests. I agree Phil. The twist is that the customer can not take and use a standard set of tests built for a fully functional part, otherwise it will find and report all the untested errors creating a nightmare for the field techs to sort out false positives. For field testing, the tests really need to live inside the same set of qualified good resources, which means customizing the tests for each qualified easypath design, to stop the test from reporting errors on logic resources not used.Article: 98929
Antti <Antti.Lukats@xilant.com> wrote: > sure they would, but have you tried to purchase them !? I've contacted TaraCom now, at least. -- ThomasArticle: 98930
Austin Lesea wrote: > John, > > How much is Altera paying you? Gee ... I've found that playing Devils Advocate would get me paid .... how much should I be asking?Article: 98931
Austin Lesea wrote: > John, > > How much is Altera paying you? Next time you are in Longmont drop me a note, and take me to lunch :) Maybe some face to face time will allow the petty BS to fade away.Article: 98932
John Williams' "Partial Reconfiguration on Xilinx Devices" email list is another resource: http://www.cs.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ The archive is available here: http://www.itee.uq.edu.au/~listarch/partial-reconfig/ scotto wrote: > > Hello, Does anybody out there actually know how to set up HWICAP in EDK? > Has > anyone ever got this to work? > > If you've ever looked into this, you know there's very little > documentation on how to setup and use HWICAP. Would someone please post a > C file instantiating, initializing, and perhaps even reading/writing a > frame through ICAP? That would be extremely helpful. > > I am but a lowely univerisy student, and as such get zero support from > Xilinx > on these or any other matters. > > Thanks much, --scottArticle: 98933
fpga_toys@yahoo.com wrote: > Austin Lesea wrote: > > How much is Altera paying you? > Next time you are in Longmont drop me a note, and take me to lunch :) > Maybe some face to face time will allow the petty BS to fade away. Be sure and bring a briefcase full (about 4K) of the reject XC4VLX200 parts so I can stay busy building the next version of my home reconfigurable super computer :) That ought to keep me busy and off CAF for several months, if not a year :) It might even give Xilinx some usable marketing collateral when I'm done, and we can talk about buying reject parts for profit afterward too!!Article: 98934
An example design for the ML321 board is automatically generated by Coregen. Another resource is the "Using High Speed Serial MGTs with the Aurora IP" Quickstart targeting the XUPV2P board: http://www.xilinx.com/univ/xupv2p.html Paul billu wrote: > > Hi There, > > I need some help getting started with the aurora core. I'm trying to > implement a simple serial protocol/data transfer between trasceivers in > Rocket IO ML321 board. Can I just use the customized aurora core > (generated by Core generator) to implement the protocol. Or, does the > core have to be integrated with some other existing design for it work. > Alternatively, is a there sample reference design available to > demonstrate a simple link. > > Thx in advance, > billuArticle: 98935
John- > let me inform u that yur english sux in a way that is of ur own making > and that probably reflects on your study abilities too. This is spelled and constructed incorrectly. It should be: let me inform u that ur english sux and proly reflects on ur study abilities 2 If you're going to use the emerging Internet chat / text messaging dielect of English, then you have to get it right. Otherwise younger engineers -- and some very sharp ones too -- will simply have no respect for your post. Only half kidding :-) -JeffArticle: 98936
John, Just wanted to be sure you were not on their pay roll. I have been made a fool of once before thinking I was talking to a potential customer when it was someone who was an actual competing company employee...boy did I feel stupid. AustinArticle: 98937
fpga_toys@yahoo.com wrote: > If Ford decided to dump perfectly good Lincon's at 80% quoting they > were saving QC costs for the occasional scratch or miss alighed seat > frame, or what ever ... defectives ... we would laugh our heads off and > realize that it was a marketing ploy to dump product below market. That's not a good analogy for Easypath. Ford can repair manufacturing defects at relatively low cost, compared to the total cost of the product. Xilinx *might* be able to repair some bad dice by using FIB, but the cost of doing so would significantly exceed the original cost of the die, and although the result might be functional, it could not be guaranteed to have comparable reliability to a normal part. Thus it could not be sold except perhaps as an unqualified engineering sample. Thus there is no motivation to do any sort of repair as part of the production process, but rather to do everything possible to increase the yield of fully functional parts. Still, for a large die, despite their best efforts there will be some parts that are not fully functional, but very nearly so (>99.999%). Unfortunately these cannot be sold as normal FPGA product. With Easypath the customer is not informed of the specific nature of the defect(s) of the parts they receive; the parts might even be 100% functional, but are not guaranteed as such. In fact Xilinx might not even be aware of all of the defects; they have tested the part against vectors that verify that it meets all relevant specifications with regard only to the specific customer configuration bitstream. Finally, they aren't "dumping", which would be selling below cost. They are likely making quite a tidy profit on Easypath, since although the price is lower than for a fully tested FPGA, the cost is also lower. Time on a semiconductor tester is very expensive, thus anything that reduced the test time significantly reduces the total part cost.Article: 98938
"Jeff Brower" <jbrower@signalogic.com> wrote in message news:1142633522.291161.217990@u72g2000cwu.googlegroups.com... <snip> > If you're going to use the emerging Internet chat / text messaging > dielect of English, then you have to get it right. Otherwise younger > engineers -- and some very sharp ones too -- will simply have no > respect for your post. > > Only half kidding :-) > > -Jeff Any idea where to find classes on chatonics in the Pacific Northwest?Article: 98939
fpga_toys@yahoo.com writes: > hmmm just like putting a yellow sticker on $10m of perfectly good > parts, and calling them lemons to justify a sale below cost? Where do you come up with this "below cost" idea? I don't see any evidence that supports it. > It also seems like a perfectly good scam for your production department > to take perfectly good tested parts, and ship them under the easypath > program for a huge kickback. A kickback? From whom? > How can you montor employee fraud with > such a dual labeling program with 80% discounts? Presumably Xilinx employs standard manufacturing traceability procedures. It is not obvious that there is any more potential for employee theft or fraud with Easypath than with their standard products. Why do you care? If there were some unscrupulous employees, presumably Xilinx would find and fix the problem themselves, with support from the authorities as necessary. Why do you have an axe to grind about Easypath?Article: 98940
Antti <Antti.Lukats@xilant.com> wrote: > gosh! just take a buzzer enabled multimeter and sit down for one > evning, there are some wires between the cypressFX2 and coolrunner, > that is it basically. the usb cable does not contain any preprogrammed > firmware (except usb vid/pid,,) so you just duplicate it, then force > impact to perform PLD update and ready you are ! > sure xilinx doesnt document how to do this, but it really isnt that > complicated. I'd be glad if you share your experience ;-) -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 98941
marcobuffa@gmail.com writes: > I've installed ISE 8.1 for linux (32 bit) on a Debian machine with no > pain at all, it works fine. > > Now I'm trying to install the same release on a dual core AMD64 > machine, with debian 64 bit, and all works fine until I need to insert > the serial code of the product, wich is ever refused. Note that I'm > using the _same_ serial I used for the 32bit machine, and our Xilinx > man said that's right. If you're using ISE Foundation (the paid version), your key should work for both 32-bit and 64-bit. For Webpack, only 32-bit is supported. If you have trouble with getting 64-bit installed, as a temporary workaround it is fairly easy to force an installation of the 32-bit version on a 64-bit machine.Article: 98942
Hi I am a student, write a diploma about application of partial reconfiguration. Would not you to give me materials where is the fast-acting with partial reconfiguration and without it compared? Beforehand thankful.Article: 98943
rickman wrote: Now I realize that > Xilinx as a whole is not a lot different than the image you present and > it bothers me. It bothers me enough that I now have a strong > preference for any other FPGA manufacturer. > > I think the fact that no one at Xilinx seems to have a problem with > your posts like this one says a lot about the company. Rickman, Austin is not alone in posting outspoken comments. You are no slouch yourself ! Luckily, Xilinx is not a monolithic dictatorship, and the company trusts its senior employees to post in this newsgroup without censorship and without reprimands. Austin and I give fast response, to the best of our knowledge (which is quite extensive), but we are not always politically correct, and both of us have a temper that can indeed be provoked by certain stupidities repeatedly voiced on this newsgroup. We handle complex and sometimes controversial subjects with engagement and also some humor. We are not the official "Voice of Xilinx". You get that from Marketing and in press releases. I would be amazed if any smart engineer would base his component choice on Austin's typing style. We would, however, appreciate if you base it on the technical information you get in this newsgoup. Peter Alfke, Xilinx ApplicationsArticle: 98944
Eric Smith wrote: > fpga_toys@yahoo.com wrote: > > If Ford decided to dump perfectly good Lincon's at 80% quoting they > > were saving QC costs for the occasional scratch or miss alighed seat > > frame, or what ever ... defectives ... we would laugh our heads off and > > realize that it was a marketing ploy to dump product below market. > > That's not a good analogy for Easypath. Ford can repair manufacturing > defects at relatively low cost, compared to the total cost of the product. Actually the point was Ford not even checking, and shipping it AS-IS, a little stronger point that Xilinx partially testing. > Xilinx *might* be able to repair some bad dice by using FIB, but the > cost of doing so would significantly exceed the original cost of the > die, and although the result might be functional, it could not be > guaranteed to have comparable reliability to a normal part. Thus it > could not be sold except perhaps as an unqualified engineering sample. Repair of defects is completely a different topic. > Finally, they aren't "dumping", which would be selling below cost. They > are likely making quite a tidy profit on Easypath, since although the > price is lower than for a fully tested FPGA, the cost is also lower. > Time on a semiconductor tester is very expensive, thus anything that > reduced the test time significantly reduces the total part cost. Tell the stock holders that when they put sellable "bad" dice in the trash can, and ship good dice which were not fully tested for a heavy discount, that CAN drop below the "cost" of a good die. There are two lost profits in this business plan ... shipping good die at less than cost, and trashing usable die that would qualify under an easypath shipment. The sum of these two failures, is easily worth a significant fraction of Xilinx's current revenue, and the management finders fee (AKA bounus) for correcting this is probably more than most people will retire with. My finders fee is a lot less .... a briefcase full of discarded XC4VLX200's which currently don't have any value and they probably have to pay to get destroyed and hauled off.Article: 98945
Austin Lesea wrote: > Just wanted to be sure you were not on their pay roll. > > I have been made a fool of once before thinking I was talking to a > potential customer when it was someone who was an actual competing > company employee...boy did I feel stupid. Ouch ... talk about getting baited :( Nope ... I don't even know an Altera person. I do know or have met several Xilinx people who have always been great people to deal with. Every time I've been against the wall, there's been a Xilinx FAE to help. Field staff always seem to have great customer skills.Article: 98946
Well Jeff Brower is absolutely right.Ppl r here to discuss the technical problems and not to discuss the formalities we need to make . John u also asked where Palnitkar said that task is synthesizable? Refer" 2nd edition of Verilog HDL by Palnitkar,Chapter 14 ,Section 14.3.1 ,Page No. 305" u will find that Task is INDEED SYNTHESIZABLE. And for your kind information I got my code synthesized...Cheers. And I have used Task in my code and it got synthesized.If u need my code i will send it 2 u. No Hard feelings John.Article: 98947
John Williams' "Partial Reconfiguration on Xilinx Devices" email list is another resource: http://www.cs.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ The archive is available here: http://www.itee.uq.edu.au/~listarch/partial-reconfig/ Valerios wrote: > > Hi > I am a student, write a diploma about application of partial > reconfiguration. Would not you to give me materials where is the > fast-acting with partial reconfiguration and without it compared? > Beforehand thankful.Article: 98948
"Chauhan" <coolsaroj@gmail.com> wrote in message news:1142638902.235823.151710@i39g2000cwa.googlegroups.com... > Well Jeff Brower is absolutely right.Ppl r here to discuss the > technical problems and not to discuss the formalities we need to make . > John u also asked where Palnitkar said that task is synthesizable? > Refer" 2nd edition of Verilog HDL by Palnitkar,Chapter 14 ,Section > 14.3.1 ,Page No. 305" u will find that Task is INDEED SYNTHESIZABLE. > > And for your kind information I got my code synthesized...Cheers. > And I have used Task in my code and it got synthesized.If u need my > code i will send it 2 u. > No Hard feelings John. Different John. JJ mentioned the syntesizables, I asked about chatonics. You are *seriously* detracting from the technical aspects of discussion; I had a bit of a headache before trying to decipher your chatter. It's seriously grotesque. Why?Article: 98949
Well the above post was adressed not 2 u but 2 JJ definetly.Sorry for giving u headache.
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z