Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Has anyone managed to get a Verilog testbench to force an internal DUT signal using ISE (9.2i)? This seems to be impossible. A DUT force has to be, pretty much by definition, hierarchical. If you try something like force top.mod.x = y; // or... assign top.mod.x = y; you get a message about an unsupported hierachical expression. Tweaking the assignments eventually gives you the catch-all unsupported constructs message, with details in #24068 and an accompanying pdf doc. The suggested work-around - to add new ports to the DUT - isn't helpful. The ISE docs claim to support 'procedural continuous assignments', but this seems to be a rather wide definition of 'supported'. Thanks - EvanArticle: 124701
On Sun, 30 Sep 2007 23:36:10 +0100, "Tim (one of many)" <tim@nooospam.roockyloogic.com> wrote: >I have a design which uses around 80% of an XC5V330. Synthesis to EDIF >is via Synplicity and it's pretty quick. > >MAP is another story. It takes around six hours and uses upwards of >6GByte (not a typo) of memory. Actually MAP claims to have used 6GB, but >Linux/LSF reports that MAP has used 12GB. The machine has 16GB installed. > >Since the Synplicity EDIF is essentially a bunch of LUT definitions, I >cannot see what MAP could be doing that needs this immense slug of >memory and time. The target speed is 20MHz, which is DC on an XC5V part, >and Synplicity believes it has achieved it. Are there any hints and tips >out there for switches or whatever that could cut the processing resources? > >For the future, Smartguide looks good. But first the design has to be >stable. For XC5, MAP also (by default) performs the placement part of PAR, see "timing driven placement". This has been optional but not very useful on previous logic families, but my limited V5 experience suggests that for Virtex-5, "timing driven placement" at the MAP phase yields huge benefits over the traditional placement phase during PAR. I've no idea why it makes such a difference with V5, but apparently not with previous families. So while MAP takes a long time; PAR will be faster to compensate. One ProjNav bug in 9.2: if you want to change the constraint table entry because you just missed timing, be aware that MAP now has its own constraint table entry; change them both and keep them in step! Otherwise MAP will run for 6 hours, then PAR (seeing a different seed) will throw away the (good) placement and take 6 more hours to create its own (terrible) one! This makes MPPR singularly useless under these circumstances; another good reason to script/batch your own... - BrianArticle: 124702
Tim (one of many) wrote: > I have a design which uses around 80% of an XC5V330. Synthesis to EDIF > is via Synplicity and it's pretty quick. > > MAP is another story. It takes around six hours and uses upwards of > 6GByte (not a typo) of memory. Actually MAP claims to have used 6GB, but > Linux/LSF reports that MAP has used 12GB. The machine has 16GB installed. > > Since the Synplicity EDIF is essentially a bunch of LUT definitions, I > cannot see what MAP could be doing that needs this immense slug of > memory and time. The target speed is 20MHz, which is DC on an XC5V part, > and Synplicity believes it has achieved it. Are there any hints and tips > out there for switches or whatever that could cut the processing resources? > > For the future, Smartguide looks good. But first the design has to be > stable. I've had some instances in the past where mistakes in my code (mistakes from the perspective of my intent, not syntax errors) have sent the mapper phase of the Synplify compile into an uncharacteristically long phase. If you had been running fine but suddenly hit a wall, look for the changes you made that brought on the 6 hour mapping phase that produces your EDIF so slowly. My recollection of one problem was the inference of a memory that wasn't integrating nicely into the Xilinx primitive; I ended up with thousands of registers in its place. While thousands of registers shouldn't bring on a long map phase themselves, there was something very strange about the way I inferred the memories that seemed to get the map phase of the synthesis bound up in a knot. It's probable the good folks at the Synplicity hotline can run your code through the synthesizer and - with performance monitors the developers use - determine what aspect of the code is crunching all that time. - John_HArticle: 124703
Hello, I'm beginner in VHDL and practice with Xilinx ISE 9.2. I want to test and8 with generic, the code is similiar to "Circuit Design with VHDL" books code and I don't understand where is problem. The synthesiser shows error: "Line 19. parse error, unexpected RANGE" library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gener_test is generic(n: integer := 8); port (input: in std_logic_vector(n-1 downto 0); output: out std_logic); end gener_test; architecture Behavioral of gener_test is signal tmp1: std_logic_vector(n-2 downto 0); --signal tmp2: std_logic; begin process(input) begin tmp1(0) <= input(0) and input(1); for i in range (1 to n-2) loop tmp1(i) <= input(i+1) and tmp(i-1); end loop; output <= tmp1(n-2); end process; end Behavioral;Article: 124704
Remove the keyword "range" inside the for loop and also the braces. Your line 19 shd be "for i in 1 to n-2 loop" -- parag On Oct 1, 9:05 am, "VladimirM" <VladimirMatve...@gmail.com> wrote: > Hello, > I'm beginner in VHDL and practice with Xilinx ISE 9.2. I want to test and8 > with generic, the code is similiar to "Circuit Design with VHDL" books code > and I don't understand where is problem. The synthesiser shows error: "Line > 19. parse error, unexpected RANGE" > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity gener_test is > generic(n: integer := 8); > port (input: in std_logic_vector(n-1 downto 0); > output: out std_logic); > end gener_test; > > architecture Behavioral of gener_test is > signal tmp1: std_logic_vector(n-2 downto 0); > --signal tmp2: std_logic; > begin > process(input) > begin > tmp1(0) <= input(0) and input(1); > for i in range (1 to n-2) loop > tmp1(i) <= input(i+1) and tmp(i-1); > end loop; > output <= tmp1(n-2); > end process; > > end Behavioral;Article: 124705
Hi all, does anyone know if the MicroBlaze Processor of Xilinx has the CLZ Instruction? I took a look in the datasheet, but didn't find anything about it. I would like to count the number of zeros in a 32-bit Register in one cycle. If this processor does not support this function, could you maybe suggest me how to calculate this operation as fast as possible? Thanks, ArmandoArticle: 124706
Antti wrote: > Hi > > I know many wise men has said NO NO, but > > 1) > http://www.latticesemi.com/forums/forum/messageview.cfm?catid=42&threadid=3505 > > Lattice engineer suggest that it works (assumable reliable) on machXO > > the IO technology between machXO and Xilinx FPGAs isnt so big so I > wonder why cant it be done with Xilinx ? > > for what I see is following > > 25MHz crystal > 27p caps > 560 series > 1M parallel > > when using LVCMOS33 SLEW=FAST > I can't address the specific chip, and you have to think about input->output delay, but it shouldn't be a big problem. I did just this on a recent design using a Xilinx 5V CPLD, and it worked beautifully with a 10 MHz crystal. I used no parallel resistor, and no series resistor, although I was just a little worried about overdrive, there. My caps were 15 pF (xtal vendor recommended 18 pF, but I have some parasitic capacitance on the board and chip pins). As far as I can tell it is working like a dream. You might set the slew to slow, that is still plenty fast for a 25 MHz signal. JonArticle: 124707
Nico Coesel wrote: > > Xilinx could buy such a circuit as IP and integrate it. The parts > containing non-volatile configuration memory would benefit greatly and > could potentially replace microcontrollers. A PLL would even be better > and also reduces the range of crystal frequencies that need to be > supported. 4MHz to 16MHz would be enough. > Don't bug Xilinx with such troubles. If the oscillator doesn't work reliably, go back to your OWN bench and figure out what you need to do. With a series and parallel resistor and resonating caps, you should be able to find component values that make it work. Now, maybe a volatile-config FPGA is a different sort of problem, because the power comes up and stabilizes long before the internal logic finishes configuration and becomes active. This may allow the power-on transients to have died out so the parallel resistor is critical to balance the input right on the threshold, or the start-up is not reliable. I think the Xilinx CPLDs work the same way, just that the internal configuration happens much quicker. I have been using Xilinx CPLDs and smaller FPGAs in places others often select microcontrollers, because latency is much less, and I feel the programming has fewer pitfalls. Of course, as long as you are not using a uP core, the application limits which technology is appropriate. JonArticle: 124708
Antti wrote: > Hi > > I am evaluating the possibility to use 2 resitor video output from > FPGA similar to: > > http://www.excamera.com/articles/15/ntsc.html > > to generate color NTSC output, so far my results show less quality Cool! For color, you would want your main clock to be some multiple of the color subcarrier frequency. In the US (NTSC) that is 3.57954525 MHz, so a good frequency might be 128 times that, or 458.1819 MHz. You have to generate the color subcarrier, whose amplitude is proportional to color saturation, and whose phase (relative to the reference burst at the beginning of each line) gives the angle around the hue wheel. This is mixed with the luminance signal. A portion of the luminance bandwidth is chopped out and sent to the color decoder. JonArticle: 124709
I think the "webmaster" may be overwhelmed by two jobs and parenthood... Hopefully some proverbial "free time" will show up soon so he can finish the transition to a new web hosing service. In the meanwhile, if there is something specific you are looking for, email me directly with the request and I'll be happy to send it to you. Eric "Antti" <Antti.Lukats@googlemail.com> wrote in message news:1191135331.336160.93980@d55g2000hsg.googlegroups.com... > looks like the website is down, any info if it that is temporary or > not? > > Antti >Article: 124710
Evan Lavelle wrote:
> assign top.mod.x = y;
>
> you get a message about an unsupported hierarchical expression.
Hmm.
Is x also declared as a testbench wire?
is
assign top.mod.x = y;
outside of blocks?
-- Mike Treseler
Article: 124711Hi all, I am designing a Spartan3E board with a DDR SDRAM. The DDR is, similarly as in Spartan3E Starter Kit but connected to bank1 (2.5V with 1.25V reference) for lower routing delay. The Spartan3E SK the clock fedback is confusing me: On S3Estarter, it goes to another bank (bank 0). They wrote in the manual: The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have best access to one of the FPGA's Digital Clock Managers (DCMs). This path is required when using the MicroBlaze OPB DDR controller. Of course, here the signal standard won't match (3.3V instead of 2.5V) and they did not connect VREF to in this bank. Does this matter or not? In the banks with low routing delay (1 and 3), there are no global clocks, only LH and RH clocks. Will they work too? Cheers, GuruArticle: 124712
On 1 Okt., 19:56, Jon Elson <el...@wustl.edu> wrote: > Antti wrote: > > Hi > > > I know many wise men has said NO NO, but > > > 1) > >http://www.latticesemi.com/forums/forum/messageview.cfm?catid=42&thre... > > > Lattice engineer suggest that it works (assumable reliable) on machXO > > > the IO technology between machXO and Xilinx FPGAs isnt so big so I > > wonder why cant it be done with Xilinx ? > > > for what I see is following > > > 25MHz crystal > > 27p caps > > 560 series > > 1M parallel > > > when using LVCMOS33 SLEW=FAST > > I can't address the specific chip, and you have to think about > input->output delay, but it shouldn't be a big problem. I did just this > on a recent design using a Xilinx 5V CPLD, and it worked beautifully > with a 10 MHz crystal. I used no parallel resistor, and no series > resistor, although I was just a little worried about overdrive, there. > My caps were 15 pF (xtal vendor recommended 18 pF, but I have some > parasitic capacitance on the board and chip pins). As far as I can tell > it is working like a dream. > > You might set the slew to slow, that is still plenty fast for a 25 MHz > signal. > > Jon- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - well, its not "might" in some cases you "need" set slew slow (or maybe further adjust the component values) with slew-fast on S3A there was overdrive overkilling the oscillation so it periodically stopped and started again (the inverter output only, the input was always seeing the crystal swing), but the DC bias did run away into outside the input range so the internal signal did stop. well, maybe have to use "safe ring oscillator" to bootstrap and monitor the crystal circuit and DCM locks but I think with extreme care and bench testing it should be all doable AnttiArticle: 124713
On Oct 1, 4:48 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > armando...@googlemail.com wrote: > > I would like to count the number of zeros in a > > 32-bit Register in one cycle. > > It is more common to have an instruction to count ones. > If so, complement and then count the ones. > > > If this processor does not support this function, could you maybe > > suggest me how to calculate this operation as fast as possible? > > There are well known ways to do this in C, though maybe not as > fast as you would like. One uses a 256 byte lookup table and > sums over the four bytes of a 32 bit value. Another uses > the bitwise AND operator and addition to add pairs of bits, > sums the pairs, quads, octets, etc. > > It is not hard to do in FPGA logic as a carry save adder tree. > If it can't be done in a single cycle at your clock rate it is > easily pipelined. > > -- glen Unless you really only want to count the leading zeroes, which only needs a priority encoder...Article: 124714
On Mon, 01 Oct 2007 12:14:50 -0700, Mike Treseler
<mike_treseler@comcast.net> wrote:
>Evan Lavelle wrote:
>
>> assign top.mod.x = y;
>>
>> you get a message about an unsupported hierarchical expression.
>
>Hmm.
>Is x also declared as a testbench wire?
>is
> assign top.mod.x = y;
>outside of blocks?
The syntax is valid; (this) assign is a procedural statement which can
only be used on variables (and the test code works on two other sims).
The procedural assign isn't particularly useful; I only mentioned it
because it shows the same problem as the 'force' statement, which *is*
very useful.
X's error message and docs claim that it's the hierarchical reference
on the LHS ('top.mod.x') which is unsupported, but ISE actually has no
problem with hierarchical lvalues. It only appears to be procedural
force/assign which is affected.
It can be pretty hard to write comprehensive testbenches without a
force statement, so I was hoping to find someone who may have a
workaround, short of wiring up extra ports in the DUT.
Evan
Article: 124715armandolou@googlemail.com wrote: > I would like to count the number of zeros in a > 32-bit Register in one cycle. It is more common to have an instruction to count ones. If so, complement and then count the ones. > If this processor does not support this function, could you maybe > suggest me how to calculate this operation as fast as possible? There are well known ways to do this in C, though maybe not as fast as you would like. One uses a 256 byte lookup table and sums over the four bytes of a 32 bit value. Another uses the bitwise AND operator and addition to add pairs of bits, sums the pairs, quads, octets, etc. It is not hard to do in FPGA logic as a carry save adder tree. If it can't be done in a single cycle at your clock rate it is easily pipelined. -- glenArticle: 124716
On Sep 29, 7:22 pm, I wrote: > I have some random stuff athttp://www.merlintec.com/download/but > unfortunately that doesn't include any HDL code yet. I will try to > find the NTSC test next week (in VHDL) and make it available. Found it and it is now at http://www.merlintec.com/download/video.vhd Most of the 218 lines are there to implement a test of the bar code reader shown as a scrolling display in the middle of the video output. You don't need any of that and just eliminating the lines where this is output (in the "dac <= ..." part) will cause the compiler to optimize away all the related circuits. There are some complications left over from early attempts to multiply a 14MHz clock signal (the DLLs only handle 25MHz and up) but that is mostly commented out. You need the proper factor to generate the 4 * 3,579,545 Hz clock from your input clock (in the "corr_fase <=" part). Sorry that some variable names and comments are in Portuguese - my clients didn't speak English. -- JecelArticle: 124717
"Eric Crabill" <eric.crabill@xilinx.com> wrote in message news:fdrgg0$fjj1@cnn.xilinx.com... >I think the "webmaster" may be overwhelmed by two jobs and parenthood... >Hopefully some proverbial "free time" will show up soon so he can finish >the transition to a new web hosing service. In the meanwhile, if there is >something specific you are looking for, email me directly with the request >and I'll be happy to send it to you. > > Eric > Hey Eric, "web hosing"! I knew Senator Stevens was right! Take care, Syms.Article: 124718
Hi, Is there any body uses the Large FPGA to build test and measurements equipments. If you use it, how big is the idle FPGA for you. thanks NarsiArticle: 124719
May I know what is the company On Sep 30, 12:50 pm, "To: Kshitij Arora <" <arora....@gmail.com> wrote: > Hi , > Currently i am working with a Semiconductor Design House as a PDK > Application Engineer. My primary job function is to support the > design teams with PDK(this icludes, DRC/LVS, LPE ,models, > techfiles..etc) related issues. I have been working in this filed for > almost 3 years. I am interested in exploring Synthesis, Place & Route > more than compared to what i am doing right now. Recently I got an > opportunity in FPGA domain. This new job offers exposure to synthesis > and P&R in FPGA domain. I dont have much knowledge about FPGA, i am > not sure how different will it be from the ASIC world. Will this add > to my earlier work experience that i have in Semi Custom/Asic > domain ? > To be more specific, will a Designer who has been working on FPGAs be > acceptable in ASIC world, will he have the almost same market value > in ASIC domain ? If i switch then will my earlier wrk exp be scraped. > If anybody could help me evaluate/(provide some feedback) on these > concerns, it would be highly appreciated. That would help me make a > right move for my career. > > Thanks & Regards > LuckyArticle: 124720
Jecel wrote:
> Found it and it is now at
>
> http://www.merlintec.com/download/video.vhd
Thanks for the example.
-- Mike Treseler
__________________________
Note:
abarras <= pbarras+cnt(11 downto 2) when wbarras='0'
else pbarras;
** Error: Length of expected is 9;
length of actual is 10.
Article: 124721"Narsi" <pnarsi@gmail.com> wrote in message news:1191283138.476957.265860@w3g2000hsg.googlegroups.com... > Hi, > > Is there any body uses the Large FPGA to build test and > measurements equipments. > If you use it, how big is the idle FPGA for you. > > thanks > Narsi > I have. It was this big for me. http://youtube.com/watch?v=wpmzS9mjz_I Sorry.Article: 124722
On Oct 1, 9:03 pm, Mike Treseler wrote:
> Note:
> abarras <= pbarras+cnt(11 downto 2) when wbarras='0'
> else pbarras;
>
> ** Error: Length of expected is 9;
> length of actual is 10.
That is indeed wrong! I wonder if this used to be a warning back in
2003 (probably WebPack 3 or so) and I just ignored it.
Anyway, this is part of the stuff that is unrelated to the video test
itself. I just had a 512 bit FIFO that was shifted 16 times per frame
each frame (960 samples per second) so I could use part of the screen
as a cheap osciloscope showing what the bar code reader (just a LED
and photo diode) was seeing so I could debug that part of the circuit.
It might come in handy if you connect a relatively slow signal to
"leitor", like a RS232 input or something.
But it would be better to just clean this up and replace the sine
("seno" in Portuguese) part with shift16 circuits as I mentioned
previously. The result would be really tiny. Missing lots and lots of
stuff, like filters, that are needed for a high quality video, of
course. But one of my computers is an Apple II, so you know I can live
with sloppy NTSC ;-)
-- Jecel
Article: 124723selva kumar wrote: > Hi, > I'd like to set up block rams(16k) to acts as a ROM lookup table > after initialization. After establishing the Memory Area as an FPGA > resource there's an option to initialize it by using memory eritor. > However, this would be very time consuming, as my memory is 16Kwords > deep. Is there some way to just reference an external text file, or > excel sheet at least automatically read/paste an external file for > this purpose? > > and also How to combine both block memory and distributed memory > (using lut) to use as one memrory of 16k? > that is , > I want 2 implenet 2 memory of size 16kX8 in fpga spartan-3 one a6X8 > take 8 block ram out of 12 block ram available in fpga? > then when I tried to use only LUT as ram of size 16kX8 the resourses > are not enough.so can u tell me hoe to combine remainning 4 blokc ram > and LUTs to implement one more memory of size 16kX8 > > please mail to me at vkmselva@gmail.com > As far as initializing a memory the .coe file is the most convenient in most applications. You can provide that file when you generate the memory in coregen. To combine a distributed memory with a bram memory you could generate both parts as separate cores in coregen and combine them with your own logic.Article: 124724
Have you tried it yet? How do you like it? Does it solve the horrible slow opening of Nios II components in SOPC Builder?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z