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>Hello All, > >I have a system which consists of many subsystems which will be >connected >to a common bus (this includes 16-bit data and 16-bit address buses). >This system is FPGA-based and I want to control its work through GUI >from PC host. >Hence, a program on PC host has to know addresses of sunsystems in >order to communicate with them. My question is - how my program will >know the addresses of each subsystems of the system and how these >addresses are assigned? So far, my host knows only addresses of it's >external ports, i.e. serial and parallel, but has no idea about what >could be addresses of subsystems on FPGA. > The driver software in the PC will have to configured to know the addresses. The method will depend on how the drivers are written, and what sort of PC->external bus. This is a software problem, not an FPGA problem.Article: 125376
On Oct 24, 12:04 pm, "RCIngham" <robert.ing...@gmail.com> wrote: > >Hello All, > > >I have a system which consists of many subsystems which will be > >connected > >to a common bus (this includes 16-bit data and 16-bit address buses). > >This system is FPGA-based and I want to control its work through GUI > >from PC host. > >Hence, a program on PC host has to know addresses of sunsystems in > >order to communicate with them. My question is - how my program will > >know the addresses of each subsystems of the system and how these > >addresses are assigned? So far, my host knows only addresses of it's > >external ports, i.e. serial and parallel, but has no idea about what > >could be addresses of subsystems on FPGA. > > The driver software in the PC will have to configured to know the > addresses. The method will depend on how the drivers are written, and what > sort of PC->external bus. > > This is a software problem, not an FPGA problem. Well, could you give an advice where to start learning how to write a driver? and how to configure a driver?Article: 125377
>> This is a software problem, not an FPGA problem. >Well, could you give an advice where to start learning how to write a >driver? >and how to configure a driver? You're in the wrong newsgroup.Article: 125378
The Xilinx Spartan-3E can be configured from an Atmel SPI dataflash. This dataflash can be programmed with a download cable and the impact tool. From what I can find in the tool and docs it is only possible to program xilinx bitstream files into the dataflash. For my application, I also want to include the program code for an external CPU in the dataflash. The CPU will boot from the dataflash, also read the bitstream data from it and then configure the FPGA, using the slave serial configuration option. Is there a posibility to program arbitrary binary files in a dataflash with the impact tool and xilinx download cable? -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 125379
On Oct 24, 12:58 pm, MikeShepherd...@btinternet.com wrote: > >> This is a software problem, not an FPGA problem. > >Well, could you give an advice where to start learning how to write a > >driver? > >and how to configure a driver? > > You're in the wrong newsgroup. ...and this is why the right direction was asked. But never mind!Article: 125380
Hi all, I've got a question about Multiplinx ( USB/JTAG interface) and ChipScope Pro. I'm using ISE 9.1i and I would like to use chipScope Pro to debug my design but it seems that multilinx platform is not supported by recent versions of chipScope Pro. Did anyone have the same problem ? Does anyone know a solution avoiding me to buy a new platform cable USB ? Thanks by advance, Best regards, Michel.Article: 125381
Vagant wrote: > On Oct 24, 12:58 pm, MikeShepherd...@btinternet.com wrote: > >>>>This is a software problem, not an FPGA problem. >>> >>>Well, could you give an advice where to start learning how to write a >>>driver? >>>and how to configure a driver? >> >>You're in the wrong newsgroup. > > > ...and this is why the right direction was asked. But never mind! > I was once in the a similar position as you are in now, with a similar system... PC host talking to attached (FPGA) based hardware. I wasn't able to see how to solve the problem until several years later when I gained a lot more experience developing embedded systems, so I don't think a news group is going to give you the answer. As far as a push in the right direction, I would recommend downloading a copy of the book on Linux Device Drivers and tryin to work through that. It should help to give you some idea of how to build the bridge between your hardware and software.Article: 125382
On Oct 24, 11:45 am, spartan3wiz <magnus.wedm...@gmail.com> wrote: > The way this post is formed in could invite non-subject post thats > rude so I'll try to answer it "correctly" with some facts. > > Congratulations Vagant, you have just bough yourself one of the best > Value-For-Money FPGA-Development boards that are out there today I > think. You'll probably be good with it for many years to come if you > are willing to learn. I also bought it when Digilent start selling it > without the Microblaze Kit which made it a bargain. Of course just > because it is called "Microblaze" there is no need to use it solely > for that. > > You can use this board almost for anything as you can see at the demos > shipped with it, stand-alone web-server, complete Microblaze-based > Linux operating system. > > My suggestion would be that you start off by doing the classical > Button/Led trick where you install ISE Webpack and by using Verilog or > VHDL you setup each button to light a LED.. This is of course massive > hardware overkill but at least you know your tools and that everythin > is connected correctly. Don't start with LCD because this needs SPI- > control and specific protocol which would be a litle messy to start > with I think. Also skip the Rotation-device as this also can bring you > some problems as a beginner.. > > I have ported the FPGA-64 (part of C-One project) for this Kit which > implements a quite complete Commodore 64. just did it for fun and for > experience. > > Another suggestions is to use the Windows tools as the USB-connection > in PC-Linux can bring you some intial problems you don't need on your > first testrun. > > Good luck with your kit! Hi, thanks a lot for reply. I also got idea that it's a great board, mainly from others. I have just started and have not find any detailed examples how to move forward learning this. I am surprised that you've got demos with this board coz I've got none. There were no tutorials included in box, just a CD with ISE WebPack 9.1 and DVD with ISE WebPack and EDK. There are many materials on Xilinx's Web Site but all these are mainly about advanced programming and there is almost nothing for beginners.Article: 125383
On Oct 24, 5:04 am, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote: > >For certain addressing patterns, the refresh can be eliminated > >alltogether, when the addressing sequence is such that all (used) > >memory cells are naturally being read, and thus refreshed, within the > >required time. > > That happens in a couple of common cases... > > Running video refresh out of DRAM > Running DSP code > Running memory tests :) > > I once worked on a memory board that worked better (at least as > measured by memory diagnostics) when the refresh was clipleaded out. > (We had a bug in the arbiter.) > > -- > These are my opinions, not necessarily my employer's. I hate spam. For SDR SDRAMs, the refresh period depends on the density. Highest density parts need twice the refresh rate (about 7.8 uS vs 15.6 uS). If you sensed the part size, or used a DIMM or SO-DIMM with a PROM for configuration, you may want to set up the refresh rate (once) after the FPGA is running. A full-fledged SDRAM controller could also set up other parameters based on a configuration PROM. This is not something that needs to be dynamic for any given system. You wouldn't swap out DIMMs with the power on. However it can be more useful than requiring a different configuration load for the FPGA depending upon the installed memory.Article: 125384
On Oct 24, 7:26 am, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > On Oct 24, 12:58 pm, MikeShepherd...@btinternet.com wrote: > > > >> This is a software problem, not an FPGA problem. > > >Well, could you give an advice where to start learning how to write a > > >driver? > > >and how to configure a driver? > > > You're in the wrong newsgroup. > > ...and this is why the right direction was asked. But never mind! If you are using Linux, get "Linux Device Drivers". You can get a free pdf of it here: http://lwn.net/Kernel/LDD3/ Regards, John McCaskill www.fastertechnology.comArticle: 125385
On Oct 24, 2:16 pm, Noway2 <Now...@triad.rr.com> wrote: > Vagant wrote: > > On Oct 24, 12:58 pm, MikeShepherd...@btinternet.com wrote: > > >>>>This is a software problem, not an FPGA problem. > > >>>Well, could you give an advice where to start learning how to write a > >>>driver? > >>>and how to configure a driver? > > >>You're in the wrong newsgroup. > > > ...and this is why the right direction was asked. But never mind! > > I was once in the a similar position as you are in now, with a similar > system... PC host talking to attached (FPGA) based hardware. I wasn't > able to see how to solve the problem until several years later when I > gained a lot more experience developing embedded systems, so I don't > think a news group is going to give you the answer. > > As far as a push in the right direction, I would recommend downloading a > copy of the book on Linux Device Drivers and tryin to work through that. > It should help to give you some idea of how to build the bridge > between your hardware and software. Many thanks for advice. :)Article: 125386
On Oct 24, 3:23 pm, John McCaskill <jhmccask...@gmail.com> wrote: > On Oct 24, 7:26 am, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > > > On Oct 24, 12:58 pm, MikeShepherd...@btinternet.com wrote: > > > > >> This is a software problem, not an FPGA problem. > > > >Well, could you give an advice where to start learning how to write a > > > >driver? > > > >and how to configure a driver? > > > > You're in the wrong newsgroup. > > > ...and this is why the right direction was asked. But never mind! > > If you are using Linux, get "Linux Device Drivers". You can get a free > pdf of it here: > > http://lwn.net/Kernel/LDD3/ > > Regards, > > John McCaskillwww.fastertechnology.com Thank you for the link. I want to use Linux as an OS running on host. However, I wonder whether a system designed using ISE WebPack under Windows will be working with Linux.Article: 125387
Hi all, I am trying to use a Aurora Core and MGT transceiver to get high Speed serial transmission signal out. I have run into several problems.. One problem is getting the Aurora Core simulated... I generated a core using the core generator with the following settings. Streaming, Simplex -Both directions. I tried to simulate the design using the given tb and the do scripts. The clocks are toggling..but there is not data being transferred.. I tried several versions of the aurora 2.4, 2.6, 2.7, 2.7.1.. Still the same issue.. Do_CC is also not asserted. so idle signals are not being sent... Is there something I am missing... Also I need to send the high speed signal out to to RF unit... So there is no initialization signals being sent back.. And tx_d_ready signal from the receiver. The initialization can be probabaly set by the sender side.. but how does the tx_d_ready signal assrted from the GT_Aurora primitve. FPGA Board - Xupv2p FPGA - XC2VP30 My setup is ISE 9.1i Sp3. Thanks, Cheers ShakithArticle: 125388
On Oct 24, 9:59 am, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > On Oct 24, 3:23 pm, John McCaskill <jhmccask...@gmail.com> wrote: > > > > > On Oct 24, 7:26 am, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > > > > On Oct 24, 12:58 pm, MikeShepherd...@btinternet.com wrote: > > > > > >> This is a software problem, not an FPGA problem. > > > > >Well, could you give an advice where to start learning how to write a > > > > >driver? > > > > >and how to configure a driver? > > > > > You're in the wrong newsgroup. > > > > ...and this is why the right direction was asked. But never mind! > > > If you are using Linux, get "Linux Device Drivers". You can get a free > > pdf of it here: > > >http://lwn.net/Kernel/LDD3/ > > > Regards, > > > John McCaskillwww.fastertechnology.com > > Thank you for the link. I want to use Linux as an OS running on host. > However, I wonder whether > a system designed using ISE WebPack under Windows will be working with > Linux. The OS that you are running the FPGA tools under does not lock your design to having to be hosted by the same OS. We produce PCI cards with Virtex-4 FX FPGAs on them. See www.fastertechnology.com for more info on them. We run EDK, ISE, ModelSim, and ImpulseC on Windows computers. We only support Linux for the PCI cards host and embedded OS. The fact that we use Windows to compile the FPGA bit streams does cause problems with using those bit streams in a Linux environment. Regards, John McCaskill www.fastertechnology.comArticle: 125389
Hello all, Can anyone point me to a good general purpose paper about selecting appropriate bit-widths for a fixed point implementation of a signal processing algorithm? I've looked around and haven't found anything that describes a general methodology to use. I have implemented a design and it isn't performing as well as I would like. I suspect it has to do with some poor selection of bit slicing when it comes to multipiers and accumulators. Thanks for your help!Article: 125390
Shakith, On simulation issue you need to have support for swift models in your simulator, although personally I think there is very little value in simulating MGTs if you are going to use one of the standard cores such as Aurora. WRT initialization, read carefully the chapter on Simplex Initialization in the Aurora User Guide. The easiest to initialize are full-duplex channels. Simplex channels require either a back channel or tricks with using timers. I used the former method in my design. /Mikhail <shakith.fernando@gmail.com> wrote in message news:1193234536.652408.171350@z24g2000prh.googlegroups.com... > Hi all, > > I am trying to use a Aurora Core and MGT transceiver to get high Speed > serial transmission signal out. > I have run into several problems.. > > One problem is getting the Aurora Core simulated... > I generated a core using the core generator with the following > settings. Streaming, Simplex -Both directions. > I tried to simulate the design using the given tb and the do scripts. > The clocks are toggling..but there is not data being transferred.. I > tried several versions of the aurora 2.4, 2.6, 2.7, 2.7.1.. Still the > same issue.. Do_CC is also not asserted. so idle signals are not being > sent... Is there something I am missing... > > Also I need to send the high speed signal out to to RF unit... > So there is no initialization signals being sent back.. And > tx_d_ready signal from the receiver. > The initialization can be probabaly set by the sender side.. but how > does the tx_d_ready signal assrted from the GT_Aurora primitve. > FPGA Board - Xupv2p > FPGA - XC2VP30 > My setup is ISE 9.1i Sp3. > > Thanks, > > Cheers > Shakith >Article: 125391
Jonathan, why so aggressive? I was just pointing out that certain applications naturally perform sufficient refresh operations in their normal addressing sequence. I can't see why this is "completely ridiculuous"... Peter Alfke On Oct 24, 12:40 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Wed, 24 Oct 2007 07:15:08 -0000, > > Antti <Antti.Luk...@googlemail.com> wrote: > >> For certain addressing patterns, the refresh can be eliminated > >> alltogether, when the addressing sequence is such that all (used) > >> memory cells are naturally being read, and thus refreshed, within the > >> required time. > >> Peter Alfke- Zitierten Text ausblenden - > > >> - Zitierten Text anzeigen - > > >Sinclair ZX? > >at least some old Z80 homecomputers used refresh by video scan > > Yes, and it's a completely ridiculous way to do it. The > added cost of making frequent additional row accesses is > far greater than the cost of the necessary refresh. > > A DRAM row is effectively a cache. When you access a row, > you read the whole row into the DRAM's row buffer as a free > side-effect, and can then make very fast column accesses > to anly location in the row. It's preposterous to throw > away that massive free bandwidth just to save yourself > some refresh effort - unless you're trying to design > a $80 home computer/toy in the early 1980s. > > In those days, the video buffer was a sufficiently > large fraction of the overall DRAM that it was > reasonable to lay out the video memory so that > every row was automatically visited by the video > scan, giving a refresh cycle every 20ms (16.7ms > in the USA). That was out-of-spec for many DRAMs > of the day (8ms refresh cycle) but in practice it > worked in almost all cases - and the manufacturers > of those computers had a shoddy enough warranty > policy that they weren't going to worry about a > handful of customers complaining about occasional > mysterious memory corruption on a hot day. > > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated.Article: 125392
On Oct 24, 2:15 am, Antti <Antti.Luk...@googlemail.com> wrote: > On 24 Okt., 07:50, Peter Alfke <al...@sbcglobal.net> wrote: > > > > > On Oct 23, 5:27 pm, "David Spencer" <davidmspen...@verizon.net> wrote: > > > > <MikeShepherd...@btinternet.com> wrote in message > > > >news:1evsh3ds7i44iqhrsc4kldthlo2vb0tul2@4ax.com... > > > > > Although it's not expressed in DRAM specs and you wouldn't want to > > > > rely on it, the effect of reducing refresh rate is to increase the > > > > access time. I'm not up-to-date with DRAM technology, but my > > > > experience with devices 30 years ago was that you could turn off > > > > refresh (and all other access) for 10s or more without losing the > > > > contents, provided you weren't pushing the device to its access time > > > > limits. > > > > > So, it's not impossible that reducing refresh rate would have a use > > > > (albeit outside the published device spec). But, as you suggest, it > > > > would help if he would just tell us what he's trying to do. > > > > > Mike > > > > Although that may well be the case for asynchronous DRAMs (because the > > > reduced charge in the memory cell capacitor would mean that the sense > > > amplifier took longer to register the state), this would not be the case for > > > SDRAM since this registers the outputs a fixed number of clocks after the > > > access starts. If the underlying access time increased by too much then the > > > data would just be wrong. > > > For certain addressing patterns, the refresh can be eliminated > > alltogether, when the addressing sequence is such that all (used) > > memory cells are naturally being read, and thus refreshed, within the > > required time. > > Peter Alfke- Zitierten Text ausblenden - > > > - Zitierten Text anzeigen - > > Sinclair ZX? > at least some old Z80 homecomputers used refresh by video scan > > Antti If I recall, the Apple II also refreshed its RAM this way, too. -Dave PollumArticle: 125393
Vagant wrote: > On Oct 24, 3:23 pm, John McCaskill <jhmccask...@gmail.com> wrote: > >>On Oct 24, 7:26 am, Vagant <vladimir.v.koroste...@rambler.ru> wrote: >> >> >>>On Oct 24, 12:58 pm, MikeShepherd...@btinternet.com wrote: >> >>>>>>This is a software problem, not an FPGA problem. >>>>> >>>>>Well, could you give an advice where to start learning how to write a >>>>>driver? >>>>>and how to configure a driver? >> >>>>You're in the wrong newsgroup. >> >>>...and this is why the right direction was asked. But never mind! >> >>If you are using Linux, get "Linux Device Drivers". You can get a free >>pdf of it here: >> >>http://lwn.net/Kernel/LDD3/ >> >>Regards, >> >>John McCaskillwww.fastertechnology.com > > > Thank you for the link. I want to use Linux as an OS running on host. > However, I wonder whether > a system designed using ISE WebPack under Windows will be working with > Linux. > What the Linux book will do is show you how to control custom hardware via the FILE concept that the OS uses. Basically, it will show you how to map the read, write, open, and ioctrl commands to functions to be performed by your hardware. You will still need to get your hardware tied into the PC's bus. This will require a lot of effort and can be done in multiple ways, such as using a PCI bridge device or embedding a PCI interface in your FPGA.Article: 125394
> > Hi, > thanks a lot for reply. I also got idea that it's a great board, > mainly from others. I have just started and have not find any detailed > examples how to move forward learning this. > There are many materials on Xilinx's Web Site but > all these are mainly about advanced > programming and there is almost nothing for beginners. > Hi, I'm very new to VHDL/FPGA myself and also have a S3E (the smaller XC4S500) board. Bought from digilent, it came with no software or manuals (the manuals are all available from xilinx web site though, of course). Not sure if you mean the reference designs at http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm They're certainly quite detailed and complex - I really only looked at the Rotary Encoder example as this gave quite a simple VHDL design to experiment with, plus it showed how to read the Rotary thingamajig. What I _did_ find really useful to look at (besides the web-based tutorials and suchlike that you can find with google), was the FPGA Arcade project http://www.fpgaarcade.com. Both PACMAN and Space Invaders have been ported to the S3E board, and of course full source is provided. I also looked at John Kent's excellent FPGA page at http://members.optushome.com.au/jekent/FPGA.htm - In particular the System09 project interested me: although there's no version specifically for the S3E board, there is an S3 version which (although not close enough to use unmodified) is an interesting insight into VHDL for me. I guess it all depends what exactly you want to do with the FPGA, but perhaps those sites might be useful? Good Luck DTArticle: 125395
On 24 Okt., 14:18, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote: > The Xilinx Spartan-3E can be configured from an Atmel SPI dataflash. > This dataflash can be programmed with a download cable and the impact > tool. > > From what I can find in the tool and docs it is only possible to program > xilinx bitstream files into the dataflash. For my application, I also > want to include the program code for an external CPU in the dataflash. > The CPU will boot from the dataflash, also read the bitstream data from > it and then configure the FPGA, using the slave serial configuration > option. > > Is there a posibility to program arbitrary binary files in a dataflash > with the impact tool and xilinx download cable? > > -- > Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) yes. just use your own tools to prepare the HEX file (MCS) and use it. impact doesnt care what inside the file. I use impact as "general purpose SPI programmer sometimes AnttiArticle: 125396
On Oct 24, 12:12 pm, John McCaskill <jhmccask...@gmail.com> wrote: > On Oct 24, 9:59 am, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > <snip> > embedded OS. The fact that we use Windows to compile the FPGA bit > streams does cause problems with using those bit streams in a Linux > environment. > That should have read: The fact that we use Windows to compile the FPGA bit streams does NOT cause problems with using those bit streams in a Linux environment. Regards, John McCaskill www.fastertechnology.comArticle: 125397
paragon.john@gmail.com wrote: > Hello all, > > Can anyone point me to a good general purpose paper about selecting > appropriate bit-widths for a fixed point implementation of a signal > processing algorithm? I've looked around and haven't found anything > that describes a general methodology to use. I have implemented a > design and it isn't performing as well as I would like. I suspect it > has to do with some poor selection of bit slicing when it comes to > multipiers and accumulators. I don't know any papers. Personally, I do an implementation of an algorithm in Matlab, first with floating point numbers, and then with integers. I can then make quick changes and graph the two implementations to compare the results. That allows me to determine how many bits I need for various portions of the algorithm to get acceptable results. By the way, I tried the Matlab fixed point package, but found that the performance was too poor to use on processing even a modest sized data set, so I stick with using ordinary integers. Typically I stick a comment at the end of most lines indicating the scaling of that particular parameter.Article: 125398
If you have the Spartan-3E Starter Kit, and are interested in using Verilog as your hardware description language, there are a few tutorials and small projects you can try at: http://www.engr.sjsu.edu/crabill/ Eric "DialTone" <DialTone@faked.com> wrote in message news:Xns99D3D2E5CC88Edialtonentlworld@62.253.170.163... >> >> Hi, >> thanks a lot for reply. I also got idea that it's a great board, >> mainly from others. I have just started and have not find any detailed >> examples how to move forward learning this. > > >> There are many materials on Xilinx's Web Site but >> all these are mainly about advanced >> programming and there is almost nothing for beginners. >> > > > Hi, > > I'm very new to VHDL/FPGA myself and also have a S3E (the smaller > XC4S500) board. Bought from digilent, it came with no software or manuals > (the manuals are all available from xilinx web site though, of course). > > Not sure if you mean the reference designs at > http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm > > They're certainly quite detailed and complex - I really only looked at > the Rotary Encoder example as this gave quite a simple VHDL design to > experiment with, plus it showed how to read the Rotary thingamajig. > > What I _did_ find really useful to look at (besides the web-based > tutorials and suchlike that you can find with google), was the FPGA > Arcade project http://www.fpgaarcade.com. Both PACMAN and Space Invaders > have been ported to the S3E board, and of course full source is provided. > I also looked at John Kent's excellent FPGA page at > http://members.optushome.com.au/jekent/FPGA.htm - In particular the > System09 project interested me: although there's no version specifically > for the S3E board, there is an S3 version which (although not close > enough to use unmodified) is an interesting insight into VHDL for me. > > I guess it all depends what exactly you want to do with the FPGA, but > perhaps those sites might be useful? > > Good Luck > DTArticle: 125399
On Wed, 24 Oct 2007 11:29:29 -0700, Peter Alfke <peter@xilinx.com> wrote: >Jonathan, why so aggressive? Ooh, I can be much more aggressive than that! And it certainly wasn't directed at you. >I was just pointing out that certain applications naturally perform >sufficient refresh operations in their normal addressing sequence. I >can't see why this is "completely ridiculuous"... Nor is it; the absurdity comes from bending the addressing so that only a small part of each row is sequentially accessed, thereby wasting the massive increase in memory bandwidth that can be achieved for sequential-access applications by using the row buffer as a cache. My spleen was being vented at some designers of old computers (as alluded to by Antti, not you) who used video scan to access every row of DRAM on each video field, thereby unnecessarily burning-up memory bandwidth (which was in short enough supply on such machines) in order to save the trouble of doing refresh properly... -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
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