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> The part was 82S101 not 82F101 - somewhere in a chain of phone calls > the S was turned into an F > > Yes I just saw the QPsemi web site - good site to know about > > Anyone know inexpensive testing equiment for PLA's - there's an > elaborate functional test procedure How many test vectors ? Are you using these for new designs, or maintenance ? We use the EETools device programmers - ChipMAX 2 / TopMAX 2 (Tm2 has some 82S devices, but memories not the PLA, so you would need to pgm on something else, and choose a CPLD with DIp28 Vcc/Gnd mapping ) We've worked with EETools to improve the vector thruput, and total vector size. You can now load 99,999 vectors, and we sent them a 3.5MB test file :) I've never needed quite that much, but figured if it was practical to generate that many vectors, it should also be practical to test to a similar limit. -jgArticle: 125601
Hi Simon, This document may be of assistance: http://www.xilinx.com/bvdocs/appnotes/xapp458.pdf Eric "Simon Heinzle" <sheinzle@inf.ethz.ch> wrote in message news:47261129$1@news1-rz-ap.ethz.ch... > Hi FPGA Group! > > I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM > interface, generated with the Xilinx Memory Interface Generator. The > complete system consists of a PCI interface, an I/O DMA buffer, a burst > module bursting from DMA buffer to the DDR2 DRAM interface. > > What is the best way to define setup/hold times for the I/O pads (UCF)? > (the RAM interface consists of a bi-dir data bus DQ, some output signals > e.g. A and the DRAM clocks CK) > 1. Using the OFFSET = OUT 5 ns AFTER "SYS_CLK_P"? Unfortunately, this does > only work using the Input Clock Pin, but it should probably better be in > reference to the DRAM clocks CK) > 2. Using TIMESPEC "TS_DDR_OUT" = FROM FFS TO "DDR_OUT" 5 ns; ? Is probably > better, but I'm not exactly sure. > > Furthermore, how would you tackle the problem if the timing at the pads > cannot be met? > > Thanks in advance for helpful answers and pointers in the right direction! > > Best regards, > Simon > > >Article: 125602
On Oct 25, 9:57 am, techG <giuliopul...@gmail.com> wrote: > HI, I'm new in FPGA, I have to build a SPI interface (in VHDL) to let > an fpga read and write a flash memory. > The fpga is a Xilinx Spartan3E, while the memory is an ST M25P16 > (serial I/O). > Do you know if is there any built vhdl core to start with? > > Thanks in advance > Giulio You can try www.opencores.org; The SPI core interface is quite simple to code up as well. CheersArticle: 125603
On 29 Okt., 11:48, Antti <Antti.Luk...@googlemail.com> wrote: > On 29 Okt., 11:46, vlsi_freak <clickonjas...@gmail.com> wrote: > > Its is true that FPGA boots its program from an external PROM. > > How external eproms are connected to FPGA. Is there any requirement in > > making PCB with FPGA. > > > 1 yes > 2 read the documentation > 3 yes read the documentation Atti you should be more precise in aswer 1: 1a) Yes (see eg. www.xilinx.com) 1b) No (see eg. www.actel.com) bye ThomasArticle: 125604
Hi, I'd like to ask experts here about ideas to perform a FFT on an arbitrary number of points (for real data). The cores usually found for an FPGA implementation only permit FFTs on a number of points that is a power of 2. In our particular case however, we need to be able to do an FFT on a vector of say, 1025 points. Our current algorithm is to zero-pad this vector to 2048 points. The problem with this approach is that we nearly double the number of points for downstream processing. This is very problematic at high datarates. We have a few ideas but since this seems like a common problem, I'd like to ask people here for tips. Thanks! PatrickArticle: 125605
Hi, I'm looking for some ideas to make an IDE to NAND or NOR flash memory interface. Have you ever heard about something about this (ip, project, chip...) ? Thanks. Franck.Article: 125606
On 30 Okt., 07:08, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > On 29 Okt., 11:48, Antti <Antti.Luk...@googlemail.com> wrote: > > > On 29 Okt., 11:46, vlsi_freak <clickonjas...@gmail.com> wrote: > > > Its is true that FPGA boots its program from an external PROM. > > > How external eproms are connected to FPGA. Is there any requirement in > > > making PCB with FPGA. > > > 1 yes > > 2 read the documentation > > 3 yes read the documentation > > Atti you should be more precise in aswer 1: > 1a) Yes (see eg.www.xilinx.com) > 1b) No (see eg.www.actel.com) > > bye Thomas Hi Thomas you could have been more precise with the spelling too :) I was wondering when somebody makes this remark, you are right 1) is YES/NO YES * Xilinx all except S3AN * Altera all except MAX2 (I think its more a FPGA than CPLD) * Lattice all except XP,XP2,machXO,ispFPGA NO * Actel all * Quicklogic all * Altera MAX2 * Lattice XP,XP2,machXO,ispFPGA * Xilinx S3AN A N T T IArticle: 125607
On 30 Okt., 07:43, Franck <franck.jull...@gmail.com> wrote: > Hi, > > I'm looking for some ideas to make an IDE to NAND or NOR flash memory > interface. Have you ever heard about something about this (ip, > project, chip...) ? > > Thanks. > Franck. make your homework ;) http://www.sst.com/products.xhtml/nand_flash_storage/85/ AnttiArticle: 125608
Hi, Even if you had the source code it could be difficult to see the actual register file since it's implemented using LUTRAMs. The register file is spread out in 64 primitives. I usually just look at the trace signals on MicroBlaze. There are signals for when MicroBlaze is writing a new value to the register file (the value, which register...) There is plenty of information in the trace signals to get a clue on what MicroBlaze is doing. The signals are described in the MicroBlaze reference guide. I use these signals when I simulate and when I debugging in target using ChipScope. Göran Bilski "dartanian" <dartanians@gmail.com> wrote in message news:1193674722.374345.163400@22g2000hsm.googlegroups.com... > Hello fpga community > > I try to compile a testbench in order to observe the waveforms of the > registers of microblaze. The problem is that i cannot see any set of > MicroBlaze register waves (32 assigned mb registers) after the > generation of the waveform screen (compile, simulate, run.. ). > > Initializing a project in EDK, input microblaze and memory type ip's > and trying to input adress values to be inserted from memory into > Microblaze processor. I follow the standard procedure.. compiling, > generating addresses - libraries - netlist, assign drivers, and > heading to simulation through modelsim. Rest of waveforms are there > (sets of mb, opb, lmb, debug, bram...). Can anyone provide me some > help. > > Thank you very much in advance. >Article: 125609
On 8 Oct, 16:19, michel.ta...@gmail.com wrote: > Hi all, > > I'm designing a board based on a virtex5 (XC5VLX50). I'm surprised, I > can't find virtex 5 symbols for using with orcad or kicad. > I only found a post explaining how to create symbol in orcad using ISE > pin file. But it requires Orcad Capture, and I plan tu use kicad > (http://www.lis.inpg.fr/realise_au_lis/kicad/) for schematics, and > only Cadence Allegro, the Orcad router for PCB. > > This is the first time I work with Xilinx, but I know for Altera FPGA, > the Orcad symbol was freely downloadable.. > > So if anyone can help me, or have an interesting link.. > > Thanks by advance, > > Best regards, Michel. I have just created a generic SPARTAN 3e symbol for ORCAD. I decided which sizes of FPGA I want to be able to support for the footprint I want, modified the description of the signals which are different between fpga size ( the different pins are clearly indicated) then imported the csv into orcad. It took me half an hour. How many hundred different variations do you think xilinx should provide? ColinArticle: 125610
Hi foundation 1.5 mapper terminates on windows XP with GPF fault, i wonder if it is caused by incompatibility with winXP or maybe the edif file generated with synplify is somehow bad? or any other recommendations how to create bit file from VHDL for XC3100A FPGA AnttiArticle: 125611
On Oct 29, 7:42 pm, Eric Smith <e...@brouhaha.com> wrote: > Wei Wang <camww...@gmail.com> writes: > > Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems > > that the > > cache memories of the processor are not behaving correctly and I > > have to turn off the caches for application programs > > to run correctly on the processor. Just wondering whether it is > > possible to check whether the processor memories have been mapped > > correctly onto the block rams on FPGA. Thanks, -Wei > > Perhaps if you post the actual project (or put a copy on a web site and > post a URL), some of us can take a look at it and try to help debug > it. Otherwise we don't have very much to go on. > > Eric Eric, I appreciate your willingness to dig further to help, but my question was how I could check the block ram mapping of my design which I thought it was quite generic, and I would expect answers, such as, look at somewhere or look for something in the synthesis log file, or open fpga editor and look for instantiations of primitives. BTW, I suppose most of us in this group do not work for ourselves, only lazy university students would post their entire project and let somebody else do the work for them. Thanks!Article: 125612
Patrick Dubois wrote: > Hi, > > I'd like to ask experts here about ideas to perform a FFT on an > arbitrary number of points (for real data). > > The cores usually found for an FPGA implementation only permit FFTs on > a number of points that is a power of 2. In our particular case > however, we need to be able to do an FFT on a vector of say, 1025 > points. Our current algorithm is to zero-pad this vector to 2048 > points. A fast fourier transmformation has to be done in samples of 2**n. This significantly simplifies the amount of mathematical processing to be done. A discrete fourier transmform can be of any size that you want. The mathematical processing is a lot more complicated. This will take a lot of gates. \why do you need to sample and process different amounts of data? > > The problem with this approach is that we nearly double the number of > points for downstream processing. This is very problematic at high > datarates. > > We have a few ideas but since this seems like a common problem, I'd > like to ask people here for tips. > > Thanks! > > Patrick >Article: 125613
Andrew FPGA wrote: >> . It seems that if we scale the >> results from the quoted paper, a 45nm FPGA will take only a 5x density >> hit (allowing hard macros) compared to a 90nm ASIC. > > I was not sure how gate size scales with silicon area used so I did > not do your calculation - but I certainly did not think 2 process > generations would give a 20x density improvement. Do you not think a > 5x density difference is significant? A 5x density difference is significant but it is less significant than a 20x density difference. (As mk rightly points out, my 5x figure is based on the faulty assumption that the FPGA is 45nm.) The point I was making is that the paper you quoted compares FPGAs and ASICs on the same process, which is often not the choice which a business will be given. Gate density, dynamic power, and clock speed are only some of the considerations a business will look at when choosing their implementation technology. FPGAs have clear advantages over ASICs in some areas, but as you have pointed out ASICs have advantages over FPGAs in others. > Also, they compared the FPGA to a standard cell asic. Presumably with > full custom the difference would be even greater. (and the NRE FPGA > advantage would be even greater too of course.) Yes, you're probably correct here.Article: 125614
On Oct 30, 6:16 am, Wei Wang wrote: > On Oct 29, 7:42 pm, Eric Smith wrote: > > Perhaps if you post the actual project (or put a copy on a web site and > > post a URL), some of us can take a look at it and try to help debug > > it. Otherwise we don't have very much to go on. > > > Eric > <SNIP> > BTW, I suppose most of us in this group do not work for ourselves, only lazy > university students would post their entire project and let somebody > else do the work for them. Thanks! Now, now. Don't be too hasty. That's what we do with Xilinx all the time when their software tools don't work "just right" or you hit that invisible brick wall that only someone with eyes from inside the brick wall can tell you why the wall exists (read: Webcases). So long as what you're working on is not proprietary, the nature of "open source" mindedness is to share with others and gather feedback. That's what posting your MHS file would provide.Article: 125615
If you only need the results at a few frequency points use the "Goertzel algorithm". There are versions of FFT defined for non-power-of-2. These are generally known as "prime factor" algorithms. The Winograd transform is related to these, but all are complicated in control terms, and so are difficult to programm on DSP microprocessors, let alone FPGAs. The power-of-2 FFTs are the most widely used for very good reasons...Article: 125616
On Oct 30, 7:02 am, Andy Botterill <a...@plymouth2.demon.co.uk> wrote: > > A fast fourier transmformation has to be done in samples of 2**n. This > significantly simplifies the amount of mathematical processing to be done. > > A discrete fourier transmform can be of any size that you want. The > mathematical processing is a lot more complicated. This will take a lot > of gates. > > \why do you need to sample and process different amounts of data? Our instrument is a FTS (Fourier Transform Spectrometer). The number of time-domain samples is directly related to the resolution of the instrument. Since we want to give flexibility to the customer, we need to be able to permit a wide range of samples, say 64 to 32k. Our FFT module therefore needs to be flexible. We could limit the number of samples to power of 2s, but this is not very practical. There is quite a large gap between 16k and 32k points. Basically I'm looking for a solution that will let me use the Xilinx FFT core that has a power of 2s limitation, to do FFTs on an arbitrary number of points. One idea is the chirp z-transform algorithm, but I'm not sure yet if it would be suitable for a FPGA implementation. PatrickArticle: 125617
"Eric Smith" <eric@brouhaha.com> wrote in message news:m3pryxlncm.fsf@donnybrook.brouhaha.com... > Wei Wang <camwwang@gmail.com> writes: >> Hello, I implemented an ARM1176JZFS on a Virtex 5 FPGA, but it seems >> that the >> cache memories of the processor are not behaving correctly and I >> have to turn off the caches for application programs >> to run correctly on the processor. Just wondering whether it is >> possible to check whether the processor memories have been mapped >> correctly onto the block rams on FPGA. Thanks, -Wei > > Perhaps if you post the actual project (or put a copy on a web site and > post a URL), some of us can take a look at it and try to help debug > it. Otherwise we don't have very much to go on. > > Eric I am not sure that putting his expensive ARM1176 core on the web would be appreciated by ARM :-) Did you write this core yourself? if not then I am sure you can get some excellent support from ARM to fix this issue, Hans www.ht-lab.comArticle: 125618
By the way, postings to 'comp.dsp' might elicit more useful answers...Article: 125619
Patrick Dubois wrote: > Hi, > > I'd like to ask experts here about ideas to perform a FFT on an > arbitrary number of points (for real data). > > The cores usually found for an FPGA implementation only permit FFTs on > a number of points that is a power of 2. In our particular case > however, we need to be able to do an FFT on a vector of say, 1025 > points. Our current algorithm is to zero-pad this vector to 2048 > points. > > The problem with this approach is that we nearly double the number of > points for downstream processing. This is very problematic at high > datarates. > > We have a few ideas but since this seems like a common problem, I'd > like to ask people here for tips. > > Thanks! > > Patrick I'd suggest that an arbitrary number - selected at runtime rather than by design - isn't practical but designing for 1025 points might be. I forget if it was LeCroy or Tektronix, but about a decade ago I read the whitepaper on their scope's FFT capability. Scopes also have the "limitation" of non-2^n size samples. Rather than decompose their FFT into 2-element butterflies, they decomposed their 2/5/10 multiple waveform samples into 2-element and 5-element FFT nodules. If the idea behind the FFT is to reuse the sin/cos values for a given phase delta, decomposing into a non-2^n system can work well. What obviously won't work well for this approach is any size with large prime numbers. Your 1025 point example calls for 5x5x41 which wouldn't pring so much in acceleration. Sorry I don't have an url for the whitepaper - it's been a decade. - John_HArticle: 125620
On 30 oct, 09:02, "RCIngham" <robert.ing...@gmail.com> wrote: > By the way, postings to 'comp.dsp' might elicit more useful answers... I thought about it but prefered to try c.a.f first to get more FPGA centric solutions. I'll try comp.dsp later if needed :) Thanks, PatrickArticle: 125621
On 30 oct, 09:23, John_H <newsgr...@johnhandwork.com> wrote: > I'd suggest that an arbitrary number - selected at runtime rather than > by design - isn't practical but designing for 1025 points might be. > > I forget if it was LeCroy or Tektronix, but about a decade ago I read > the whitepaper on their scope's FFT capability. Scopes also have the > "limitation" of non-2^n size samples. Rather than decompose their FFT > into 2-element butterflies, they decomposed their 2/5/10 multiple > waveform samples into 2-element and 5-element FFT nodules. If the idea > behind the FFT is to reuse the sin/cos values for a given phase delta, > decomposing into a non-2^n system can work well. What obviously won't > work well for this approach is any size with large prime numbers. > > Your 1025 point example calls for 5x5x41 which wouldn't pring so much in > acceleration. > > Sorry I don't have an url for the whitepaper - it's been a decade. > > - John_H Thanks for the idea. But ideally I'd like to limit myself to power of 2 FFTs so that I can use the Xilinx core. The number of points needs to be flexible from 64 to 32k. Decomposition into smaller chunks seems like a promising avenue. Although if one number is decomposible into two power of 2s (e.g. 8192, which is divisable by 64 and 128), then that number itself will be a power of 2. I'd be quite happy with an algorithm that increases the number of points possible (compared to only power of 2s). Being able to do _every_ possible number of points is probably too strict a requirement. PatrickArticle: 125622
Thanks Eric, I checked the XApp458 and various XApp7** about Virtex 4 DDR2, as we are using a Virtex 4 FX. I'm using the DDR2 controller from the Memory Interface Generator. The main problem are the output delays. Input delays seem to be calibrated using tap delay lines. I had a working example with output delays between 4.4ns and 5.1ns (Data, Address, Control, DRAM clock). I extended that example (but no changes to the DRAM interface), now the output delays range between 4.4 ns (Data, Control, Dram Clock) and 8.9 ns (Address). What is are the best constraints to define a tight window? (I'm now using TIMESPEC ... = FROM FFS TO "OUT" 5.3 ns, which cannot be met) What is a good strategy to meet those timing constraints? Thanks in advance, Simon "Eric Crabill" <eric.crabill@xilinx.com> wrote in message news:fg5qai$nq03@cnn.xilinx.com... > Hi Simon, > > This document may be of assistance: > http://www.xilinx.com/bvdocs/appnotes/xapp458.pdf > > Eric > > "Simon Heinzle" <sheinzle@inf.ethz.ch> wrote in message > news:47261129$1@news1-rz-ap.ethz.ch... >> Hi FPGA Group! >> >> I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM >> interface, generated with the Xilinx Memory Interface Generator. The >> complete system consists of a PCI interface, an I/O DMA buffer, a burst >> module bursting from DMA buffer to the DDR2 DRAM interface. >> >> What is the best way to define setup/hold times for the I/O pads (UCF)? >> (the RAM interface consists of a bi-dir data bus DQ, some output signals >> e.g. A and the DRAM clocks CK) >> 1. Using the OFFSET = OUT 5 ns AFTER "SYS_CLK_P"? Unfortunately, this >> does only work using the Input Clock Pin, but it should probably better >> be in reference to the DRAM clocks CK) >> 2. Using TIMESPEC "TS_DDR_OUT" = FROM FFS TO "DDR_OUT" 5 ns; ? Is >> probably better, but I'm not exactly sure. >> >> Furthermore, how would you tackle the problem if the timing at the pads >> cannot be met? >> >> Thanks in advance for helpful answers and pointers in the right >> direction! >> >> Best regards, >> Simon >> >> >> > >Article: 125623
On Oct 29, 12:15 pm, mk <kal*@dspia.*comdelete> wrote: > On Mon, 29 Oct 2007 17:09:15 +0000, Philip Potter > > <p...@see.sig.invalid> wrote: > >IIRC Xilinx Virtex-5 is on a 45nm process. > > No, Virtex-5 is 65nm. No foundry is selling 45nm production wafers > yet.http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5... No FPGA foundry... Intel is selling 45nm quad core processors now. Historically, processors and FPGAs are leading applications of the latest, smallest geometry sizes (for general purpose logic, as opposed to specific things like memory, etc.). AndyArticle: 125624
Hello all I am looking for references of books about digital design (ASIC & FPGA, high speed, processor, signal processing ... ) What are the books you wouldn't work without ? Thanks in advance Nicolas
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