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Messages from 124975

Article: 124975
Subject: where to download latest systemc libararies?
From: e2point@yahoo.com
Date: Sat, 13 Oct 2007 18:01:04 -0700
Links: << >>  << T >>  << A >>
where to download latest systemc libraries? i checked www.systemc.org,
but there is no link for download.


Article: 124976
Subject: Re: where to download latest systemc libararies?
From: "HT-Lab" <hans64@ht-lab.com>
Date: Sun, 14 Oct 2007 07:39:28 GMT
Links: << >>  << T >>  << A >>

<e2point@yahoo.com> wrote in message 
news:1192323664.794842.33100@z24g2000prh.googlegroups.com...
> where to download latest systemc libraries? i checked www.systemc.org,
> but there is no link for download.
>
You can download 2.2 from:

http://www.systemc.org/downloads/standards/

Hans
www.ht-lab.com



Article: 124977
Subject: Re: FPGA tools under VMware or Parallels on a Mac?
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: Sun, 14 Oct 2007 08:51:48 -0000
Links: << >>  << T >>  << A >>
On Oct 10, 3:17 pm, "Ron N." <rhnlo...@yahoo.com> wrote:
> Which vendor's FPGA  development and USB download tools have
> people found to work reliably on a Mac or MacBook under either the
> Parallels or VMware virtualizers, running Windows XP, 2k or linux?

Quartus II 7.2 Web Ed. in a WinXP Pro SP2 VM on VMware Fusion, running
on a 2 GiB Mac Book Pro works 100% perfect for me.

> If so, which virtualization environments worked with which USB
> FPGA download cables?  How much memory was needed?

USB Blaster worked out of the box for me. I allocated 700 MiB to the
VM but I haven't even tried to see how more or less affects
performance.

There are a lot of benefits to running this in a VM, but the major
drawback I see is that the VM has a non-trivial cpu load (= battery
life) even when just idling. Obviously suspending it solves that.

Tommy


Article: 124978
Subject: Altera devices connecting to DDR memory.
From: pgw <"SwietyMikolaj["@]poczta.onet.pl>
Date: Sun, 14 Oct 2007 14:35:08 +0200
Links: << >>  << T >>  << A >>
Hi

In Cyclone II ep2c5 pinouts document:
http://www.altera.com/literature/dp/cyclone2/ep2c5.pdf
Some pins have additional discription: DQxxx DQSxx DMxx.

DQS signals are assign to this pins because this pins are routed directly
to the clock control block and global clock bus.

But why DQx (data) and DM (data mask) signals are assign to this pins.

Is that requisite assignment or only recommended?
If recommended then why?

This assignment is not comfortable for me but I don't know whether I can
change it.

Thanks for any information.

-- 
PGW

Article: 124979
Subject: Re: Altera devices connecting to DDR memory.
From: Sebastien Bourdeauducq <sebastien.bourdeauducq@gmail.com>
Date: Sun, 14 Oct 2007 06:10:12 -0700
Links: << >>  << T >>  << A >>
Hi,

>From what I've read in the Cyclone II handbook (in the "External
memory interface section"), DQS assignments are required while DM
assignments are only recommended. I think that it allows you to use
some dedicated circuitry that helps to meet the tight DDR timing
requirements.

BTW, do you understand well how each line should be terminated (SSTL-2
signaling) ? I have problems with this. If you are pretty sure of your
electrical schematics, could you send them to sebastien dot
bourdeauducq at gmail dot com ?

And what are the on-chip termination series resistors ? 25 ohm or 50
ohm ?

Regards,

Sebastien


Article: 124980
Subject: Re: Altera devices connecting to DDR memory.
From: pgw <"SwietyMikolaj["@]poczta.onet.pl>
Date: Sun, 14 Oct 2007 15:45:12 +0200
Links: << >>  << T >>  << A >>
Sebastien Bourdeauducq wrote:

> Hi,
> 
>>From what I've read in the Cyclone II handbook (in the "External
> memory interface section"), DQS assignments are required while DM
> assignments are only recommended. I think that it allows you to use
> some dedicated circuitry that helps to meet the tight DDR timing
> requirements.

Thanks for this information.

> BTW, do you understand well how each line should be terminated (SSTL-2
> signaling) ? I have problems with this. If you are pretty sure of your
> electrical schematics, could you send them to sebastien dot
> bourdeauducq at gmail dot com ?
>
> And what are the on-chip termination series resistors ? 25 ohm or 50
> ohm ?
 
I think it should be 25 because 50 is to mach.
But I don't use on-chip termination only external resistors because
"Optimal value ... should be determined by simulations." this quotation is
from: http://www.freescale.com/files/32bit/doc/app_note/AN2582.pdf
(Many helpful informations in this AN)

Secound reasone: "When using on-chip series termination, programmable drive
strength is not available." Cyclone II Handbook.
This AN is also interesting:
http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/DDR_P2P_ApplicationNote20031014.pdf


-- 
PGW

Article: 124981
Subject: Re: Altera devices connecting to DDR memory.
From: pgw <"SwietyMikolaj["@]poczta.onet.pl>
Date: Sun, 14 Oct 2007 15:51:50 +0200
Links: << >>  << T >>  << A >>
Sebastien Bourdeauducq wrote:

> BTW, do you understand well how each line should be terminated (SSTL-2
> signaling) ? I have problems with this. If you are pretty sure of your
> electrical schematics, could you send them to sebastien dot
> bourdeauducq at gmail dot com ?

I forgot. Some schematics you can find in Altera kits documentations
http://www.altera.com/products/devkits/kit-dev_platforms.jsp

Cyclone II Starter Development Kit
Cyclone III Starter FPGA Kit
Nios II Development Kit, Cyclone II Edition (2C35)

-- 
pgw

Article: 124982
Subject: Re: MIG for Linux?
From: pwie42 <paul@sisyphus.teil.cc>
Date: Sun, 14 Oct 2007 07:37:32 -0700
Links: << >>  << T >>  << A >>
hei duane,

i had the same problem a couple of weeks before, but in the end i
booted my winXP image in VMware generated the core and the used the
generated design under linux.

as far as i know you have to have the latest IP upgrade installed,
especially for the DDR controller , but MIG only works under winXP!

i would not recommend to try it with wine, cause if its running under
wine, you still have to install the hole webpack 9,2, and it needs
lots of diskspace.

but anyway i did not get the ddr controller core working, cause the [O|
I]DDR entity's used for data capture produced Xs in the calibration
process and those Xs propagated throw the hole core!
well it was the first time i used to try working with DDR, so it might
be an error or some wrong constraints by me..
i found a thread with people having the same problem, but in german:
http://www.mikrocontroller.net/topic/77320
and here my problem report:
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/d3c251b6a93f24d0/b52bcc700cf58537?lnk=gst&q=ddr#b52bcc700cf58537

if you get it to work please let me know!

mfg
paul


Duane Clark wrote:
> So I thought I would try out this MIG thing I see mentioned
> occasionally, But according to
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?BV_UseBVCookie=yes&getPagePath=25406
>
> Software Requirements
>
> - ISE 9.2.01i
> - Windows XP (32 bit)
>
> So is MIG really windows only?
>
> I currently have ISE 8.2. That same page says:
> - MIG is no longer provided as a separate download, but is now
> incorporated into IP Updates. MIG v1.73 is available through 9.2i IP
> Update 1.
>
> So does anyone know if older versions of MIG are available somewhere (I
> have not been able to find them)? Does it run under Wine maybe? Is it
> worth bothering with (I am specifically interested in a plain DDR
> interface)?


Article: 124983
Subject: Re: MIG for Linux?
From: Duane Clark <junkmail@junkmail.com>
Date: Sun, 14 Oct 2007 17:46:38 GMT
Links: << >>  << T >>  << A >>
pwie42 wrote:
> hei duane,
> 
> i had the same problem a couple of weeks before, but in the end i
> booted my winXP image in VMware generated the core and the used the
> generated design under linux.
> 
> as far as i know you have to have the latest IP upgrade installed,
> especially for the DDR controller , but MIG only works under winXP!

Well... I don't have WinXP (or Vista for that matter) so that is not an 
option for me. Okay, technically I guess I paid for them, but I never 
booted or used them. I am not going to bother with VMware/Windows. I do 
have Win2000 around that I can boot if absolutely necessary.

> i would not recommend to try it with wine, cause if its running under
> wine, you still have to install the hole webpack 9,2, and it needs
> lots of diskspace.

Diskspace is cheap and I have plenty of that, so I might give it a try 
sometime. I found a tool from Xilin called mig007_rel6, which is used 
for DDR designs on V2P (yes I am using V2P devices, and I know the 
current "real" MIG does not support them). I guess this is an early 
incarnation of MIG, though the exact relationship is a bit cryptic. It 
partially works under Wine, but doesn't generate the output files, and 
is prone to hangs. But it seems to work under Win2000, so I guess I'll 
use that for now.

> but anyway i did not get the ddr controller core working, cause the [O|
> I]DDR entity's used for data capture produced Xs in the calibration
> process and those Xs propagated throw the hole core!
> well it was the first time i used to try working with DDR, so it might
> be an error or some wrong constraints by me..
> i found a thread with people having the same problem, but in german:
> http://www.mikrocontroller.net/topic/77320
> and here my problem report:
> http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/d3c251b6a93f24d0/b52bcc700cf58537?lnk=gst&q=ddr#b52bcc700cf58537

Well, it has been a long time since I bothered with simulating a back 
annotated design. I am not sure it is worth the trouble.

I have found the documentation for the design generated by this version 
of mig to be a bit cryptic, and the generated design/testbench doesn't 
seem to work as is, at least not in a functional simulation. I think the 
problem is that without actual LUT/routing delays for the DQS delay 
lines, the simulation won't work, though I am still checking into that.

Article: 124984
Subject: Re: Newbie,the simplest way to program an FPGA at home?
From: Sebastien Bourdeauducq <sebastien.bourdeauducq@gmail.com>
Date: Sun, 14 Oct 2007 18:00:05 -0000
Links: << >>  << T >>  << A >>
Hi,

If you can find the serial configuration devices for your FPGA (try
Mouser and Digikey, they are usually better than Farnell and RS), use
them.

Otherwise, use either a microcontroller or a CPLD. Of course you'll
need development tools for them as well.

Regards,

Sebastien


Article: 124985
Subject: Re: Quartus II Web Edition License - SOPC Builder generation?
From: ghelbig@lycos.com
Date: Sun, 14 Oct 2007 18:06:42 -0000
Links: << >>  << T >>  << A >>
On Oct 13, 1:42 am, Eric <sendt...@removethis.yahoo_andthis.com>
wrote:
> If I have the web edition license, is it still possible to use the SOPC
> builder?
>
> I'm just trying to build one of the projects in the tutorial...
>
> Thanks,
> Eric
>
> ------------------------
> This is the error I get
> ------------------------
>
> Altera SOPC Builder Version 7.00 Build 33
>            Error: Generator program
>                   for module 'cpu_0' did NOT run successfully.
> generator cmd was 'c:/altera/70/quartus//bin/perl/bin/perl
> -Ic:/altera/70/quartus/sopc_builder/bin
> -Ic:/altera/70/quartus/sopc_builder/bin/europa
> -Ic:/altera/70/quartus/sopc_builder/bin/perl_lib -I.
> -IC:/altera/72/ip/nios2_ip/altera_nios2
> -IC:/altera/72/ip/sopc_builder_ip/altera_avalon_pio
> --sopc_lib_path=F:/fpga_stuff/dram_system_sopc+C:/altera/72/ip/pci_express_compiler/lib/sopc_builder+C:/altera/72/ip/ddr3_high_perf/lib/sopc_builder+C:/altera/72/ip/ddr2_high_perf/lib/sopc_builder+C:/altera/72/ip/ddr_high_perf/lib/sopc_builder+C:/altera/72/ip/sopc_builder_ip+C:/altera/72/ip/nios2_ip+C:/altera/72/ip/triple_speed_ethernet/lib/sopc_builder+C:/altera/72/ip/pci_compiler/lib/sopc_builder+C:/altera/72/ip/ddr_ddr2_sdram/lib/sopc_builder+c:/altera/70/quartus/sopc_builder/components
> --generate=1 --verbose=0 --software_only=0
> --module_lib_dir=C:/altera/72/ip/nios2_ip/altera_nios2
> --sopc_quartus_dir=c:/altera/70/quartus/ --projectname=dram_system.quartus'
>
> Error in processing.  System NOT successfully generated.

(serious snippage above)

You are trying to build with a mixture of 7.0 and 7.2 components.

That will NOT work, web-pack or subscription.  At least it never has
for me...

G.


Article: 124986
Subject: Re: MIG for Linux?
From: Duane Clark <junkmail@junkmail.com>
Date: Sun, 14 Oct 2007 11:46:29 -0700
Links: << >>  << T >>  << A >>
Duane Clark wrote:
> ...
> I have found the documentation for the design generated by this version 
> of mig to be a bit cryptic, and the generated design/testbench doesn't 
> seem to work as is, at least not in a functional simulation. I think the 
> problem is that without actual LUT/routing delays for the DQS delay 
> lines, the simulation won't work, though I am still checking into that.

And indeed, adding a small bit of delay to the dqs_delay entity does fix 
the simulation. Since synthesis tools will ignore delays, it is a bit of 
a mystery why this was not already included, and how the simulation 
could possibly have worked without it.

Article: 124987
Subject: R: Newbie,the simplest way to program an FPGA at home?
From: "blisca" <bliscachiocciolinatiscali.it>
Date: Sun, 14 Oct 2007 21:34:34 +0200
Links: << >>  << T >>  << A >>

Sebastien Bourdeauducq <sebastien.bourdeauducq@gmail.com> wrote in message
1192384805.659829.161740@v29g2000prd.googlegroups.com...
> Hi,
>
> If you can find the serial configuration devices for your FPGA (try
> Mouser and Digikey, they are usually better than Farnell and RS), use
> them.
>
> Otherwise, use either a microcontroller or a CPLD. Of course you'll
> need development tools for them as well.
>
> Regards,
>
> Sebastien
many thanks,
i'm oriented to use an  SPI serial EEPROM,it looks that in this way viathe
jtag i will be able to program it,correct?Perhaps it would need a bit of
time more than a parallel device,but it looks much simpler

at home i have
1)a Cyclone Pro  programmer,but the micro i'm using  in this
moment(9s12E64,80 pin )doesn't allows to program an external flash through
the BDM
2)a jtag digilent programming cable
3)some scraped xc95144 xilinx cpld
how could i use it in the bes way possible(or, i must say ,in the more
convenient way possible)?


i would  to know how to program a flash through a generic microcontroller
without passing through BDM or JTAG ports,please,can you suggest me a link?

Thanks once more









Article: 124988
Subject: Re: R: Newbie,the simplest way to program an FPGA at home?
From: Dave Pollum <vze24h5m@verizon.net>
Date: Sun, 14 Oct 2007 15:28:50 -0700
Links: << >>  << T >>  << A >>
On Oct 14, 2:34 pm, "blisca" <bliscachiocciolinatiscali.it> wrote:
> Sebastien Bourdeauducq <sebastien.bourdeaud...@gmail.com> wrote in message
>
> 1192384805.659829.161...@v29g2000prd.googlegroups.com...> Hi,
>
> > If you can find the serial configuration devices for your FPGA (try
> > Mouser and Digikey, they are usually better than Farnell and RS), use
> > them.
>
> > Otherwise, use either a microcontroller or a CPLD. Of course you'll
> > need development tools for them as well.
>
> > Regards,
>
> > Sebastien
>
> many thanks,
> i'm oriented to use an  SPI serial EEPROM,it looks that in this way viathe
> jtag i will be able to program it,correct?Perhaps it would need a bit of
> time more than a parallel device,but it looks much simpler
>
> at home i have
> 1)a Cyclone Pro  programmer,but the micro i'm using  in this
> moment(9s12E64,80 pin )doesn't allows to program an external flash through
> the BDM
> 2)a jtag digilent programming cable
> 3)some scraped xc95144 xilinx cpld
> how could i use it in the bes way possible(or, i must say ,in the more
> convenient way possible)?
>
> i would  to know how to program a flash through a generic microcontroller
> without passing through BDM or JTAG ports,please,can you suggest me a link?
>
> Thanks once more

Since you have the Digilent JTAG cable, you can use Xilinx ISE/iMPACT
to directly program both Xilinx CPLDs and FPGAs, using the JTAG pins
of the chips.
-Dave Pollum


Article: 124989
Subject: Re: Quartus II 7.2 web edition - Linux or not?
From: cs_posting@hotmail.com
Date: Sun, 14 Oct 2007 17:30:46 -0700
Links: << >>  << T >>  << A >>
On Oct 13, 6:31 pm, Tommy Thorn <tommy.th...@gmail.com> wrote:

> Personally I'd care more about having a version that worked under Wine/
> CrossOver than a native Linux port.

Um, why???

If costs were equaly, why would you want to deal with an extra
compatability layer compared to native?

Only reason I can see is if the "native" version actually used some
kind of horrid compatability layer itself.

I can see reasons for running something in a VM (if you don't trust
it), but wine is not a VM...


Article: 124990
Subject: Re: Quartus II 7.2 web edition - Linux or not?
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: Mon, 15 Oct 2007 03:31:59 -0000
Links: << >>  << T >>  << A >>
On Oct 14, 5:30 pm, cs_post...@hotmail.com wrote:
> On Oct 13, 6:31 pm, Tommy Thorn <tommy.th...@gmail.com> wrote:
>
> > Personally I'd care more about having a version that worked under Wine/
> > CrossOver than a native Linux port.
>
> Um, why???

When I wrote that it was because a native Linux would not make a
difference to me when running it on Mac OS. No, I don't expect a
native Mac OS port.

However, now that I've gotten a tad bit further with CrossOver(*) I've
been extremely disappointed to see that CrossOver actually has a even
larger load (~ 30 %) when idle, compared to the ~ 20 % load in a WinXP
VM. Indeed, a Linux VM would be even better as with recent changes to
the kernel the load can get quite load indeed (unfortunately I don't
thave the number, but I _think_ it's way less than 10 %).


> If costs were equaly, why would you want to deal with an extra
> compatability layer compared to native?

Because native to me is Darwin.

Tommy
(*) The trick to get Quartus II running in CrossOver was the remove
jtagserver.exe and jtagconfig.exe. Unfortunately, it crashes as soon
as I try actually _doing_ anything.


Article: 124991
Subject: R: R: Newbie,the simplest way to program an FPGA at home?
From: "blisca" <bliscachiocciolinatiscali.it>
Date: Mon, 15 Oct 2007 07:27:40 +0200
Links: << >>  << T >>  << A >>

----- Original Message -----
From: Dave Pollum <vze24h5m@verizon.net>
Newsgroups: comp.arch.fpga
Sent: Monday, October 15, 2007 12:28 AM
Subject: Re: R: Newbie,the simplest way to program an FPGA at home?


> On Oct 14, 2:34 pm, "blisca" <bliscachiocciolinatiscali.it> wrote:
> > Sebastien Bourdeauducq <sebastien.bourdeaud...@gmail.com> wrote in
message
> >
> > 1192384805.659829.161...@v29g2000prd.googlegroups.com...> Hi,
> >
> > > If you can find the serial configuration devices for your FPGA (try
> > > Mouser and Digikey, they are usually better than Farnell and RS), use
> > > them.
> >
> > > Otherwise, use either a microcontroller or a CPLD. Of course you'll
> > > need development tools for them as well.
> >
> > > Regards,
> >
> > > Sebastien
> >
> > many thanks,
> > i'm oriented to use an  SPI serial EEPROM,it looks that in this way
viathe
> > jtag i will be able to program it,correct?Perhaps it would need a bit of
> > time more than a parallel device,but it looks much simpler
> >
> > at home i have
> > 1)a Cyclone Pro  programmer,but the micro i'm using  in this
> > moment(9s12E64,80 pin )doesn't allows to program an external flash
through
> > the BDM
> > 2)a jtag digilent programming cable
> > 3)some scraped xc95144 xilinx cpld
> > how could i use it in the bes way possible(or, i must say ,in the more
> > convenient way possible)?
> >
> > i would  to know how to program a flash through a generic
microcontroller
> > without passing through BDM or JTAG ports,please,can you suggest me a
link?
> >
> > Thanks once more
>
> Since you have the Digilent JTAG cable, you can use Xilinx ISE/iMPACT
> to directly program both Xilinx CPLDs and FPGAs, using the JTAG pins
> of the chips.



Yes,but  what i want is to have self programming on power-on for the FPGA
thanks anyway




Article: 124992
Subject: FIFO depth
From: vishnuprasanth@gmail.com
Date: Sun, 14 Oct 2007 22:44:06 -0700
Links: << >>  << T >>  << A >>
I have doubt in calculating FIFO depth.
Transmitter is writing 16 bit data with a frequency of 40 KHz.
Receiver is reading 8 bit data with a frequency of 60 KHz.
What is the depth of FIFO I need to use and how I need to calculate
the FIFO depth?


Article: 124993
Subject: Re: FIFO depth
From: backhus <nix@nirgends.xyz>
Date: Mon, 15 Oct 2007 08:22:17 +0200
Links: << >>  << T >>  << A >>
Hi,
Your transmitter is sending 640kbit/s, but your receiver is reading only 
480kbit/s. With a continous operation on both sides your fifo needs to 
be infinite.

Missing data: Are there gaps in the transmitted data stream or some sort 
of handshake?

The average transmitted data has to be below 480kbit/s. It depends on 
the method that is used to reduce the transmitters data rate how to 
calculate the fifo size.

have a nice synthesis
   Eilert

vishnuprasanth@gmail.com schrieb:
> I have doubt in calculating FIFO depth.
> Transmitter is writing 16 bit data with a frequency of 40 KHz.
> Receiver is reading 8 bit data with a frequency of 60 KHz.
> What is the depth of FIFO I need to use and how I need to calculate
> the FIFO depth?
> 

Article: 124994
Subject: Re: R: Newbie,the simplest way to program an FPGA at home?
From: backhus <nix@nirgends.xyz>
Date: Mon, 15 Oct 2007 08:27:52 +0200
Links: << >>  << T >>  << A >>
Hi Blisca
> i'm oriented to use an  SPI serial EEPROM,it looks that in this way viathe
> jtag i will be able to program it,correct?Perhaps it would need a bit of
> time more than a parallel device,but it looks much simpler

If you want to use SPI anyway, why not use SD-cards (or MMC) to store 
the configuration data. You can (re)write these with any PC that has a 
card reader and the small ones come really cheap.
About the implementation look at www.opencores.org. There's a project 
that uses a CPLD for booting FPGAs from Flash-Cards.

have a nice synthesis
    Eilert

Article: 124995
Subject: Re: Newbie,the simplest way to program an FPGA at home?
From: Alan Nishioka <alan@nishioka.com>
Date: Mon, 15 Oct 2007 00:43:49 -0700
Links: << >>  << T >>  << A >>
On Oct 13, 6:14 am, "blisca" <bliscachiocciolinatiscali.it> wrote:
> Hi
> i 'm trying to practice VHDL at home,until today i did some things using
> obsolete Lattice and Xilinx CPLD.
> One year ago i bought a Spartan educational board from  Digilent with a
> programming cable included,so i can program obsolete Virtex FPGAs via JTAG
> and this could be enough for educational purposes.
>
> Now i would like to implement some kind of self programming at power-on,for
> Xilinx Virtex.

1.  The simplest way to program a Xilinx fpga is to hook it up to a
Xilinx configuration prom.  The xc18v01 can be programmed via jtag
which can then program the fpga.  You don't have to write any code
since impact programs the prom.

2.  You might be able to cross connect to the prom on your Spartan
board if it is big enough.

3.  Someone posted to this group about using a couple of gates to
trick an spi eeprom into programming an fpga.  You would still have to
program the spi eeprom somehow, either by using a programmer or
writing one.

Alan Nishioka


Article: 124996
Subject: Re: Quartus II 7.2 web edition - Linux or not?
From: Kees Bakker <spam@altium.nl>
Date: Mon, 15 Oct 2007 11:40:11 +0200
Links: << >>  << T >>  << A >>
Tommy Thorn wrote:
>...
> Personally I'd care more about having a version that worked under Wine/
> CrossOver than a native Linux port.

Wine??? There are very, very few applications that actually work under Wine.
And of those, the majority is of no interest for Linux users, because there
are perfect alternatives which are native Linux.

Wine is - that's my experience anyway - no environment to run Win32 applications
on a Linux PC.

> 
> My $0.0145,

That's roughly 0.01

> Tommy

My 0.013793
--
Kees


Article: 124997
Subject: Re: Newbie,the simplest way to program an FPGA at home?
From: Andrew FPGA <andrew.newsgroup@gmail.com>
Date: Mon, 15 Oct 2007 03:27:30 -0700
Links: << >>  << T >>  << A >>
> i 'm trying to practice VHDL at home,until today i did some things using
> obsolete Lattice and Xilinx CPLD.

Hi there, if you want to learn VHDL why not focus on the VHDL and
forget about getting it working on the FPGA hardware. Download Xilinx
Webpack and Xilinx Modelsim starter edition(free), write some vhdl,
and then simulate it to check you understand. Iterate. You can also
synthesis it with webpack to check out if it gives you the gates and
flops you were expecting. Stick to some sensible design rules and then
the later jump to the FPGA hardware becomes trivial.
-Keep your design synchronous, use as few clocks as possible,
preferably one. (and only use one edge)
-Don't gate the clock
-Register any asynchronous inputs

I suppose that approach is not as much fun as playing around with
actual hardware though.

Cheers
Andrew


Article: 124998
Subject: Re: Quartus II 7.2 web edition - Linux or not?
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Mon, 15 Oct 2007 10:49:27 +0000 (UTC)
Links: << >>  << T >>  << A >>
Kees Bakker <spam@altium.nl> wrote:
> Tommy Thorn wrote:
> >...
> > Personally I'd care more about having a version that worked under Wine/
> > CrossOver than a native Linux port.

> Wine??? There are very, very few applications that actually work under Wine.
> And of those, the majority is of no interest for Linux users, because there
> are perfect alternatives which are native Linux.

> Wine is - that's my experience anyway - no environment to run Win32 
> applications
> on a Linux PC.

If Altera would talk to Codeweaver(and pay a small amount of what they pay
to Mainsoft to Codewaever) , wine could become be a perfect alternative with
minimal effort...

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 124999
Subject: Re: MIG for Linux?
From: "jacobusn@xilinx.com" <naude.jaco@gmail.com>
Date: Mon, 15 Oct 2007 12:09:33 -0000
Links: << >>  << T >>  << A >>
The newest version of MIG will support 32-bit Linux Red Hat Enterprise
4.0. The newest version (2.0) will be in IP Update 2 for ISE 9.2i and
will be released on 10/17/2007.

What device are you targeting?





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