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> [deleted detailed description of what the poster uses] >What tools do you prefer? Why ? Since you appear intent mainly on telling us what you use, I wonder if this is just an introduction for telling us why your choices are better. Few people have experience of several tools which achieve similar results. Perhaps those who teach can offer useful advice, but most of us have a very limited view, as do you, so our "preference" is likely to be explained by "because it's all I've ever used".Article: 126576
psihodelia@googlemail.com wrote: > Mr. Decaluwe, > > you do great work ! > Do not listen any disrespectful troll who has no idea what is MyHDL. > > What is still missed on MyHDL page are clear informative examples and > tutorials. Current domain name is also bad to remember. Menu structure > is also poor. > > Thanks in advance! You did see the examples here - maybe slighly miss-named as cookbook ? http://myhdl.jandecaluwe.com/doku.php/cookbook:intro Jan added fitter reports and mapping results to these examples, and they are quite good. -jgArticle: 126577
Changing the values of the generics will only set up the proper address decoding for your IP core, however it will not automatically instantiate the required amount of registers. If you look at the user_logic.vhd file you will see slv_regX declarations for every register where X goes from 0 to N. You will have to modify this code to include the proper amount of registers as well if you want everything to work properly. Does your IP core need constant access to the values that will be stored in the registers, or could you just throw the values in a BRAM? -Jason On Nov 20, 12:12 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > Yeah, I made extra sure this was happening. Somehow, I've now got it to > read and write up to 64 registers. > > ---Matthew Hicks > > > Matthew Hicks wrote: > > >> I have created a custom peripheral in EDK 9.1/ISE 9.1 that needs to > >> have 100 registers and communicates with the PowerPC CPU via the PLB > >> bus. > > > [snip] > > >> Therefore, I selected 32 registers and tried to change the > >> USER_NUM_CE > >> constant in the top-level module in the > >> created template to 128, as opposed to 32. I have read the PLB IPIF > >> datasheet from Xilinx, which only says that USER_NUM_CE needs to be a > >> power of two, which is why I used 128 versus 100. After > >> implementation, > >> access to any register above 32 leads to a returned value of zero, > >> when > >> it should be non-zero. Any suggestions of what else I need to change > >> in > >> the generated IPIF code to get this working? > > The wizard generates 2 files, the top file and the user logic file. > > Make sure that the constants are set up correctly in both files. > > > --- > > JoeArticle: 126578
Jim Granville wrote: > > You could download the Lattice Mico32, and reality check against that, > as that is open source. > Most FPGAs these days have multiport RAM, so it makes sense to optimise > your architecture to use that - in your case for registers, and maybe > even for micocode storage. > Thank your for your answer: Indeed I use RAMB16_S36 for microcode-storage, the final design will probably need four of them, as the microcode is more than 36 bit wide. The idea from the other posters to change to Virtex FPGAs is currently not an option for me, as I really want to develop for the cheaper Spartan platform, for which a lot of affordable boards are offered - if necessary I will buy a board with the next larger Spartan 3 on it. Greetings, Jürgen -- Jürgen Böhm www.aviduratas.de "At a time when so many scholars in the world are calculating, is it not desirable that some, who can, dream ?" R. ThomArticle: 126579
Jon Elson wrote: > > > Yes, wide adders use a lot of LUTs. Multiplexers use up LUTs too. A > single 4-input LUT could form a single bit of a 2-input mux, wasting one > input. If you need more inputs, then you have to combine several LUTs > to perform one bit's worth of multiplexer. > Currently I have predominantly three (5bit select) x (32bit data size) muxes with 16 alternatives select actually used (I overdimensioned the muxes, as I did not exactly knew before having written the microcode, how many inputs would be necessary). Are these muxes realized by cascaded LUTs, and does your above remark imply, that a 5-stages-deep chain of LUTs (1 stage for every select bit) will be used? Greetings, Jürgen -- Jürgen Böhm www.aviduratas.de "At a time when so many scholars in the world are calculating, is it not desirable that some, who can, dream ?" R. ThomArticle: 126580
Hi all,
I am little confused with naming of different family devices.....In
vertex V which i should consider as number of slices...
for example:
Device utilization summary:
---------------------------
Selected Device : 5vlx30ff324-1
Slice Logic Utilization:
Number of Slice Registers: 407 out of 19200 2%
Number of Slice LUTs: 502 out of 19200 2%
Number used as Logic: 502 out of 19200 2%
Slice Logic Distribution:
Number of Bit Slices used: 787
Number with an unused Flip Flop 380 out of 787 48%
Number with an unused LUT: 285 out of 787 36%
Number of fully used Bit Slices: 122 out of 787 15%
IO Utilization:
Number of IOs: 91
Number of bonded IOBs: 89 out of 220 40%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 32 3%
Selected Device : 3s1500fg320-4
Number of Slices: 397 out of 13312 2%
Number of Slice Flip Flops: 407 out of 26624 1%
Number of 4 input LUTs: 643 out of 26624 2%
Number of IOs: 91
Number of bonded IOBs: 89 out of 221 40%
Number of GCLKs: 1 out of 8 12%
Regards,
faz
Article: 126581Hi, I have been working on a project and get the coding done and tested using Behavioral Simulation. However, I download it into the FPGA(Spartan 3), it wouldn't work. So I went back and discovered that the Post-route Simulation are all wrong. I had not encountered this before. What could be the source of the problem? Or is there specific areas which I could look at? BTW, I am using Xilinx ISE 9.2i. Thank You AndyArticle: 126582
On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect the outputs from possible miswiring to GND or +3.3V or Output-2- Output. Is there any common practice way to accomplish this? I'm considering a 2.2k series resistor array "chip". But maybe there's a more appropiate way? Also what's the reaction of loading the output with say a 300 ohm resistor and specifying 16 mA drive?Article: 126583
On Tue, 27 Nov 2007 23:37:58 -0800 (PST), "andyto@gmail.com" <andyto@gmail.com> wrote: >Hi, > >I have been working on a project and get the coding done and tested >using Behavioral Simulation. However, I download it into the >FPGA(Spartan 3), it wouldn't work. So I went back and discovered that >the Post-route Simulation are all wrong. I had not encountered this >before. What could be the source of the problem? Or is there specific >areas which I could look at? Most probably you're not meeting timing. Does it help if you run the design at a slower speed? It might be easier to check the simulation for lower speed. Check the timing reports. Also make sure that your constraints are setup correctly (all clocks defined, clock relationships defined, false paths added, multi-cycle paths multiply checked).Article: 126584
I gutted the generated user logic portion of code and added my registers, so I have enough. It was the enable signals that weren’t working for the higher numbered registers. In the end, I found that it was easier to work around this issue by doing the address decoding in my own logic. I also found it easier to directly connect my interrupt signal to the output as opposed to passing it to the IPIF block, which never allowed the signal to pass through, even though it was set-up to do so. If I had more time, I would write my own as I found Xilinx's code to be an utterly disappointing and dysfunctional rat's nest. ---Matthew Hicks > Changing the values of the generics will only set up the proper > address decoding for your IP core, however it will not automatically > instantiate the required amount of registers. > > If you look at the user_logic.vhd file you will see slv_regX > declarations for every register where X goes from 0 to N. You will > have to modify this code to include the proper amount of registers as > well if you want everything to work properly. > > Does your IP core need constant access to the values that will be > stored in the registers, or could you just throw the values in a BRAM? > > -Jason > > On Nov 20, 12:12 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > >> Yeah, I made extra sure this was happening. Somehow, I've now got it >> to read and write up to 64 registers. >> >> ---Matthew Hicks >> >>> Matthew Hicks wrote: >>> >>>> I have created a custom peripheral in EDK 9.1/ISE 9.1 that needs to >>>> have 100 registers and communicates with the PowerPC CPU via the >>>> PLB bus. >>>> >>> [snip] >>> >>>> Therefore, I selected 32 registers and tried to change the >>>> USER_NUM_CE >>>> constant in the top-level module in the >>>> created template to 128, as opposed to 32. I have read the PLB >>>> IPIF >>>> datasheet from Xilinx, which only says that USER_NUM_CE needs to be >>>> a >>>> power of two, which is why I used 128 versus 100. After >>>> implementation, >>>> access to any register above 32 leads to a returned value of zero, >>>> when >>>> it should be non-zero. Any suggestions of what else I need to >>>> change >>>> in >>>> the generated IPIF code to get this working? >>> The wizard generates 2 files, the top file and the user logic file. >>> Make sure that the constants are set up correctly in both files. >>> >>> --- >>> JoeArticle: 126585
Make sure you include the path to the signals if there is a heirarchy. ---Matthew Hicks > Hello together, > > in my vhdl design for ISE 9.2 I want to partition the component > instances of the submodules in my toplevel into defined areas of my > fpga ic. > > I have never done this but had seen some examples before, where it > might have worked (e.g. projects with reconfiguration). > > So I adapted my ucf-file accordingly by adding several area group > constraints and assigned an instance for each area group like in this > short example snippet: > > AREA_GROUP "ag1" RANGE = SLICE_X0Y0:SLICE_X50Y50; > INST instance_name_of_first_component_from_toplevel AREA_GROUP = ag1; > AREA_GROUP "ag2" RANGE = SLICE_X51Y0:SLICE_X100Y50; > INST instance_name_of_second_component_from_toplevel AREA_GROUP = ag2; > ... > But now I'm getting an error (while implementation stage - don't know > exactly at the moment). The error message says roughly, that the > instances cannot be found (something like that) and i'm proposed to > delete the relevant constraint to go on. > > I use the label name of the component port map statement in my > toplevel as the instance names inside the ucf. > > Is this wrong or what's the problem? Any suggestions? > > I can't post the exact error message at the moment, but it will be > given later if it's necessary. > > I have read, that it is possible to generate or extract such area > constraints by using the floorplanner. Does anyone know a helpful and > not too sparse tutorial for the floorplanner, especially for my > purpose? > > Thanks a lot. > L. SchreiberArticle: 126586
posedge52@yahoo.com wrote: > On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect > the outputs from possible miswiring to GND or +3.3V or Output-2- > Output. Is there any common practice way to accomplish this? > > I'm considering a 2.2k series resistor array "chip". But maybe there's > a more appropiate way? Depends on your speed, and how rugged you want it. 2K2 would allow a fault to over +/- 24V, and still be OK. You can parallel a cap, with each 2K2, if you need faster edges. > Also what's the reaction of loading the output with say a 300 ohm > resistor and specifying 16 mA drive? If you have the choice, and a lot of drive loads, it can help to avoid change of all drives at the same time. Reduces the ground bounce. -jgArticle: 126587
Wolfgang Grafen wrote:
> First of all, I miss sufficient documentation and really useful examples. A
> large project I think of has some millions gate coded in hundreds of blocks
> designed by five or more hardware designers with several clock domains
> and will finally work. It should be able to efficiently simulate, write
> back synthesis timing information and so on.
>
> I like Python for a long time. Python was not designed for hardware
> design. The ideal language has the most comprehensive syntax and good
> support e.g. for parallel processes. It can be done in Python, but with
> less comprehensive syntax and less simulation performance compared to an
> optimised language.
>
> Of course, this is only my opinion. I promise I will look over MyHDL
> again (did it last half a year ago).
My opinion is quite different :-) but let's discuss this further in the
MyHDL newsgroup if you want to.
Anyway, this implies that MyHDL is likely to disappoint you. Also,
it will probably work better for "agile" hardware design based on
programmable platforms than for the mega-asic projects that
you are describing.
However, I believe those will become out of date long before VHDL does :-)
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 126588So, I should use LOCKED and DO(1) to reset my DCM outside of FPGA, or I can reset DCM inside FPGA using another clock_input. Only these 2 solutions? Maybe I will do it in my next design, I cannot use DCM these time. Anyway, thanks, all of you.Article: 126589
Hello,
I am currently using the DDR2 controler from XILING (under MIG1.72) for a
VIRTEX4.
I am encountering a problem of access speed when I write to the memory.
Each time I access the memory, my project requires that I use different line
and column addresses
(ie. I am writing in different lines and columns each time ).
Example:
first Write access (address) : line 1, column 1
second Write acces (address) : line 2, column 3
Can you indicate me how to use the controler in an optimal way (how can the
delay between the 2 write access be minimized) ?
Should I use the 'PRECHARGE' command ?
Can I use a option in MIG ?.
Please, find below Datasheet generated by MIG Version 1.72
I would be grateful if someone could help me. Thanks in advance
Regards,
Benoît
----------------------------------------------
Datasheet generated by MIG Version 1.72 :
----------------------------------------------
FPGA :
Target Device : xc4vlx60-ff668
Speed Grade : -11
DCI for Data : enabled
DCI for Address and Control: disabled
Interface Parameters :
Frequency : 200
Data Width : 16
Depth : 1
Row Address : 13
Column Address : 10
Bank Address : 2
ECC : ECC Disabled
Other Options :
DCM : enabled
Add Test Bench : disabled
Clocking Type : Direct_clocking
ClockCapableIO(CC) : disabled
Design Parameters :
Mode Register :
Burst Length : 4(010)
Burst Type : sequential(0)
CAS Latency : 3(011)
Mode : normal(0)
DLL Reset : no(0)
Write Recovery : 3(010)
PD Mode : fast exit(0)
Extended Mode Register :
DLL Enable : Enable-Normal(0)
Output Drive Strength : Fullstrength(0)
RTT (nominal) : RTT Disabled(00)
Additive Latency (AL) : 0(000)
OCD Operation : OCD Exit(000)
DQS# Enable : Enable(0)
RDQS Enable : Disable(0)
Outputs : Enable(0)
Memory Configuration : DDR2_SDRAM:Components
Part Number : MT47H32M16XX-5E
**********
I used the default MT47H32M16XX-5E model (included
in Mig), but I use
a ELPIDA EDD5116AFTA (32Mx16) on my board
**********
Article: 126590PAR failed because "unable to find location..." Sounds like I'm out of SLICEL . Reports said SLICEL : 92%,SLICEM 2%, other kind of resources less than 60%. Since there are a lot of SLICEMs left.Can PAR use SLICEM to replace SLICEL ? Are there some attributes I need to set?Article: 126591
Hi, did you notice that you always burst in data. So depending on the burst length you have to increment your column address by 4 or 8 to nor overwrite your recent data. Using long bursts increases your performance because your memory wasts much time when you switch between read and write mode.Article: 126592
On Nov 28, 4:12 pm, mk <kal*@dspia.*comdelete> wrote: > On Tue, 27 Nov 2007 23:37:58 -0800 (PST), "and...@gmail.com" > > <and...@gmail.com> wrote: > >Hi, > > >I have been working on a project and get the coding done and tested > >using Behavioral Simulation. However, I download it into the > >FPGA(Spartan 3), it wouldn't work. So I went back and discovered that > >the Post-route Simulation are all wrong. I had not encountered this > >before. What could be the source of the problem? Or is there specific > >areas which I could look at? > > Most probably you're not meeting timing. Does it help if you run the > design at a slower speed? It might be easier to check the simulation > for lower speed. > Check the timing reports. Also make sure that your constraints are > setup correctly (all clocks defined, clock relationships defined, > false paths added, multi-cycle paths multiply checked). I had actually set to clk to a a very slow one. From the timing reports, I had actually meet all constrains and my design only use a single clock.Article: 126593
Hopefully some of you guys who have gone through this can comment... We're doing our first board with a couple of DDRs and have a query with ground plane coupling when routing the signals out of the FPGA. We're hoping to get away with a 6 layer board so the stack is.. sig1 GND sig2 sig3 PWR sig4 Any signals that're routed from the FPBA ball to sig4 won't have the same good GND return paths to the FPGA that those coming out on sig1/sig2 will have. We're aiming to run the interface at ~2* 120MHz. We don't have any simulation tools so are having to design using best practice. We can place a GND island in on the PWR layer under the FPGA/DDR with plenty of vias stitching it up to the 'real' GND plane, but this will make the PWR routing more difficult. Does this matter, will the difference in GND coupling be a problem? Some of the app notes we've read suggest that the track impedance isn't too much of a problem. Thanks for any pointers, NialArticle: 126594
Hi, I'm trying to add an existing project which successfully synthesized and simulated with ISE 8.2 and Modelsim to an XPS-project. It's verilog / VHDL Mixed, with the top-module being verilog with vhdl and verilog submodules. so I started using the import peripheral wizard, and it is recognizing my .prj file correctly. However I get an error in the HDL Analyzing Step: HDLCompilers:87 - "C:\.....\top_module.v" line 217 Could not find module/primitive 'sub_module' "sub_module" is a vhdl-entity though. An I can't see any message in the log file like "Compiling VHDL Moduel..." Only verilog-messages are appearing. In the HDL Source File Path the VHDL-Files are recognized. Yes, I put the language-droplist to mixed. any hints? TimoArticle: 126595
Not sure if this will help you but the Virtex-5 DDR2 controllers have a feature called Bank Management which improves the management of open banks in your controller. The controller keeps track of whether the bank being accessed already has an open row or not and also decides whether a PRECHARGE command should be issued or not to that bank. When bank management is enabled via the MULTI_BANK_EN parameter, a maximum of four banks/rows can open at any one time. A least recently used (LRU) algorithm is employed to keep the three most recently used banks and to close the least recently used bank when a new bank/row location needs to be accessed. (From MIG UG) This is not going to be added as a feature in Virtex-4 controllers, but you can generate a Virtex-5 controller and implement it on a Virtex-4 device at the cost of a drop in overall performance. But it is likely that it will improve the delay between different writes (if they are issues to a open bank). Just a though, Good luck JacoArticle: 126596
On Wed, 28 Nov 2007 10:06:22 -0000, "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: >Hopefully some of you guys who have gone through this can >comment... I haven't yet, but I'm asking myself the same sort of questions for the same sort of reasons. >We're hoping to get away with a 6 layer board so the stack is.. Just an opinion. While the board may be routable on 6 layers ... check the incremental cost of 8 layers over 6. Sometimes it's 10% or less. That gives you a second ground plane and allows you to improve power distribution. Unless this is a HIGHLY cost-sensitive product, that looks like a good investment to me, given the cost of the time involved in engineering a solution any more closely. - BrianArticle: 126597
On Nov 27, 11:01 pm, Philipp <Patrick.Batema...@gmx.at> wrote: > Alright, at least the multilinx cable is working, so the LED flashes. I > connected the GND, VCC, TDO, TDI, TCK and TMS. Still I cant get a > connection over the serial port which is quite weird. > I used automatic detection but I get the following error blog from > Impact. Is there an issue with the drivers? In addition, I use two DB25 > adapters in order to connect the cable to the board. Shouldnt be an > issue either, is that correct? > > iMPACT Version: H.38 > iMPACT log file started on 2007/11/27 17:22:31 > // *** BATCH CMD : setPreference -pref UserLevel:NOVICE > // *** BATCH CMD : setPreference -pref MessageLevel:DETAILED > // *** BATCH CMD : setPreference -pref ConcurrentMode:FALSE > // *** BATCH CMD : setPreference -pref UseHighz:FALSE > // *** BATCH CMD : setPreference -pref ConfigOnFailure:STOP > // *** BATCH CMD : setPreference -pref StartupCLock:AUTO_CORRECTION > // *** BATCH CMD : setPreference -pref AutoSignature:FALSE > // *** BATCH CMD : setPreference -pref KeepSVF:FALSE > // *** BATCH CMD : setPreference -pref svfUseTime:FALSE > // *** BATCH CMD : setPreference -pref UserLevel:NOVICE > // *** BATCH CMD : setPreference -pref MessageLevel:DETAILED > // *** BATCH CMD : setPreference -pref ConcurrentMode:FALSE > // *** BATCH CMD : setPreference -pref UseHighz:FALSE > // *** BATCH CMD : setPreference -pref ConfigOnFailure:STOP > // *** BATCH CMD : setPreference -pref StartupCLock:AUTO_CORRECTION > // *** BATCH CMD : setPreference -pref AutoSignature:FALSE > // *** BATCH CMD : setPreference -pref KeepSVF:FALSE > // *** BATCH CMD : setPreference -pref svfUseTime:FALSE > GUI --- Boundary-Scan Mode selected > // *** BATCH CMD : setMode -bs > GUI --- Auto connect to cable... > // *** BATCH CMD : setCable -port auto > AutoDetecting cable. Please wait. > CB_PROGRESS_START - Starting Operation. > Connecting to cable (USB Port). > Cable connection failed. > Connecting to cable (Parallel Port - LPT1). > Checking cable driver. > Driver windrvr6.sys version = 8.1.1.0. LPT base address = 0378h. > ECP base address = 0778h. > Cable connection failed. > Connecting to cable (Parallel Port - LPT2). > Checking cable driver. > Driver windrvr6.sys version = 8.1.1.0.Cable connection failed. > Connecting to cable (Parallel Port - LPT3). > Checking cable driver. > Driver windrvr6.sys version = 8.1.1.0.Cable connection failed. > Connecting to cable (Parallel Port - LPT4). > Checking cable driver. > Driver windrvr6.sys version = 8.1.1.0.Cable connection failed. > Connecting to cable (Usb Port - USB21). > Checking cable driver. > File C:\WINDOWS\system32\drivers\xusbdfwu.sys not found. > Driver file not found. Inf file version = 0. > Driver xusbdfwu.sys version: 1017 (2001). > Driver windrvr6.sys version = 8.1.1.0.Cable connection failed. > Connecting to cable (COM1 Port). > Cable connection failed. > Cable connection failed. > Cable connection failed. > Cable connection failed. > CB_PROGRESS_END - End Operation. > Elapsed time = 16 sec. > Cable autodetection failed. > ***** Closing iMPACT program. ***** Philipp, I have some suggestions: 1- Look around for a patch of multilinx on Xilinx website. Although it solved my problem but many of the usb devices (including my mouse) stopped functioning after applying this patch. 2- Try changing the PC-connectivity of multilinx (from USB to serial). Hope this helps. Regards /MHArticle: 126598
I thought 2 uses for a global line, as reset and clock enable, because my application DO require both. By the way, I=B4m not confused about reset. It's not an issue about using the buffer. It does route my signal, whatever it=B4s source it is, to a global buffer (I can see that on FPGA EDITOR) but then, it indeed "jumps" to regular lines after the buffer. So, I thought that might there is someway to force the route through global lines, because be it a clock or not, every signal connects to CLB using a matrix. It could do that for anysignal. Couldn't it? No, but it seems to me that this is imposed by the PAR tool. My point that the clock input for every FF on the FPGA can be any signal on the design, a bad, but possible design pratice. The same for enable and reset. So, the limitation is not on the interconnect matrix, because ALL signals that enter a LUT or FF comes from there. On Nov 27, 10:58 pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Eric Smith wrote: > > austin writes: > >> No, you cannot use global resources for a logic signal in S3. > > > I've heard you say that before, and I don't dispute it, but I'm curious > > as to the reason. How does the S3 "know" whether the signal I've got > > driving a global clock net is actually a clock? Is there a minimum > > frequency for the clock net? I don't see one in the datasheet. > > It's not a case of classifying the input as a "clock", but one of "you > can't get there from here". The global clock nets go to clock pins, if > your destination is something other than a clock pin then it has to > "hop off" and use the regular routing resources to get there. > > Ed McGettigan > -- > Xilinx Inc.Article: 126599
On Nov 28, 1:23 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > Make sure you include the path to the signals if there is a heirarchy. > > ---Matthew Hicks > > > > > Hello together, > > > in my vhdl design for ISE 9.2 I want to partition the component > > instances of the submodules in my toplevel into defined areas of my > > fpga ic. > > > I have never done this but had seen some examples before, where it > > might have worked (e.g. projects with reconfiguration). > > > So I adapted my ucf-file accordingly by adding several area group > > constraints and assigned an instance for each area group like in this > > short example snippet: > > > AREA_GROUP "ag1" RANGE = SLICE_X0Y0:SLICE_X50Y50; > > INST instance_name_of_first_component_from_toplevel AREA_GROUP = ag1; > > AREA_GROUP "ag2" RANGE = SLICE_X51Y0:SLICE_X100Y50; > > INST instance_name_of_second_component_from_toplevel AREA_GROUP = ag2; > > ... > > But now I'm getting an error (while implementation stage - don't know > > exactly at the moment). The error message says roughly, that the > > instances cannot be found (something like that) and i'm proposed to > > delete the relevant constraint to go on. > > > I use the label name of the component port map statement in my > > toplevel as the instance names inside the ucf. > > > Is this wrong or what's the problem? Any suggestions? > > > I can't post the exact error message at the moment, but it will be > > given later if it's necessary. > > > I have read, that it is possible to generate or extract such area > > constraints by using the floorplanner. Does anyone know a helpful and > > not too sparse tutorial for the floorplanner, especially for my > > purpose? > > > Thanks a lot. > > L. Schreiber- Hide quoted text - > > - Show quoted text - Hi, An addendum to Matthew Hicks comment, use "modulename_*" to define area group for all signals if you explode the hierarchy. /MH
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