Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Wed, 21 Nov 2007 12:09:19 +0100, Timo Gerber <timo.g@web.de> wrote: >Hi, >I'm using Xilinx 8.2.03i and I get an Error Xst:528 "Multi-source in >Unit ..." >It's a wire in a submodule and i checked the code: >The signal is an output to module A and an input to module B. >There is no other assignment to this signal. Inside module B the signal >is only on the right-side of any "=" assignments. > >Could there be a bug in Xst when using a design containig both VHDL and >verilog files? If you have Modelsim, this could be another use for the "drivers" command. - BrianArticle: 126426
I'm soldering up my first FPGA design and I'm getting discouraged. I'm using an Altera Cycline with an EPCS1 serial configuration device. I've soldered up the passives and the power supply but the only active part I've put on the board is the configuration PROM. I've connected my ByteBlaster to my board, and it doesn't see the PROM device. I get the error "Unable to scan device chain. Can't scan JTAG chain." Quartus will, however, see the Cyclone device on another (also not-working) board of mine. I've checked and double-checked the connections per Figure 4-2 of the Serial Configuration Devices datasheet, and the continuity tester says it all checks out. I've tried the PROM soldered in both ways, but no success. Are there any magical troubleshooting steps out there I don't know of? It's quite discouraging that I've spent this money to have custom boards made, paid for parts, etc. and find that I can't program the PROM. Thanks in advance for any tips. -MattArticle: 126427
On Nov 21, 10:12 pm, "Nevo" <nev...@hotmail.com> wrote: > I'm soldering up my first FPGA design and I'm getting discouraged. > > I'm using an Altera Cycline with an EPCS1 serial configuration device. I've > soldered up the passives and the power supply but the only active part I've > put on the board is the configuration PROM. > > I've connected my ByteBlaster to my board, and it doesn't see the PROM > device. I get the error "Unable to scan device chain. Can't scan JTAG > chain." Quartus will, however, see the Cyclone device on another (also > not-working) board of mine. > > I've checked and double-checked the connections per Figure 4-2 of the Serial > Configuration Devices datasheet, and the continuity tester says it all > checks out. I've tried the PROM soldered in both ways, but no success. That might be the clue. I don't know the pinout of the PROM device, but they often use power and ground on diagonal pins. If you put it in backwards the first time, it is ruined and turning it around will not help. Figure out which way is right and put a new one on the board. > Are there any magical troubleshooting steps out there I don't know of? It's > quite discouraging that I've spent this money to have custom boards made, > paid for parts, etc. and find that I can't program the PROM. Yes, there are lots of magical steps. But we can't share them or we are banned from the coven.Article: 126428
Nevo wrote: > I'm soldering up my first FPGA design and I'm getting discouraged. > > I'm using an Altera Cyclone with an EPCS1 serial configuration device. I've > soldered up the passives and the power supply but the only active part I've > put on the board is the configuration PROM. > > I've connected my ByteBlaster to my board, and it doesn't see the PROM > device. I get the error "Unable to scan device chain. Can't scan JTAG > chain." Quartus will, however, see the Cyclone device on another (also > not-working) board of mine. > > I've checked and double-checked the connections per Figure 4-2 of the Serial > Configuration Devices datasheet, and the continuity tester says it all > checks out. I've tried the PROM soldered in both ways, but no success. > > Are there any magical troubleshooting steps out there I don't know of? It's > quite discouraging that I've spent this money to have custom boards made, > paid for parts, etc. and find that I can't program the PROM. > > Thanks in advance for any tips. > > -Matt A JTAG chain is usually a "chain" with outputs from one chip feeding inputs of the other. Is your ByteBlaster indeed connected directly to the TDI and TDO pins? If you have the FPGA as part of that chain yet not installed, there's a link missing. Are you aware the board has to be fully powered up to have the JTAG work? The ByteBlaster alone will not make the device (your PROM) come up. It may sound like a silly question but all I know is this is your first FPGA design. - John_HArticle: 126429
In a design, I have to generate several clocks with precisely phase relationship, I'd like to use DCM. But the clock_input is not stable. It could possiblely change frequency, even stop for a while. I dont have input signal to reset DCM. How can I use DCM in this condition? Or, if don't use DCM, how can I chieve precise phase relationship? Thank you!Article: 126430
Problem solved! Thanks for your answers. I dont know exactly what it was, but i must have been something with `define and `ifdef statements in the verilog code... Timo Gerber schrieb: > Hi, > I'm using Xilinx 8.2.03i and I get an Error Xst:528 "Multi-source in > Unit ..." > It's a wire in a submodule and i checked the code: > The signal is an output to module A and an input to module B. > There is no other assignment to this signal. Inside module B the signal > is only on the right-side of any "=" assignments. > > Could there be a bug in Xst when using a design containig both VHDL and > verilog files? > > TimoArticle: 126431
Hi,
I just bougth a card with FPGA "Virtex4 XC4VLX60 668pinBGA -11"
The board is equiped with a DDR2 SDRAM memorie.
FPGA and memory is connected with signals such as DQ[0:15], DQS[0:1],
DQSN[0:1].
I use Xilinx controler (MIG 1.72) in ISE 9.1.03i.
The pinout of this board is :
DDR2_DQS0 => PIN number M21 (IO_L13P_9)
DDR2_DQS0_N => PIN number M2O (IO_L13N_9)
DDR2_DQS1 => PIN number K20 (IO_L5N_9)
DDR2_DQS1_N => PIN number L19 (IO_L5P_9)
I have an error in ISE, because there is an inversion between DQS1 <->
DQS1_N
DDR2_DQS1 should have PIN number L19 (IO_L5P_9)
(When I do this inversion in ucf file, I can route my FPGA)
Please, see below the VHDL code (MIG 1.72).
Can you help me to find a solution to modify the VHDL code, and so get round
the bug pinout of this board
Thanks lot.
Regards,
Benoit.
The VHDL code (MIG 1.72) is :
----------------------------------------------------------------------------
---
-- Device : Virtex-4
-- Design Name : DDR2 Direct Clocking
-- Purpose : This module places the data stobes in the IOBs.
----------------------------------------------------------------------------
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity mem_interface_top_v4_dqs_iob is
port (
CLK : in std_logic;
RESET : in std_logic;
DLYINC : in std_logic;
DLYCE : in std_logic;
DLYRST : in std_logic;
CTRL_DQS_RST : in std_logic;
CTRL_DQS_EN : in std_logic;
DDR_DQS : inout std_logic;
DDR_DQS_L : inout std_logic;
DQS_RISE : out std_logic
);
end entity;
architecture arc_v4_dqs_iob of mem_interface_top_v4_dqs_iob is
signal dqs_in : std_logic;
signal dqs_out : std_logic;
signal dqs_delayed : std_logic;
signal ctrl_dqs_en_r1 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal clk180 : std_logic;
signal data1 : std_logic;
signal DQS_UNUSED : std_logic;
signal RESET_r1 : std_logic;
begin
vcc <= '1';
gnd <= '0';
clk180 <= not CLK;
process(CLK)
begin
if (CLK = '1' and CLK'event) then
RESET_r1 <= RESET;
end if;
end process;
process(clk180)
begin
if clk180'event and clk180 = '1' then
if (CTRL_DQS_RST = '1') then
data1 <= '0';
else
data1 <= '1';
end if;
end if;
end process;
idelay_dqs : IDELAY
generic map(
IOBDELAY_TYPE => "VARIABLE",
IOBDELAY_VALUE => 0
)
port map (
O => dqs_delayed,
I => dqs_in,
C => CLK,
CE => DLYCE,
INC => DLYINC,
RST => DLYRST
);
iddr_dqs : IDDR
generic map(
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
SRTYPE => "SYNC"
)
port map (
Q1 => DQS_RISE,
Q2 => DQS_UNUSED,
C => CLK,
CE => vcc,
D => dqs_delayed,
R => RESET_r1,
S => gnd
);
oddr_dqs : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE",
SRTYPE => "SYNC"
)
port map (
Q => dqs_out,
C => clk180,
CE => vcc,
D1 => data1,
D2 => gnd,
R => gnd,
S => gnd
);
tri_state_dqs : FD
port map (
D => CTRL_DQS_EN,
Q => ctrl_dqs_en_r1,
C => clk180
);
iobuf_dqs : IOBUFDS
port map (
O => dqs_in,
IO => DDR_DQS,
IOB => DDR_DQS_L,
I => dqs_out,
T => ctrl_dqs_en_r1
);
end arc_v4_dqs_iob;
Article: 126432On Nov 21, 11:27 pm, rickman <gnu...@gmail.com> wrote: > On Nov 21, 12:43 pm, G_Abg <Gael.Abgr...@gmail.com> wrote: > > > > > > > On 21 nov, 14:54, rickman <gnu...@gmail.com> wrote: > > > > On Nov 21, 3:30 am, G_Abg <Gael.Abgr...@gmail.com> wrote: > > > > > Hi, > > > > > I have just begin my PhD on SDR and I will have to use a FPGA with > > > > partial dynamic reconfiguration. The system which interest me have a > > > > Xilinx Virtex-4 SX35 integrated on it and I'm not sure this FPGA can > > > > do it. > > > > > If someone could answer me, it'll be great. > > > > I haven't looked at the Virtex-4 devices in detail, but Xilinx has > > > included partial dynamic reconfiguration in their parts for several > > > generations now. The trick is that they don't support this in > > > software... at least very well. PDC sounds good on paper, but seems > > > to be hard to implement and clearly there is not much demand for it. > > > > I'm curious, what is SDR and why are you working on it? > > > SDR is for Software Defined Radio. I'm sorry but I'm not enough good > > in english to explain you what it consists of, I let you find it by > > yourself. (Perhaps one day my english will be sufficient to do that > > ^^) > > It is not an English problem, it is an abbreviation problem. We use > so many of them that they become context dependent jargon that even > people who work in the field don't always know what you are talking > about. > > I am very familiar with SDR, both the generic usage and the version > defined by the US government which is a particular implementation. > > > About why I am working on it, it's very simple, I find this subject > > very interesting and mostly because I think it will open me good job > > opportunities after my PhD. > > > If you want more information about this subject, I could find some > > articles for you. > > Thanks, but I have been up to my ears in the topic. Yes, it should > provide you with good job opportunities over a long span as more and > more SDR related application open up constantly.- Hide quoted text - > > - Show quoted text - Hi I suggest you to perform extensive literature survey and visit mailing list at university of Queensland, Australia. They guys are doing a wonderful work in dynamic reconfiguration. Although Xilinx Jbits tool is rather obsolete now but playing with the tool can give a very good insight to FPGA for reconfiguration and then I would suggest you start working with EDK, PlanAhead and ISE for final application. Best of luck for your research. /MHArticle: 126433
Hi I would like to use the following evaluation board to run my implementation: http://www.alpha-data.com/adm-xrc-ii.html My intention was to use Chipscope in combination with JTAG to download the bitstream to the FPGA and then use Chipscope to analyse whats going on in the chip. Unfortunately the documentation for this card doesnt not say a lot how this can be accomplished. It says that there is a External JTAG connector and it supports Chipscope but I couldnt find any information how this can be done, for instance what additional hardware do I need to connect to the JTAG interface. Anyone made an experience with such a card and could give me some hints? Many thanks, PhilippArticle: 126434
rickman wrote: > On Nov 20, 6:22 pm, <steve.l...@xilinx.com> wrote: >> A substantial amount of work is required for each appication when we >> move away from Wind/U. We have decided not to do that for FPGA >> Editor. Instead, we are creating a new application that is a combination >> of PACE, Floorplanner, FPI, FPE and FPGA Editor. That will be >> available in 11.1 (March 2009). >> >> Steve > > I read that correctly as a year and a half from now, right? That > seems like a loooooong way off. I remember once being told that > supporting partial reconfiguration on the Spartan devices was a few > months off and that Xilinx was committed to it. I don't think that has > ever materialized. How serious is Xilinx about this new tool, PACE? > Anything more committal than just "committed"? > I have to agree, this seems a VERY long way off. The day ISE ran without windu was a real landmark (and a good one too). Unfortunately, starting floorplaner of fpga editor is still a real pain. AndyArticle: 126435
hi fnds, is there any software that converts 'c' program to a 'vhdl' program??Article: 126436
The (better) VMETRO equivalent has the standard .1" header on the PMC and you connect your xilinx cable directly to it. I can't see an equivalent on the photo. JTAG is routed to the PMC connector and you might be at the mercy of the motherboard. Have you tried phoning them? ColinArticle: 126437
On Thu, 22 Nov 2007 03:22:02 -0800 (PST),
dilip <dilip.manu@gmail.com> wrote:
> is there any software that converts
> 'c' program to a 'vhdl' program??
Not without application of brain, no.
Look for information on some relevant products:
Cynthesizer (Forte Design Systems)
Catapult C (Mentor Graphics)
C-synthesis (Celoxica)
CyberWorkBench (NEC)
SystemStudio (Synopsys)
and probably a bunch more I haven't thought of.
To get you started, here's a translation of a well-known
C program into VHDL, achieved without any special software:
use std.textio.all;
entity hello is end;
architecture world of hello is
begin
process
begin
write(output, "Hello World" & CR & LF);
wait;
end process;
end;
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 126438Hi, is it possible to make an input react on a falling edge of an output in a vhdl testbench? i'm using modelsim se 6 and the following statement doesnt work: ... wait on (Ack'event and Ack = '0'); i also tried wait on falling_edge(Ack) is there any way to do this?Article: 126439
colin wrote: > The (better) VMETRO equivalent has the standard .1" header on the PMC > and you connect your xilinx cable directly to it. I can't see an > equivalent on the photo. JTAG is routed to the PMC connector and you > might be at the mercy of the motherboard. > > Have you tried phoning them? I emailed them two days ago, but no answer so far. Still waiting for answer, dont know where this JTAG signal is going to.Article: 126440
On Thu, 22 Nov 2007 13:35:13 +0100, Timo Gerber <timo.g@web.de> wrote:
>Hi,
>is it possible to make an input react on a falling edge of an output in
>a vhdl testbench?
>
>i'm using modelsim se 6 and the following statement doesnt work:
>...
>wait on (Ack'event and Ack = '0');
>
>i also tried
>wait on falling_edge(Ack)
>
>is there any way to do this?
Wrong form of "wait".
You mean
wait until Ack = '0';
"wait on" accepts a list of signals, and is released when
any one of those signals has an event.
"wait until" accepts a Boolean expression. It automatically
creates a "wait on" sensitivity list from all signals that
participate in the expression; whenever one of those signals
changes, it wakes up, tests the expression and releases if
the expression is true. If the expression is false, "wait"
goes back to sleep waiting for the next signal change.
You can also add a timeout using "wait for".
So
wait until Ack = '0';
is automatically re-written by VHDL as
wait on Ack until Ack = '0';
and therefore it's pointless to put the 'event test
into the expression.
You could also (very usefully for a testbench) do
wait until Ack = '0' for 10 us;
and now the wait will time-out if Ack has not gone to
zero within the specified timeout. Of course, this means
that you need to test Ack when you come out of the wait:
wait until Ack = '0' for 10 us;
assert Ack = '0'
report "Timeout failure waiting for Ack='0'"
severity ERROR;
If you provide an explicit "on" sensitivity list, then
the automatic sensitivity list is not created:
wait until Ack = '0' and Ready = '1';
-- wakes up on every event on Ack or Ready
wait on Ack until Ack = '0' and Ready = '1';
-- doesn't wake up on Ready events, but only on Ack events
Finally, note that "wait until" is always edge-triggered. If
the "until" condition is already true when you do the wait,
it will NOT release immediately - it needs at least one
signal transition to be released. So you may need something
like this:
if Ack /= '0' then
wait until Ack = '0';
end if;
if there's a risk that Ack might already be zero before you
hit the wait statement.
hth
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 126441Hi all, I've some trouble designing a virtex 5 board. I use the "Xilinx Virtex 5 LX development kit" schematic ( provided by Avnet ) as model, and the Xilinx App Note "Virtex 5 PCB User guide 203". My problem is about the capacitors required by the FPGA. In the pcb user guide, there is a section wich details the list of required capacitors / slices. Capacitors used are 330uF, 2.2uF, and 220nF. But I was surprised when I look at the "Xilinx Virtex 5 LX development kit" schematic, because only 100uF, 2.2uF, 100nF and a lot of 1nF are used.. there is a lot of differences between the two.. So my question is, what do you think about that ? and what will you advice to me ? Do you think it would be better if I add 1nF capacitors for very high frequencies variations ? Thanks by advance, Best regards, Michel.Article: 126442
Thank you for comment. My 32-bit windows machine has actually 3GB of RAM space. I had no problem to implement the system with EDK. The "memory allocation problem" occurred when I tried to run "Post PAR simulation" in Modelsim. SDF file size is 29MB. The system contains 12 MicroBlaze and totally 125 BRAMs. It seems that 29MB of SDF file and 12 MicroBlazes are too much for Modelsim. If anyone has experience to "simulate (relatively) large system", please let me know.Article: 126443
Aha! I went to bed last night pretty discouraged, but found a ray of hope this morning. It seems there's a power supply issue on my board. I don't think I'm going to be able to solve the programming issue until I solve the power supply issue. Stay tuned... :)Article: 126444
"John_H" <newsgroup@johnhandwork.com> wrote in message news:fL81j.8078$B21.5046@trndny07... > Nevo wrote: >> I'm soldering up my first FPGA design and I'm getting discouraged. >> >> I'm using an Altera Cyclone with an EPCS1 serial configuration device. >> I've soldered up the passives and the power supply but the only active >> part I've put on the board is the configuration PROM. >> >> I've connected my ByteBlaster to my board, and it doesn't see the PROM >> device. I get the error "Unable to scan device chain. Can't scan JTAG >> chain." Quartus will, however, see the Cyclone device on another (also >> not-working) board of mine. >> >> I've checked and double-checked the connections per Figure 4-2 of the >> Serial Configuration Devices datasheet, and the continuity tester says it >> all checks out. I've tried the PROM soldered in both ways, but no >> success. >> >> Are there any magical troubleshooting steps out there I don't know of? >> It's quite discouraging that I've spent this money to have custom boards >> made, paid for parts, etc. and find that I can't program the PROM. >> >> Thanks in advance for any tips. >> >> -Matt > > A JTAG chain is usually a "chain" with outputs from one chip feeding > inputs of the other. Is your ByteBlaster indeed connected directly to the > TDI and TDO pins? If you have the FPGA as part of that chain yet not > installed, there's a link missing. > > Are you aware the board has to be fully powered up to have the JTAG work? > The ByteBlaster alone will not make the device (your PROM) come up. It > may sound like a silly question but all I know is this is your first FPGA > design. > > - John_H There is no chain, just the PROM device. Yes, I am powering the board during the scan. (Thank you, though, for pointing that out!)Article: 126445
Jonathan Bromley schrieb: > Finally, note that "wait until" is always edge-triggered. If > the "until" condition is already true when you do the wait, > it will NOT release immediately - it needs at least one > signal transition to be released. So you may need something > like this: > > if Ack /= '0' then > wait until Ack = '0'; > end if; > > if there's a risk that Ack might already be zero before you > hit the wait statement. > > hth Thanks, your answer helps alot. I want to check the falling edge of an one-clock-cycle pulse. so Ack is low from the beginning...Article: 126446
bhb wrote: > Hi, > > I just bougth a card with FPGA "Virtex4 XC4VLX60 668pinBGA -11" > The board is equiped with a DDR2 SDRAM memorie. > FPGA and memory is connected with signals such as DQ[0:15], DQS[0:1], > DQSN[0:1]. > I use Xilinx controler (MIG 1.72) in ISE 9.1.03i. > > The pinout of this board is : > DDR2_DQS0 => PIN number M21 (IO_L13P_9) > DDR2_DQS0_N => PIN number M2O (IO_L13N_9) > DDR2_DQS1 => PIN number K20 (IO_L5N_9) > DDR2_DQS1_N => PIN number L19 (IO_L5P_9) > > I have an error in ISE, because there is an inversion between DQS1 <-> > DQS1_N > DDR2_DQS1 should have PIN number L19 (IO_L5P_9) > (When I do this inversion in ucf file, I can route my FPGA) > Can you help me to find a solution to modify the VHDL code, and so get round > the bug pinout of this board I don't understand - you have an error in the ucf file, you changed the ucf file, it fixed the problem but you want a different solution so that you don't have the change the ucf file? Your VHDL code directly instantiates the IOB. ISE 'knows' to which pins the IO and IOB outputs of IOBUFDS can connect. Your VHDL connects the DQS pins using vector notation, which is good because it is concise and understandable. If you wanted to change the VHDL, you could instantiate the IOBUFDS of each DQS separately. For the DQS that has the error in the ucf, change the signal names to match the ucf. This will make an inverted DQS output, so be sure to invert that DQS bit somewhere in the DQS generation logic. Check the timing carefully to make sure that the inversion doesn't cause any timing errors. Finally, put in a comment explaining why you made this change. I had a similar problem on a design, except that the PC board had an error and the N FPGA output went to a P SDRAM input; the P FPGA output went to the N SDRAM input. I inverted the signal before the IOB then commented it carefully so that months later I wouldn't wonder why that signal was coded differently than the rest. (It was my job to check to PCB artwork before fab, too.) --- Joe Samson Pixel VelocityArticle: 126447
Okay, just discovered the external JTAG Connector on the board. I just wonder where I could get a suitable parallel or USB cable for that. The pins are as follows: 1) Vcc 2) GND 3) - 4)TCK 5) - 6)TDO 7)TDI 8) 9)TMS Unfortunately I cant make one myself ;) ThanksArticle: 126448
Thank you for comment. I need to change my file.ucf to route the FPGA. So, the information is opposite. DQS0 should have the same information as DQS1 (I use Lower and Upper byte in memory). But with this chnage in ucf, DQS0 = DQS1_N. I changed IOBUFDS for only DQS1, DSQ1_N I invert DQS1 bit in the DQS1 generation logic, but I have no result in the board (the source code was tested in a other DDR2 memory with success). I don't know if the problem is a timing or other. Could you indicate me an example (please find the code in my first mail) to invert DQS1 bit in the DQS1 generation logic. Thanks lot in advance. Best regards, Benoit. "Joseph Samson" <user@not.my.company> a écrit dans le message news: 1th1j.70646$YL5.24511@newssvr29.news.prodigy.net... > bhb wrote: > > Hi, > > > > I just bougth a card with FPGA "Virtex4 XC4VLX60 668pinBGA -11" > > The board is equiped with a DDR2 SDRAM memorie. > > FPGA and memory is connected with signals such as DQ[0:15], DQS[0:1], > > DQSN[0:1]. > > I use Xilinx controler (MIG 1.72) in ISE 9.1.03i. > > > > The pinout of this board is : > > DDR2_DQS0 => PIN number M21 (IO_L13P_9) > > DDR2_DQS0_N => PIN number M2O (IO_L13N_9) > > DDR2_DQS1 => PIN number K20 (IO_L5N_9) > > DDR2_DQS1_N => PIN number L19 (IO_L5P_9) > > > > I have an error in ISE, because there is an inversion between DQS1 <-> > > DQS1_N > > DDR2_DQS1 should have PIN number L19 (IO_L5P_9) > > (When I do this inversion in ucf file, I can route my FPGA) > > Can you help me to find a solution to modify the VHDL code, and so get round > > the bug pinout of this board > > I don't understand - you have an error in the ucf file, you changed the > ucf file, it fixed the problem but you want a different solution so that > you don't have the change the ucf file? > > Your VHDL code directly instantiates the IOB. ISE 'knows' to which pins > the IO and IOB outputs of IOBUFDS can connect. Your VHDL connects the > DQS pins using vector notation, which is good because it is concise and > understandable. If you wanted to change the VHDL, you could instantiate > the IOBUFDS of each DQS separately. For the DQS that has the error in > the ucf, change the signal names to match the ucf. This will make an > inverted DQS output, so be sure to invert that DQS bit somewhere in the > DQS generation logic. Check the timing carefully to make sure that the > inversion doesn't cause any timing errors. Finally, put in a comment > explaining why you made this change. > > I had a similar problem on a design, except that the PC board had an > error and the N FPGA output went to a P SDRAM input; the P FPGA output > went to the N SDRAM input. I inverted the signal before the IOB then > commented it carefully so that months later I wouldn't wonder why that > signal was coded differently than the rest. (It was my job to check to > PCB artwork before fab, too.) > > > --- > Joe Samson > Pixel VelocityArticle: 126449
On Nov 16, 12:15 am, "BobW" <nimby_NEEDS...@roadrunner.com> wrote: > "Brian Drummond" <brian_drumm...@btconnect.com> wrote in message > > news:lrgoj3d81f2jgs5jtd1rc037b9qmugn89v@4ax.com... > > > On Wed, 14 Nov 2007 18:31:15 -0800 (PST), Amit <amit.ko...@gmail.com> > > wrote: > > >>On Nov 12, 8:57 am, Ray Andraka <r...@andraka.com> wrote: > >>Hi Ray, > > >>Thank your response. what is your webiste's domain? > > > I think I'd trywww.andraka.comjust to see what happened... > > > - Brian > > I firmly believe that there needs to be some sort of universally-accepted > occupational guidance test put into place. Here is a candidate for the first > and only question: > > 1 - Find Ray Andraka's website on your own. > > If one fails this test then that person would be forced to look deeply into > a mirror and would be strongly encouraged to consider a more menial > occupation. > > Bob Ok bob.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z