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On Nov 28, 3:03 pm, "and...@gmail.com" <and...@gmail.com> wrote: > On Nov 28, 4:12 pm, mk <kal*@dspia.*comdelete> wrote: > > > > > > > On Tue, 27 Nov 2007 23:37:58 -0800 (PST), "and...@gmail.com" > > > <and...@gmail.com> wrote: > > >Hi, > > > >I have been working on a project and get the coding done and tested > > >using Behavioral Simulation. However, I download it into the > > >FPGA(Spartan 3), it wouldn't work. So I went back and discovered that > > >the Post-route Simulation are all wrong. I had not encountered this > > >before. What could be the source of the problem? Or is there specific > > >areas which I could look at? > > > Most probably you're not meeting timing. Does it help if you run the > > design at a slower speed? It might be easier to check the simulation > > for lower speed. > > Check the timing reports. Also make sure that your constraints are > > setup correctly (all clocks defined, clock relationships defined, > > false paths added, multi-cycle paths multiply checked). > > I had actually set to clk to a a very slow one. From the timing > reports, I had actually meet all constrains and my design only use a > single clock.- Hide quoted text - > > - Show quoted text - Andy, Check pad report as well. /MHArticle: 126601
<andyto@gmail.com> wrote in message news:f8e7c317-1dea-42be-9108-2bab0ef3d6e2@s8g2000prg.googlegroups.com... > On Nov 28, 4:12 pm, mk <kal*@dspia.*comdelete> wrote: >> On Tue, 27 Nov 2007 23:37:58 -0800 (PST), "and...@gmail.com" >> >> <and...@gmail.com> wrote: >> >Hi, >> >> >I have been working on a project and get the coding done and tested >> >using Behavioral Simulation. However, I download it into the >> >FPGA(Spartan 3), it wouldn't work. So I went back and discovered that >> >the Post-route Simulation are all wrong. I had not encountered this >> >before. What could be the source of the problem? Or is there specific >> >areas which I could look at? >> >> Most probably you're not meeting timing. Does it help if you run the >> design at a slower speed? It might be easier to check the simulation >> for lower speed. >> Check the timing reports. Also make sure that your constraints are >> setup correctly (all clocks defined, clock relationships defined, >> false paths added, multi-cycle paths multiply checked). > > I had actually set to clk to a a very slow one. From the timing > reports, I had actually meet all constrains and my design only use a > single clock. Post-route simulations fail for only one reason...timing. - Does your testbench model the FPGA inputs with the proper setup and hold times? 'Proper' meaning it models the real world system which is also failing. - Any asynchronous clocking going on? i.e. The clock input of a flip flop is the output of some other combinatorial logic or a flip flop? A purely synchronous design wouldn't have this approach, since you say you're running at a 'slow' clock speed, I'm guessing that you're violating a hold time requirement (which will happen independent of clock speed). Violating a hold time requirement is darn near impossible in an FPGA with a synchronous design but very easy when you have gated clocks being generated internallly. KJArticle: 126602
On Nov 28, 9:38 am, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > posedg...@yahoo.com wrote: > > On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect > > the outputs from possible miswiring to GND or +3.3V or Output-2- > > Output. Is there any common practice way to accomplish this? > > > I'm considering a 2.2k series resistor array "chip". But maybe there's > > a more appropiate way? > > Depends on your speed, and how rugged you want it. > 2K2 would allow a fault to over +/- 24V, and still be OK. > You can parallel a cap, with each 2K2, if you need faster edges. > > > Also what's the reaction of loading the output with say a 300 ohm > > resistor and specifying 16 mA drive? > > If you have the choice, and a lot of drive loads, it can help to > avoid change of all drives at the same time. Reduces the ground bounce. The other chips is an 10/100Mbps ethernet PHY (25 MHz/40ns). And the concern is shorts to either GND or +3,3V (no 24V).Article: 126603
Rgamer wrote: > I thought 2 uses for a global line, as reset and clock enable, because > my application DO require both. By the way, I´m not confused about > reset. > > It's not an issue about using the buffer. It does route my signal, > whatever it´s source it is, to a global buffer (I can see that on FPGA > EDITOR) but then, it indeed "jumps" to regular lines after the buffer. > So, I thought that might there is someway to force the route through > global lines, because be it a clock or not, every signal connects to > CLB using a matrix. It could do that for anysignal. Couldn't it? > > No, but it seems to me that this is imposed by the PAR tool. My point > that the clock input for every FF on the FPGA can be any signal on the > design, a bad, but possible design pratice. The same for enable and > reset. > So, the limitation is not on the interconnect matrix, because ALL > signals that enter a LUT or FF comes from there. In FPGA Editor, if you click on the interconnect matrix where the global lines feed each CLB, each bubble that connects to a global line - when clicked on - will highlight the paths that connection can feed. They are all clock lines, no reset. If you highlight the bubble connected to the slice clock lines, you'll see where the clock can get its signal. Through the CLB interconnect matrix, the global lines can only feed clocks (at least in families before V5). The limitation IS the interconnection matrix. Why do you believe otherwise?Article: 126604
posedge52@yahoo.com wrote: > On the Spartan-3 with Vcco at 3.3V in LVTTL mode if I want to protect > the outputs from possible miswiring to GND or +3.3V or Output-2- > Output. Is there any common practice way to accomplish this? > > I'm considering a 2.2k series resistor array "chip". But maybe there's > a more appropiate way? > Also what's the reaction of loading the output with say a 300 ohm > resistor and specifying 16 mA drive? Are you designing a board with a production run of three that you'll be assembling with the toaster-oven technique? If you're using a professional assembly house, there is post-assembly testing that will test for shorts. If you have a production run too small for a bed-of-nails tester, there are still flying-lead manufacturing defect analyzers that can check your board for shorts. Why design in "protection" that limits your signal characteristics when all you're protecting from is manufacturing faults? If you were cycling connecting the FPGA in and out of a connector over and over to varying equipment, I could understand some concern. But for soldered-on chips? There are better ways.Article: 126605
Jan Decaluwe schrieb: > Wolfgang Grafen wrote: > >> First of all, I miss sufficient documentation and really useful >> examples. A >> large project I think of has some millions gate coded in hundreds of >> blocks >> designed by five or more hardware designers with several clock domains >> and will finally work. It should be able to efficiently simulate, >> write back synthesis timing information and so on. >> >> I like Python for a long time. Python was not designed for hardware >> design. The ideal language has the most comprehensive syntax and good >> support e.g. for parallel processes. It can be done in Python, but >> with less comprehensive syntax and less simulation performance >> compared to an optimised language. >> >> Of course, this is only my opinion. I promise I will look over MyHDL >> again (did it last half a year ago). > > My opinion is quite different :-) but let's discuss this further in the > MyHDL newsgroup if you want to. No, MyHDL doesn't disappoint me. I will give it another try. I would like to have something Pythonic like MyHDL in my work flow :) > Also, it will probably work better for "agile" hardware design based on > programmable platforms than for the mega-asic projects that > you are describing. The pressure to have a better HDL language is not as high as a better language for verification. I could imagine MyHDL could excel here. AFAIK you can use MyHDL through the Verilog external interface. When I tried MyHDL last VHDL language generation support was just coming. > > Jan WolfgangArticle: 126606
> In FPGA Editor, if you click on the interconnect matrix where the global > lines feed each CLB, each bubble that connects to a global line - when > clicked on - will highlight the paths that connection can feed. They > are all clock lines, no reset. If you highlight the bubble connected to > the slice clock lines, you'll see where the clock can get its signal. > > Through the CLB interconnect matrix, the global lines can only feed > clocks (at least in families before V5). Using global lines for reset should work in Virtex4 as well. Cheers, JimArticle: 126607
Jim Granville schrieb: > psihodelia@googlemail.com wrote: >> Mr. Decaluwe, >> >> you do great work ! >> Do not listen any disrespectful troll who has no idea what is MyHDL. >> >> What is still missed on MyHDL page are clear informative examples and >> tutorials. Current domain name is also bad to remember. Menu structure >> is also poor. >> >> Thanks in advance! > > You did see the examples here - maybe slighly miss-named as cookbook ? > > http://myhdl.jandecaluwe.com/doku.php/cookbook:intro > > Jan added fitter reports and mapping results to these examples, and > they are quite good. > > -jg Yes, I saw it and followed some examples before. Now I remember, I had problems describing and simulating a design composed of several modules. It is only me - I didn't know how to do it and I would like the documentation extended in this way. People who have to decide whether MyHDL will used for a project or not would like to see even more, a proof, e.g. a complete project, multiple clock domains, individual delays on signals (after...ns), asynchronous logic handling come in my mind. The developpers might know MyHDL can do all that, but naturally there is the fear that approaching the top from the bottom a system might fail somewhere inbetween. MyHDLs documentation is becoming better and better. I honour that. Just my 2 cents WolfgangArticle: 126608
Hi I am using Impact and Xilinx Multilinx cable to communicate to my FPGA board. I was able that the connection to the board is established, but somehow I just see a CPLD instead of a Virtex II FPGA board. Anyone an idea how to have access to the FPGA that is hosted on the board? CheersArticle: 126609
Sylvain Munaut <SomeOne@SomeDomain.com> wrote:
> VHDL is a hardware description language. Meaning that you should _not_
> use it to describe what you want the hardware to do. But you should
> use it to describe the hardware you want built. It's up to you to find
> what hardware to build to do what you want it to do ...
Describing wires explicitly is a very popular style
and works well for synthesis. But it is possible for
me to describe procedurally, how a set of registers
are to be updated, like this:
http://home.comcast.net/~mike_treseler/stack.vhd
And leave it to synthesis to work out the wires, like this:
http://home.comcast.net/~mike_treseler/stack.pdf
-- Mike Treseler
Article: 126610On Nov 28, 4:29 am, wxy0...@gmail.com wrote: > PAR failed because "unable to find location..." > > Sounds like I'm out of SLICEL . > > Reports said SLICEL : 92%,SLICEM 2%, other kind of resources less than > 60%. > > Since there are a lot of SLICEMs left.Can PAR use SLICEM to replace > SLICEL ? Are there some attributes I need to set? Normally you would run out of SLICEM not SLICEL because SLICEM has everything in SLICEL plus a lot more. The error must be caused by something else. What does the error message exactly say? Cheers, Jim http://home.comcast.net/%7Ejimwu88/toolsArticle: 126611
Yes, Next time, be sure you have a local oscillator--your life will be far easier. Austin wxy0624@gmail.com wrote: > > So, I should use LOCKED and DO(1) to reset my DCM outside of FPGA, or > I can reset DCM inside FPGA using another clock_input. Only these 2 > solutions? > > Maybe I will do it in my next design, I cannot use DCM these time. > > Anyway, thanks, all of you.Article: 126612
Eric, The global clock network on Virtex, Virtex E, Virtex II, Spartan 3, and Virtex 4, has dedicated IOB locations to get onto the global tree easily, which then goes to a clock switchbox in the center of the die, and then on to the H-tree which then goes to every CLB/IOB/BRAM/DSP/DCM tile's clock input (it goes nowhere else). The switchbox also is able to "see" clock outputs from the DCM tiles which have been connected to drive a global clock resource. So, if you place a logic signal on the global clock resource, it has only one possible destination: the clock inputs of the tiles. In V5 we added the ability of the global signal to "get off" the H-tree at the destination, and re-enter local interconnect. AustinArticle: 126613
~ 2 mA per bank. AustinArticle: 126614
> [deleted detailed description of what the poster uses] >What tools do you prefer? Why ? I use the tools (editor, simulator, synthesis) that my employer's IT department give me to use. They are good enough. Next job the tools may be different, but they will still be good enough, because I am good enough to use them sufficiently well. HTH ;-)Article: 126615
Nial, Get a Signal Integrity Tool. The money you spend on that is recovered by NOT having to respin your pcb and first assembly run ONE TIME. For something that has guaranteed payback, for the cost of a respin in materials alone (does not even include your time, the pcb designer's time, your cost of lost opportunity being late to market...) why do people choose to suffer? Are you a masochist? Do you enjoy pain? Or are you a sadist? Do you enjoy causing pain to others? I suppose if I wanted revenge on a horrible boss, I would just follow their directions, but what is the fun in that? Go work for someone who has a brain. AustinArticle: 126616
<posedge52@yahoo.com> wrote in message news:0795c59c-a408-4ea6-b0a2-e5840a3027b9@d4g2000prg.googlegroups.com... > On Nov 28, 9:38 am, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > > The other chips is an 10/100Mbps ethernet PHY (25 MHz/40ns). > And the concern is shorts to either GND or +3,3V (no 24V). Putting 2.2k series resistors in signals that will be expected to have rise and fall times of one or two nanoseconds is very unlikely to work. Think about it. The time constant of a 2.2k resistor in series with a 5pF input capacitance is 11ns - an order of magnitude higher than your edge rate and almost comparable to the actual cycle time. As others have said, don't waste time designing for possible manufacturing defects and compromising your design in the process. I would argue that the only time you would do this is if a defect could cause major problems such as fire or risk to life, neither of which is likely on a low-voltage, low-power board.Article: 126617
On Nov 26, 1:05 pm, <steve.lass@xilinx.com> wrote: > "rickman" <gnuarm@gmail.com> wrote in message > > news:d1662618-8529-41c6-a716-d83b5fc791ac@w28g2000hsf.googlegroups.com...> On Nov 20, 6:22 pm, <steve.l...@xilinx.com> wrote: > >> A substantial amount of work is required for each appication when we > >> move away from Wind/U. We have decided not to do that for FPGA > >> Editor. Instead, we are creating a new application that is a combination > >> of PACE, Floorplanner, FPI, FPE and FPGA Editor. That will be > >> available in 11.1 (March 2009). > > >> Steve > > > I read that correctly as a year and a half from now, right? > > Yes. We plan to keep FPGA Editor around for a while so if there are > issues, let us know. Hopefully the issue that started this thread is > solved by the answer record provided.> That seems like a loooooong way off. I remember once being told that > > supporting partial reconfiguration on the Spartan devices was a few > > months off and that Xilinx was committed to it. > > I don't remember a commitement on Spartan support. We have it working > internally, but it's a very difficult flow and not something we are > prepared to support. The big difference between Spartan and Virtex is > that Spartan glitches when reconfigured. That means you need to isolate > partial regions including IO, and static routes cannot cross parial > regions. We are commited to Partial Reconfig for Virtex. > > Steve Now I am really confused. I read in another thread here about the partial reconfiguration toolm PlanAhead. When I looked on the web site it lists several Spartan 3 devices as being supported. Are you saying that this page is incorrect? I can't say I am intimate with the limitations of the PlanAhead tool as I have never worked with it or even seen documentation. My application requires the low cost of the Spartan 3 devices and uses partial modular reconfiguration as a way to minimize the number of bit streams. With various hardware modules connected, the combinations of interfaces become huge. In essence, I want to create compatible interface modules within the FPGA that can be combined at run time by a small ARM processor. Initially the processor would query what hardware modules are connected to the FPGA and then load the appropriate interface modules into the FPGA. I'm not clear on your description of "static routes", but if I can't run signals from I/Os through one module to another, the pinouts become very, very constraining. The next time I am building a board that could use PlanAhead, I will take a look, but if Spartan 3 parts are not supported, or are not very usable with PlanAhead, then this does not really solve any of my design problems.Article: 126618
"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in message news:5r4stdF12jom4U1@mid.individual.net... > > We can place a GND island in on the PWR layer under the FPGA/DDR > with plenty of vias stitching it up to the 'real' GND plane, but > this will make the PWR routing more difficult. > > Does this matter, will the difference in GND coupling be a problem? > > > Nial > I would never split a plane except as a last resort (unless you can sandwich it between two solid planes - I often use a four layer GND, split power, split power, GND sandwich in the middle of 16-20 layer boards), because of the issues with traces crossing the split. If you must stick to six layers then you need to make the power plane look like a ground plane by ensuring that there are adequate decoupling capacitors spread uniformly across the board, such that no point on the board is more than some short distance from a capacitor. The AC return current can flow along the power plane and through the capacitor to ground. Of course, you want to reduce the inductance so use 0402 or 0603 parts with vias very close to the pads.Article: 126619
I understood. And thanks for all for the replies. So, I can't use a global line for reset and like all Xilinx guys say, I shouldn't use it. IMHO the lack of reset circuitry is a serious flaw. I have a global enable too, that must get everypart of the design. Again, no way to use it as global. This is even a more serious flaw, since enable is the best design pratice regarding FPGAs. I think I'll have to prey that PAR meet my timing constraints, as they are somewhat tight... Does anyone have a better idea than using low skew lines? Can it be done with any other FPGA that can route a common signal to a global net, without being a clock? I=B4ve read that both Altera and Lattice support reset signals, *maybe* they support other signals too. Regards, On Nov 28, 12:54 pm, Jim Wu <jimwu88NOOOS...@yahoo.com> wrote: > > In FPGA Editor, if you click on the interconnect matrix where the global= > > lines feed each CLB, each bubble that connects to a global line - when > > clicked on - will highlight the paths that connection can feed. They > > are all clock lines, no reset. If you highlight the bubble connected to= > > the slice clock lines, you'll see where the clock can get its signal. > > > Through the CLB interconnect matrix, the global lines can only feed > > clocks (at least in families before V5). > > Using global lines for reset should work in Virtex4 as well. > > Cheers, > JimArticle: 126620
I am not able to load the bit file from the compact flash card to V5. It goes through the system ACE asic. We also have path to load the bit file from Xilinx JTAG connector to V5 - This path works but the one through SystemACE is not working. How to solve this? I am using same bit files in both places. Thanks.Article: 126621
"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote: >Hopefully some of you guys who have gone through this can >comment... > >We're doing our first board with a couple of DDRs and have a >query with ground plane coupling when routing the signals out >of the FPGA. > >We're hoping to get away with a 6 layer board so the stack is.. > >sig1 >GND >sig2 >sig3 >PWR >sig4 > >Any signals that're routed from the FPBA ball to sig4 won't have >the same good GND return paths to the FPGA that those coming out >on sig1/sig2 will have. > >We're aiming to run the interface at ~2* 120MHz. I have designed a similar 4 layer board which runs DDR at 100MHz. As long as the traces between the FPGA and the DDR memory do not cross plane borders, you'll probably be fine. In my design I optimized the connections so I did have at most one via close to the FPGA pin in traces between the FPGA and DDR. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 126622
> Has this been tested with a 512 MiB DIMM? No, these will not work. Only SODIMMs with capacities up to 256Mbyte are supported. regards, ValerijArticle: 126623
Jürgen Böhm wrote: > Hi, > > currently I am designing (as an amateur project) a 32bit Stack > oriented CPU with two stack-pointers (Data Stack/Return Stack) and some > additional registers, that are partly purely auxiliary, partly dedicated > for the intended purpose of the CPU as a specialized Lisp-Processor. > The control is microcoded and the greater part of the microcode is > already written and successfully tested (in simulation with Icarus). > Missing at the moment is parts of the ALU functions and the complete > interrupt/exception logic. > Nevertheless the design (done in Verilog), when synthesized, occupies > already about 1100 slices in a Spartan 3 FPGA, which I feel is a bit > heavy for what seems to me a very simple design. [snip] The synthesized results are really the worst case scenario. Before worrying about a design, take it through mapping; that's where most of the logic optimization and signal trimming happens. We have designs that are over 100% utilized after synthesis that fit just fine after mapping. --- Joe Samson Pixel VelocityArticle: 126624
On Nov 28, 5:06 am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > Hopefully some of you guys who have gone through this can > comment... > > We're doing our first board with a couple of DDRs and have a > query with ground plane coupling when routing the signals out > of the FPGA. > > We're hoping to get away with a 6 layer board so the stack is.. > > sig1 > GND > sig2 > sig3 > PWR > sig4 > Power and ground are not going to be forming a very good capacitor to supply power so you're making a big compromise right there, it won't be a really low inductance pathway to deliver power to the parts on the board. Ideally you'd like to have two more layers, move PWR up to be underneath GND and then mirror that on the bottom side (i.e. sig1, GND, PWR, sig2, sig3, PWR, GND, sig4). Whether your 6 layer bites you or not will depend entirely on how much switching is going on and how demanding the parts are. I recently consulted on a design that had the above type of stackup and the PCB was unable to deliver enough 3.3V to the FPGA and would cause it to functionally upset, the board failed. Adding the planes and putting power adjacent to ground was the biggest impact in the fix, other remedies that were tried to band aid the boards while waiting for the improved stackup design had only marginal impact. > Any signals that're routed from the FPBA ball to sig4 won't have > the same good GND return paths to the FPGA that those coming out > on sig1/sig2 will have. As long as you're not talking about signals having to cross a break in the power plane itself, being adjacent to the cut up power plane is not much different. It all comes down to how much copper is on that plane adjacent to the signal. The electromagnetic field does not care the voltage level on the hunk of metal that it runs into first. > > We're aiming to run the interface at ~2* 120MHz. > Is that 2 DDRs at 120 MHz? Or 240 MHz? > We don't have any simulation tools so are having to design using best > practice. > If you can't spring for si tools, then I'd suggest the following resources that you should peruse in besides just this particular newsgroup 1. "Right the First Time: A Practical Handbook on High Speed PCB Design and System Design". Volumes 1 and 2, by Lee W. Ritchey. Each will set you back about $90USD I think but they are both well worth it. Can be purchased from speedingedge.com (I have no financial or other interest in the book or the Speeding Edge company, this is just a recommendation for what I've found to be an excellent resource). 2. http://www.freelists.org/list/si-list which is a newsgroup dedicated to signal integrity issues. Post your questions up there and you'll get well informed responses from a number of experts. comp.arch.fpga contains some people that know what they're talking about and others that only think they know. In fairness though, this FPGA newsgroup has a different focus that handles issues that run through the whole spectrum of issues related to FPGA design starting from synthesis/simulation tool problems, coding formats, downloading, component packaging and PCB design, etc. > We can place a GND island in on the PWR layer under the FPGA/DDR > with plenty of vias stitching it up to the 'real' GND plane, but > this will make the PWR routing more difficult. > Putting the island in won't help at all. Kevin Jennings
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