Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 127125

Article: 127125
Subject: Re: I try to Tri-Mode Embedded EMAC
From: Jim Wu <jimwu88NOOOSPAM@yahoo.com>
Date: Wed, 12 Dec 2007 07:29:43 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 12, 1:29 am, dream_life_0102 <yosh...@jp.fujitsu.com> wrote:
> hello
>
> I will be trying  to [Tri-Mode Embedded EMAC]  except EDK tool.
>
> Can I implement only  by  ISE 9.1i   tool ?
>
> Does anyone have a sample project?

You can generate one from CoreGen.

Cheers,
Jim
http://home.comcast.net/%7Ejimwu88/tools

Article: 127126
Subject: Re: Poor quality Xilinx boards ? Your experience ?
From: "ereader" <rats@myhouse.com>
Date: Wed, 12 Dec 2007 07:32:45 -0800
Links: << >>  << T >>  << A >>

>> I have seen this with older versions of ISE WebPACK, too. I was able to
>> solve it by reducing the transfer speed. With ISE WebPACK 9.2 I never had
>> this problem, old Digilent boards (Sparten 3 and Spartan 3E) are working
>> fine, too.
>
> I think you hit on the problem "ereader" is having.  I recall playing with 
> the speed for our own production boards in the past.  24 Mb/s may fail, 
> but 12 Mb/s is golden by my recollection.

How do you reduce the speed ?   I don't see any speed selection on the 
boards
or in IMPACT.


> I've had three development boards with no problems on any of them.  I've 
> hauled the one between home and work many times, observing reasonable 
> handling at each location.  The performance has been great.
>
> I respect and appreciate the work Digilent does and look forward to more 
> purchases down the road.

They do offer a good value but their tech support is nonexistent and their 
documentation
is also nonexistent. 



Article: 127127
Subject: Debugging designs that are running on FPGA
From: Paul <Paul@yahoo.co.uk>
Date: Wed, 12 Dec 2007 15:34:58 +0000
Links: << >>  << T >>  << A >>
Hi

I have a simple question. I have a design where the RTL simulation is 
working. Now I would like to see if the design also works then on the 
FPGA. The obvious way would be to use the JTAG interface and see what is 
going on in the CHIP. Anyway, is there somehow another way this could be 
achieved? For example is there somehow a way that a file could be 
written to which I can get them someway access? Or is the JTAG the only 
option I have?

Cheers
Paul

Article: 127128
Subject: Re: Altera ByteBlaster II schematic
From: "koce" <bojan_1981@yahoo.com>
Date: Wed, 12 Dec 2007 09:46:15 -0600
Links: << >>  << T >>  << A >>
Can U, please, send me a byteblasterII schematic file if U have it.
Thank U!
Bojan

--
Message posted using http://www.talkaboutelectronicequipment.com/group/comp.arch.fpga/
More information at http://www.talkaboutelectronicequipment.com/faq.html


Article: 127129
Subject: Newbee Microblaze system BRAM utlization confusion
From: ratemonotonic <niladri1979@gmail.com>
Date: Wed, 12 Dec 2007 07:49:18 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi All ,

I am new to FPGA development and have learned VHDL using text books.
NOW! that doesn't teach practical aspects!
I am extremely confused with the following discovery -

I am using Spartan 3 400k device and it has 16 block rams.
I have configured a microblaze system to use block ram as follows -

1) Local memory - 16 Kbytes
2) OPB Block Ram 1 -   8Kbytes
3) OPB Block Ran  2 -   8Kbytes

That means that it has used up all the block Rams.

Now the confusing part -  I have designed an IP which consumes 15
Block Rams , and when I include the IP in my microblaze system , the
bitstream gets generated! The synthesis report shows that my IP is
using up 15 Block Rams and that microblaze momories are using up 16
Block Rams! That means that the system is using up 31 Block Rams!

How is that Possilbe?

Any help would be greatly appreciated.

BR
Rate

Article: 127130
Subject: Re: Poor quality Xilinx boards ? Your experience ?
From: austin <austin@xilinx.com>
Date: Wed, 12 Dec 2007 07:55:55 -0800
Links: << >>  << T >>  << A >>
ereader,

The boards we have in the lab last for many, many years.  My Digilent
board also still works (going on 3 years).

What are you doing to them?

Electrical discharge testing?

Austin

Article: 127131
Subject: Re: Debugging designs that are running on FPGA
From: Kris Vorwerk <kris.vorwerk@gmail.com>
Date: Wed, 12 Dec 2007 07:58:50 -0800 (PST)
Links: << >>  << T >>  << A >>
> I have a simple question. I have a design where the RTL simulation is
> working. Now I would like to see if the design also works then on the
> FPGA. The obvious way would be to use the JTAG interface and see what is
> going on in the CHIP.

Hmm.  It'd probably be easier for you to pipe the outputs of some
important internal signals or registers to the I/Os of the FPGA (where
you could hook up a logic analyzer, or even attach LEDs if the output
is simple enough to understand).

Of course, this might be hard to do in some designs (since it may
alter your critical path timing), or you may not have any I/Os to
spare.  But this is a pretty easy debugging technique that I've found
to be relatively successful in the past.


K.

Article: 127132
Subject: Re: Poor quality Xilinx boards ? Your experience ?
From: "ereader" <rats@myhouse.com>
Date: Wed, 12 Dec 2007 08:24:55 -0800
Links: << >>  << T >>  << A >>

> The boards we have in the lab last for many, many years.  My Digilent
> board also still works (going on 3 years).
>
> What are you doing to them?
>
> Electrical discharge testing?

I've spent about  $1k  of my own money on these boards so I am as
careful with them as I can be. The boards seem mostly OK. My problems
seem to be with the JTAG cables & connection. I suspect the JTAG header
pins & plugs are low quality & are worn out after some number of use.
Unfortunately I don't have enough test equipment to really debug the problem
and I don't really want to waste my time on it either. My ethernet cables 
are trouble
free and swapping my hard disks regularly hasn't given  me any problems 
either.
So there are cheap cabling solutions that work well. Too bad JTAG cabling & 
maybe
software is not at the same level of reliability. 



Article: 127133
Subject: Re: Poor quality Xilinx boards ? Your experience ?
From: austin <austin@xilinx.com>
Date: Wed, 12 Dec 2007 08:59:17 -0800
Links: << >>  << T >>  << A >>
ereader,

OK, so you are a serious user, and you seem to be having more than your
fair share of problems.

Given the header pins, and socket are gold plated copper, it takes one
hell of a lot of wear to remove the gold, and then, you still have copper.

It would also take a great deal of bending and tugging to crack solder,
bend pins, etc.

In addition to checking on the speed settings of the cable/software, I
would also ask if you have a ground loop.  Is the board also connected
to something else?  Perhaps you are controlling something, or
interfacing with something?  If the two systems share the same ground,
it may be that they are both "grounded" to separate electrical system feeds.

Austin

Article: 127134
Subject: Re: Xilinx RocketIO problems
From: Duane Clark <junkmail@junkmail.com>
Date: Wed, 12 Dec 2007 17:12:05 GMT
Links: << >>  << T >>  << A >>
John Stein wrote:
> Hi.
> I am trying to establish a communication between two RocketIO driven
> Virtex2P FPGAs. I am currently simulating the design running into the
> following problem: When I set the RocketIO Transmitters (Xilinx
> GT_CUSTOM) into parallel loopback mode everything is fine (received data
> = sent data). Whenever I set it into serial loopback mode (or try to
> communicate with another RocketIO receiver) I seem to receive strange
> data (which doesn't seem to be connected to sent data in any way). I am
> completely running out of ideas what I might do wrong, even though I am
> just a starter with RocketIO. An yes, I did read the RocketIO Users
> Guide, but I didn't find it very helpful for my problem.

Are you trying to implement your own protocol? If you are just 
transferring data between the devices, why not use the Aurora protocol? 
It is simple and already debugged, and works quite well.

Article: 127135
Subject: Re: Poor quality Xilinx boards ? Your experience ?
From: John_H <newsgroup@johnhandwork.com>
Date: Wed, 12 Dec 2007 09:13:57 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 12, 7:32 am, "ereader" <r...@myhouse.com> wrote:
<snip>
>
> How do you reduce the speed ?   I don't see any speed selection on the
> boards
> or in IMPACT.
<snip>

Open the Impact tool (I have 9.2.03i).
Go to the Output menu tab.
Select the "Cable Setup..." menu item.
The dialog box that pops up includes a Xilinx USB Cable radio button
and, when selected, has "Max Speed" and "Select Speed" settings
available.

When I choose the "Max Speed" I still end up with my original 6 MHz
setting that I had when I opened Impact.  If your speed is 24 MHz or
you want to try different speeds, go to the "Select Speed" setting
[and press the OK button to get the available speeds] and dial that
speed back.

I've noticed the marginal JTAG chain behavior when I'm in a non-Xilinx
application hooking up through the same Digilent USB connection that
implements the Xilinx USB Cable on the demo board.  In that other
application, 24 MHz is the default and the results on our production
boards are often spotty with the TCLK termination schemes we've used.
Dialing the speed down to 12 MHz or 6 MHz can eliminate the problem.

Good luck getting a stable connection,
- John_H

Article: 127136
Subject: Re: DDS generator with interpolated samples for Spartan3E development board
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Wed, 12 Dec 2007 09:21:40 -0800
Links: << >>  << T >>  << A >>
On Wed, 12 Dec 2007 14:18:51 +0000, Brian Drummond
<brian_drummond@btconnect.com> wrote:

>On Tue, 11 Dec 2007 20:10:53 -0800, John Larkin
><jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:
>
>>On Tue, 11 Dec 2007 08:34:38 +0100, Frank Buss <fb@frank-buss.de>
>>wrote:
>>
>>>John Larkin wrote:
>>>
>>>> At any decent speed, analog issues (noise, nonlinearity, thd, drift,
>>>> crosstalk) overwhelm math accuracy, and at 14 dac bits we're already
>>>> there. At 32 MHz and healthy swings, the thd limit is the output
>>>> amplifiers, with 50-60 dB tough to hit. But most commercial arbs and
>>>> RF signal generators have ghastly thd specs, like -30 or even -20 dBc.
>>>
>>>I want to generate AES3 and S/PDIF as well, which needs 24 bit resolution.
>>>But for the audio signals the frequency needs only below 20kHz, so I think
>>>I can split this: very good 24 bit, but slow generator with direct sine
>>>calculation from fdlibm and DDS table lookup for faster signals.
>>
>>What do you do with 24-bit data? No dac can keep up with that.
>
>Further processing, normally. Audio signals are ideally recorded with
>enough headroom to allow mix, EQ, dynamic range adjustment and other
>processing, without unnecessary compromises in resolution.  
>
>At the consumption end of the chain, 24 bits is a bit unnecessary,
>though there are DACs pushing 20 bits.
>
>- Brian

Oh. Audio. That never makes sense.

John


Article: 127137
Subject: Re: Poor quality Xilinx boards ? Your experience ?
From: "ereader" <rats@myhouse.com>
Date: Wed, 12 Dec 2007 09:22:08 -0800
Links: << >>  << T >>  << A >>
The board is just by itself.  No complicated setup. I am suspicious of the
Digilent jtag cable connector. It's just shrink wrapped header. Probably
a very cheap header. There are many different types of xilinx download
cables from  $12 to $200. That right there suggest the xilinx download
solutions are not well thought out.  Why should such an essential & basic
function have so many variations ?  It should be just plug & go with nothing
to adjust or check.


"austin" <austin@xilinx.com> wrote in message 
news:fjp415$d2u1@cnn.xsj.xilinx.com...
> ereader,
>
> OK, so you are a serious user, and you seem to be having more than your
> fair share of problems.
>
> Given the header pins, and socket are gold plated copper, it takes one
> hell of a lot of wear to remove the gold, and then, you still have copper.
>
> It would also take a great deal of bending and tugging to crack solder,
> bend pins, etc.
>
> In addition to checking on the speed settings of the cable/software, I
> would also ask if you have a ground loop.  Is the board also connected
> to something else?  Perhaps you are controlling something, or
> interfacing with something?  If the two systems share the same ground,
> it may be that they are both "grounded" to separate electrical system 
> feeds.
>
> Austin 



Article: 127138
Subject: Re: Debugging designs that are running on FPGA
From: Duane Clark <junkmail@junkmail.com>
Date: Wed, 12 Dec 2007 17:25:51 GMT
Links: << >>  << T >>  << A >>
Paul wrote:
> Hi
> 
> I have a simple question. I have a design where the RTL simulation is 
> working. Now I would like to see if the design also works then on the 
> FPGA. The obvious way would be to use the JTAG interface and see what is 
> going on in the CHIP. Anyway, is there somehow another way this could be 
> achieved? For example is there somehow a way that a file could be 
> written to which I can get them someway access? Or is the JTAG the only 
> option I have?

What FPGA you are using? What kind of interfaces are already available 
on your design? How much data do you want to capture? How fast?

Typically, I already have some sort of interface that goes to a 
computer, allowing me to capture data to a file. I commonly include some 
debugging circuitry within my designs that allow me to steer 
intermediate data to the output, so that I can verify the operation of 
different stages in the data path.

I kind of infer from the way you phrased the question the you don't want 
to use Chipscope? If that assumption is wrong, and you have a Xilinx 
FPGA, then how about Chipscope? It does exactly what you are asking 
about, though it does use the JTAG port.

Article: 127139
Subject: Re: Poor quality Xilinx boards ? Your experience ?
From: "ereader" <rats@myhouse.com>
Date: Wed, 12 Dec 2007 09:28:29 -0800
Links: << >>  << T >>  << A >>
Thanks for the tip.


"John_H" <newsgroup@johnhandwork.com> wrote in message 
news:aef566b7-cc88-4a54-bf07-6fb2e3fc56ca@a35g2000prf.googlegroups.com...
> On Dec 12, 7:32 am, "ereader" <r...@myhouse.com> wrote:
> <snip>
>>
>> How do you reduce the speed ?   I don't see any speed selection on the
>> boards
>> or in IMPACT.
> <snip>
>
> Open the Impact tool (I have 9.2.03i).
> Go to the Output menu tab.
> Select the "Cable Setup..." menu item.
> The dialog box that pops up includes a Xilinx USB Cable radio button
> and, when selected, has "Max Speed" and "Select Speed" settings
> available.
>
> When I choose the "Max Speed" I still end up with my original 6 MHz
> setting that I had when I opened Impact.  If your speed is 24 MHz or
> you want to try different speeds, go to the "Select Speed" setting
> [and press the OK button to get the available speeds] and dial that
> speed back.
>
> I've noticed the marginal JTAG chain behavior when I'm in a non-Xilinx
> application hooking up through the same Digilent USB connection that
> implements the Xilinx USB Cable on the demo board.  In that other
> application, 24 MHz is the default and the results on our production
> boards are often spotty with the TCLK termination schemes we've used.
> Dialing the speed down to 12 MHz or 6 MHz can eliminate the problem.
>
> Good luck getting a stable connection,
> - John_H 



Article: 127140
Subject: Re: Poor quality Xilinx boards ? Your experience ?
From: austin <austin@xilinx.com>
Date: Wed, 12 Dec 2007 10:06:26 -0800
Links: << >>  << T >>  << A >>
ereader,

Parallel port to JTAG, or USB to JTAG cable from Digilent?

I understand you think these cables are garbage, but the general
consensus on this board is that the hardware is just fine.

The only issues I have heard complaints about are the software drivers
for USB cables from anyone.  Seems the variations of hardware, and
operating systems for supporting USB have added additional headaches.

Austin

Article: 127141
Subject: Re: FPGA Board design basics
From: John_H <newsgroup@johnhandwork.com>
Date: Wed, 12 Dec 2007 10:26:44 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 12, 7:13 am, Poonam <poonam.mur...@gmail.com> wrote:
> Hi,
>
> I have been developing applications in Xilinx FPGAs using VHDL for the
> past 3 years for a small company in Virginia. As our designs are
> getting larger and more complex, the off-the-shelf boards we have been
> using are proving to be insufficient. I am interested in learning
> about designing boards myself with FPGAs, ADCs, DACs etc. I am new to
> board design and am wondering where to start. Any suggestions would be
> greatly appreciated.
>
> Thanks,
> Poonam

Without communicating the level of engineer you are, it's hard to
communicate what it takes to succeed in board design.  Are you even a
hardware engineer?  Do you prototype hardware with flying wires, a
soldering iron, and cheap plastic cases?  Do you know anything about
power regulators, amplifiers, transmission line theory, or PCB
manufacturing issues?

Please tell us a little more about what you bring to the table.

Article: 127142
Subject: Re: Chipscope 7.1 and JTAG TAP
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 12 Dec 2007 10:28:29 -0800
Links: << >>  << T >>  << A >>
Paul wrote:
> Hi
> 
> I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a 
> Instruction width of 6 bits. I have a design for which I had 
> automatically generated a JTAG Controller. I can successfully sythesize 
> the design as well as the JTAG TAP. The problem is just that when I use 
> ChipScope Pro with to connect to the device it tells me that there are 0
> Core units found in the JTAG device chain.
> 
> I have the following options when generating the JTAG TAP Controller:
> 
> Instruction Register Bid Width: 6  (this is what Chipscope pro tells me)
> Version Number: 0
> Pert Number:     0
> Manufacturer:    0
> TDI Signal name: tdi
> TDO Signal name: tdo
> TMS Signal name: tms
> TCK Signal name: tck
> TRST Signal name: trst_n
> 
> I dont think that Version number, Part Number and Manufacturer are 
> critical, right? Anyone an idea what I could have been missing?
> Probably something obvious when running the synthesis with Xilinx XST?
> 
> Many thanks for helpful tips!
> Paul

It sounds like you created your own unique JTAG TAP controller for some
reason and put it in your design and expect that ChipScope would work
with it.  It won't.

ChipScope uses the built in JTAG controller to communicate through the
internal BSCAN block and one of the internal USER ports to a soft ICON
(Integrated CONtroller) core and then to 1-15 ChipScope debug cores
such as ILA (Integrated Logic Analyzer) or VIO (Virtual Input/Output).

I would strongly suggest that you read the introduction chapter in the
ChipScope 7.1i User Guide for a better understanding of using ChipScope.
http://www.xilinx.com/ise/verification/chipscope_pro_sw_cores_7_1i_ug029.pdf

Ed McGettigan
--
Xilinx Inc.

Article: 127143
Subject: Re: FPGA Board design basics
From: Poonam <poonam.murali@gmail.com>
Date: Wed, 12 Dec 2007 10:45:35 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 12, 1:26 pm, John_H <newsgr...@johnhandwork.com> wrote:
> On Dec 12, 7:13 am, Poonam <poonam.mur...@gmail.com> wrote:
>
> > Hi,
>
> > I have been developing applications in Xilinx FPGAs using VHDL for the
> > past 3 years for a small company in Virginia. As our designs are
> > getting larger and more complex, the off-the-shelf boards we have been
> > using are proving to be insufficient. I am interested in learning
> > about designing boards myself with FPGAs, ADCs, DACs etc. I am new to
> > board design and am wondering where to start. Any suggestions would be
> > greatly appreciated.
>
> > Thanks,
> > Poonam
>
> Without communicating the level of engineer you are, it's hard to
> communicate what it takes to succeed in board design.  Are you even a
> hardware engineer?  Do you prototype hardware with flying wires, a
> soldering iron, and cheap plastic cases?  Do you know anything about
> power regulators, amplifiers, transmission line theory, or PCB
> manufacturing issues?
>
> Please tell us a little more about what you bring to the table.

You are right.. I should've mentioned before that I don't have any
hardware experience, but do have some theoretical knowledge about
amplifiers, transmission line theory etc. I am a complete newbie in
PCB design..

Poonam

Article: 127144
Subject: Re: Poor quality Xilinx boards ? Your experience ?
From: "ereader" <rats@myhouse.com>
Date: Wed, 12 Dec 2007 11:34:29 -0800
Links: << >>  << T >>  << A >>
Parallel to JTAG.

I'm glad to hear the positive impressions of digilent cables & boards.
That means maybe it's just a sw problem & I don't have to buy new boards.

"austin" <austin@xilinx.com> wrote in message 
news:fjp7v2$d2e1@cnn.xsj.xilinx.com...
> ereader,
>
> Parallel port to JTAG, or USB to JTAG cable from Digilent?
>
> I understand you think these cables are garbage, but the general
> consensus on this board is that the hardware is just fine.
>
> The only issues I have heard complaints about are the software drivers
> for USB cables from anyone.  Seems the variations of hardware, and
> operating systems for supporting USB have added additional headaches.
>
> Austin 



Article: 127145
Subject: Re: FPGA Board design basics
From: Gabor <gabor@alacron.com>
Date: Wed, 12 Dec 2007 11:39:52 -0800 (PST)
Links: << >>  << T >>  << A >>
On Dec 12, 1:45 pm, Poonam <poonam.mur...@gmail.com> wrote:
> On Dec 12, 1:26 pm, John_H <newsgr...@johnhandwork.com> wrote:
>
>
>
> > On Dec 12, 7:13 am, Poonam <poonam.mur...@gmail.com> wrote:
>
> > > Hi,
>
> > > I have been developing applications in Xilinx FPGAs using VHDL for the
> > > past 3 years for a small company in Virginia. As our designs are
> > > getting larger and more complex, the off-the-shelf boards we have been
> > > using are proving to be insufficient. I am interested in learning
> > > about designing boards myself with FPGAs, ADCs, DACs etc. I am new to
> > > board design and am wondering where to start. Any suggestions would be
> > > greatly appreciated.
>
> > > Thanks,
> > > Poonam
>
> > Without communicating the level of engineer you are, it's hard to
> > communicate what it takes to succeed in board design.  Are you even a
> > hardware engineer?  Do you prototype hardware with flying wires, a
> > soldering iron, and cheap plastic cases?  Do you know anything about
> > power regulators, amplifiers, transmission line theory, or PCB
> > manufacturing issues?
>
> > Please tell us a little more about what you bring to the table.
>
> You are right.. I should've mentioned before that I don't have any
> hardware experience, but do have some theoretical knowledge about
> amplifiers, transmission line theory etc. I am a complete newbie in
> PCB design..
>
> Poonam

Here's some basics on board design for the relatively uninitiated.

1)  Get the eval board schematics for each major part in your design.

2)  Assume all eval boards are overdesigned and try to get a grasp of
the subset of the eval design required for your system.

3)  Don't assume anyone smarter than you has done the mundane parts
of the eval design such as power supplies and bypass caps.  Look at
the recommended bypassing from manufacturer appnotes.  Use the data
sheet values for power consumption where available, or use the power
estimator when using a programmable part.  Some power estimators also
provide estimated bypass cap requirements.

4)  If possible get another engineer to review your schematics.  For
programmable parts like FPGA's make sure you can fit a design with
the pinout assignments in the schematic.  If you don't have the design
already finished, at least set up a project with the appropriate
inputs,
outputs, and IO standards to check for issues like banking or clock
routing.

5) Use a reputable design house to lay out your circuitry.  Don't
assume you can pick up a copy of PADS layout and push the autoroute
button to design a board.

I'm sure there are a lot more items that could be added to this list,
but its a starting point.  You may also find that hiring an outside
design firm to do at least your first design will be worth it in the
long run.  Later designs that are variations on the original will then
have a solid starting point.

Regards,
Gabor

Article: 127146
Subject: Re: FPGA Board design basics
From: John Adair <g1@enterpoint.co.uk>
Date: Wed, 12 Dec 2007 11:42:22 -0800 (PST)
Links: << >>  << T >>  << A >>
Your are entering a very big subject area that most people make the
classic mistake that "it's just drawing lines on the screen". We
entered the manufacturing market 4 years ago with some substantial
practical experience being involved in customer designs but it was
still a very big jump to doing it all yourself. I know, from many
years helping customers out of problems, that our own hit rate in
delivering perfect boards is exceptional. Some our boards are still
effectively in their first revision. Even now after our having design
something like 100 major designs in the last 4 years we still are
learning things about the process and even new tricks. Some companies
that we see actually think they are doing well if they get it right in
3 revisions of a particular board. I have seen some customer designed
projects go to 7+ revisions before they called us in.

That all said it can be a very pleasant task to layout boards somthing
like tacking a jigsaw pauzzle. Whether you find doing boards yourself
good fun, or frustrating and expensive when you make mistakes, you
might want to start doing a simple design on a cheap package like
Eagle and then going through the manufacturing process. Having learned
some of the ropes you can then make better judgements on what tools to
buy and even if the own layout process works for you.

John Adair
Enterpoint Ltd. - Home of CR1 the J1962 solution.



On 12 Dec, 18:45, Poonam <poonam.mur...@gmail.com> wrote:
> On Dec 12, 1:26 pm, John_H <newsgr...@johnhandwork.com> wrote:
>
>
>
>
>
> > On Dec 12, 7:13 am, Poonam <poonam.mur...@gmail.com> wrote:
>
> > > Hi,
>
> > > I have been developing applications in Xilinx FPGAs using VHDL for the
> > > past 3 years for a small company in Virginia. As our designs are
> > > getting larger and more complex, the off-the-shelf boards we have been
> > > using are proving to be insufficient. I am interested in learning
> > > about designing boards myself with FPGAs, ADCs, DACs etc. I am new to
> > > board design and am wondering where to start. Any suggestions would be
> > > greatly appreciated.
>
> > > Thanks,
> > > Poonam
>
> > Without communicating the level of engineer you are, it's hard to
> > communicate what it takes to succeed in board design.  Are you even a
> > hardware engineer?  Do you prototype hardware with flying wires, a
> > soldering iron, and cheap plastic cases?  Do you know anything about
> > power regulators, amplifiers, transmission line theory, or PCB
> > manufacturing issues?
>
> > Please tell us a little more about what you bring to the table.
>
> You are right.. I should've mentioned before that I don't have any
> hardware experience, but do have some theoretical knowledge about
> amplifiers, transmission line theory etc. I am a complete newbie in
> PCB design..
>
> Poonam- Hide quoted text -
>
> - Show quoted text -


Article: 127147
Subject: Re: Xilinx RocketIO problems
From: John Stein <slimepit@fragmasters.net>
Date: Wed, 12 Dec 2007 21:03:34 +0100
Links: << >>  << T >>  << A >>
[RocketIO]

> Are you trying to implement your own protocol? If you are just
> transferring data between the devices, why not use the Aurora protocol?
> It is simple and already debugged, and works quite well.

As a matter of fact, I have to write a conduit for a special application
protocol already established. I do have the source code for that
protocol and I basically followed each step which is done, but had no
success. It seems so strange, that the parallel loopback works, but the
serial does not. As a matter of fact this is my first high speed
protocol experience and as far as I understand the synchronization
(apart from bit alignment) is done by the RocketIO controller. I still
find no explanation why the bits are changed in that drastic matter
(input doesn't seem to match output in any way)
I also had a look at the Aurora protocol, but I am not sure if that is
really going to help me (even though I'm still looking through it).
At this point pretty much every idea is welcome.

John

Article: 127148
Subject: Spartan 3e pin question
From: kislo <kislo02@student.sdu.dk>
Date: Wed, 12 Dec 2007 12:24:50 -0800 (PST)
Links: << >>  << T >>  << A >>
I have a question regarding the T9 pin of the FT256 footprint of the
spartan 3e .. GCLK0 shares pin with the RDWR_B pin which is a
configuration pin whitch according to the datasheet (p.97) has to be
low during configuration .. how is it possible to use GLCK0 as input
for my primary fpga clock source? (im am using SPI for configuration).

Article: 127149
Subject: Re: Debugging designs that are running on FPGA
From: nico@puntnl.niks (Nico Coesel)
Date: Wed, 12 Dec 2007 20:29:55 GMT
Links: << >>  << T >>  << A >>
Paul <Paul@yahoo.co.uk> wrote:

>Hi
>
>I have a simple question. I have a design where the RTL simulation is 
>working. Now I would like to see if the design also works then on the 
>FPGA. The obvious way would be to use the JTAG interface and see what is 
>going on in the CHIP. Anyway, is there somehow another way this could be 
>achieved? For example is there somehow a way that a file could be 
>written to which I can get them someway access? Or is the JTAG the only 
>option I have?

I usually design a debug bus into the fpga which outputs its signals
on a few pins. A mux allows me to select the signals from particular
module inside the FPGA. In this way I can monitor both internal and
external signals using a logic analyser.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search