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On Nov 23, 7:06 pm, wxy0...@gmail.com wrote: > On 11=D4=C223=C8=D5, =C9=CF=CE=E73=CA=B157=B7=D6, hal-use...@ip-64-139-1-6= 9.sjc.megapath.net (Hal > > > > Murray) wrote: > > In article <4b0dadd1-4bdb-4825-ad06-6d8ca2c6d...@i29g2000prf.googlegroup= s.com>, wxy0...@gmail.com writes: > > > >In a design, I have to generate several clocks with precisely phase > > >relationship, I'd like to useDCM. But the clock_input is not stable. > > >It could possiblely change frequency, even stop for a while. I dont > > >have input signal to resetDCM. How can I useDCMin this condition? > > >Or, if don't useDCM, how can I chieve precise phase relationship? > > > What sort of frequency range are you interested in? > > > This isn't "phase" as measured in degrees, but have you > > considered an external delay line? If you pick the delays > > for the fastest frequency the logic should still work when > > the clock slows down. But it might not give you the output > > you want. > > > Have you looked at clock generator chips? Some of them > > have multiple outputs at different speeds. You might get > > lucky and find something that fits you needs. > > > In the old days, the do-it-yourself clock generator was > > a PAL clocked at twice the highest speed you needed. > > (Or a '374 and a few gates.) > > > -- > > These are my opinions, not necessarily my employer's. I hate spam. > > Thank you, Murray > > It's my fault that I didn't make a clear description. > > My whole project is based on a virtex-4 SX55 FPGA, only one > clock_input, frequency up to 300MHz, and may chang to any frequency > slower, but not under my control. So, in FPGA, I have to use some > logic to generate some slower clock in the FPGA to feed internal > logic, which have precisely phase relationship. > > As the clock may change frequency while not even notified, how can I > use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with > given phase relationship without DCM? Can I use the LOCKED signal to > reset DCM? Is it reliable? > > Thanks! So you have an incoming clock that can be any frequency up to 300 MHz, and may also stop completely. Can you run your logic off another, stable oscillator? A DCM is not the only way to reduce the clock rate: You can use a simple binary counter for that. Your question is incomplete. Therefore it is tough to suggest solutions. Peter Alfke, Xilinx ApplicationsArticle: 126476
On 11=D4=C224=C8=D5, =C9=CF=CE=E711=CA=B122=B7=D6, Peter Alfke <al...@sbcglo= bal.net> wrote: > On Nov 23, 7:06 pm, wxy0...@gmail.com wrote: > > > > > > > On 11=D4=C223=C8=D5, =C9=CF=CE=E73=CA=B157=B7=D6, hal-use...@ip-64-139-1= -69.sjc.megapath.net (Hal > > > Murray) wrote: > > > In article <4b0dadd1-4bdb-4825-ad06-6d8ca2c6d...@i29g2000prf.googlegro= ups.com>, wxy0...@gmail.com writes: > > > > >In a design, I have to generate several clocks with precisely phase > > > >relationship, I'd like to useDCM. But the clock_input is not stable. > > > >It could possiblely change frequency, even stop for a while. I dont > > > >have input signal to resetDCM. How can I useDCMin this condition? > > > >Or, if don't useDCM, how can I chieve precise phase relationship? > > > > What sort of frequency range are you interested in? > > > > This isn't "phase" as measured in degrees, but have you > > > considered an external delay line? If you pick the delays > > > for the fastest frequency the logic should still work when > > > the clock slows down. But it might not give you the output > > > you want. > > > > Have you looked at clock generator chips? Some of them > > > have multiple outputs at different speeds. You might get > > > lucky and find something that fits you needs. > > > > In the old days, the do-it-yourself clock generator was > > > a PAL clocked at twice the highest speed you needed. > > > (Or a '374 and a few gates.) > > > > -- > > > These are my opinions, not necessarily my employer's. I hate spam. > > > Thank you, Murray > > > It's my fault that I didn't make a clear description. > > > My whole project is based on a virtex-4 SX55 FPGA, only one > > clock_input, frequency up to 300MHz, and may chang to any frequency > > slower, but not under my control. So, in FPGA, I have to use some > > logic to generate some slower clock in the FPGA to feed internal > > logic, which have precisely phase relationship. > > > As the clock may change frequency while not even notified, how can I > > use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with > > given phase relationship without DCM? Can I use the LOCKED signal to > > reset DCM? Is it reliable? > > > Thanks! > > So you have an incoming clock that can be any frequency up to 300 MHz, > and may also stop completely. > Can you run your logic off another, stable oscillator? > A DCM is not the only way to reduce the clock rate: You can use a > simple binary counter for that. > > Your question is incomplete. Therefore it is tough to suggest > solutions. > Peter Alfke, Xilinx Applications- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7= =D6 - > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - Hi, Peter First, I don't have any other oscillators. Second, as I know, it is tough to achieve phase relationship using binary counters. Phase relationship can change dramticly while frequency changs.Do you have any suggestions? Third,can I use LOCKED signal to reset DCM? Is it reliable? ThanksArticle: 126477
On Nov 23, 7:44 pm, wxy0...@gmail.com wrote: > On 11=D4=C224=C8=D5, =C9=CF=CE=E711=CA=B122=B7=D6, Peter Alfke <al...@sbcg= lobal.net> wrote: > > > > > On Nov 23, 7:06 pm, wxy0...@gmail.com wrote: > > > > On 11=D4=C223=C8=D5, =C9=CF=CE=E73=CA=B157=B7=D6, hal-use...@ip-64-139= -1-69.sjc.megapath.net (Hal > > > > Murray) wrote: > > > > In article <4b0dadd1-4bdb-4825-ad06-6d8ca2c6d...@i29g2000prf.googleg= roups.com>, wxy0...@gmail.com writes: > > > > > >In a design, I have to generate several clocks with precisely phase= > > > > >relationship, I'd like to useDCM. But the clock_input is not stable= . > > > > >It could possiblely change frequency, even stop for a while. I dont= > > > > >have input signal to resetDCM. How can I useDCMin this condition? > > > > >Or, if don't useDCM, how can I chieve precise phase relationship? > > > > > What sort of frequency range are you interested in? > > > > > This isn't "phase" as measured in degrees, but have you > > > > considered an external delay line? If you pick the delays > > > > for the fastest frequency the logic should still work when > > > > the clock slows down. But it might not give you the output > > > > you want. > > > > > Have you looked at clock generator chips? Some of them > > > > have multiple outputs at different speeds. You might get > > > > lucky and find something that fits you needs. > > > > > In the old days, the do-it-yourself clock generator was > > > > a PAL clocked at twice the highest speed you needed. > > > > (Or a '374 and a few gates.) > > > > > -- > > > > These are my opinions, not necessarily my employer's. I hate spam. > > > > Thank you, Murray > > > > It's my fault that I didn't make a clear description. > > > > My whole project is based on a virtex-4 SX55 FPGA, only one > > > clock_input, frequency up to 300MHz, and may chang to any frequency > > > slower, but not under my control. So, in FPGA, I have to use some > > > logic to generate some slower clock in the FPGA to feed internal > > > logic, which have precisely phase relationship. > > > > As the clock may change frequency while not even notified, how can I > > > use DCM wihout any UNLOCKED problem? Or, how can I got the clocks with= > > > given phase relationship without DCM? Can I use the LOCKED signal to > > > reset DCM? Is it reliable? > > > > Thanks! > > > So you have an incoming clock that can be any frequency up to 300 MHz, > > and may also stop completely. > > Can you run your logic off another, stable oscillator? > > A DCM is not the only way to reduce the clock rate: You can use a > > simple binary counter for that. > > > Your question is incomplete. Therefore it is tough to suggest > > solutions. > > Peter Alfke, Xilinx Applications- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4= =D7=D6 - > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > Hi, Peter > > First, I don't have any other oscillators. > > Second, as I know, it is tough to achieve phase relationship using > binary counters. > Phase relationship can change dramticly while frequency changs.Do you > have any suggestions? > > Third,can I use LOCKED signal to reset DCM? Is it reliable? > > Thanks If you want meaningful suggestions, you must tell us more about your design and its constraints. When you say that you have no continuously running oscillator: You can buy one for about $1.00. Peter AlfkeArticle: 126478
On Thu, 22 Nov 2007 13:33:14 -0800, Mike Treseler wrote: > Paul Taylor wrote: >> ... >> I also have a marked keyword, which is a safeguard >> because sometimes I stupidly use the wrong variable, e.g. an >> unsynchronised signal instead of one that I have synchronised for use >> (especially when I come back to change some code). > > Interesting. > I now handle this manually by using annoying > identifiers for the unsynch nodes. > Maybe "run_glitchy" vs "run". > >> I would be interested to know what mistakes others commonly make, that are >> found by the VHDL compiler. > > OK here's mine. > I get automated mistake-finding at the > editor, analysis, and elaboration level > of each library unit. > > 1. Emacs vhdl-mode completes keywords > and identifiers, matches most parens > and prompts for clauses in a keyword statement. > This prevents most syntax errors from happening. > > 2. I run simulation analysis > vcom -c mydesign.vhd > from an editor function key every few lines of code. > This step finds the most errors > but puts the cursor right on each one > and tells me what's wrong. > > I would estimate: > 90% syntax punctuation: missing or excess : ; ) etc. > 10% static mismatch of code with local or library subtypes. > Length, range etc. > 10% signature mismatch of code and local or library subprograms > > At the top level, Emacs vhdl-make automatically finds > units with multiple declarations in the project path, like this: > WARNING: Architecture declared twice (used 1.): "synth" of "cnt_decode" > 1. in "~/vhdl/play/cnt__decode.vhd" (line 18) > 2. in "~/vhdl/play/cnt_decode.vhd" (line 18) > > 3. elaboration: > vsim -c mydesign > will find most runtime mismatches > and give a pretty good description of what's wrong. > Some messages are more cryptic hints at infinite loops,like > ** Fatal: Write failure in vlm process (32,-1) > > That leaves the functional errors to simulation > viewers and assertions, but I have no automated > method for this. > > -- Mike Treseler Thanks for info, Paul.Article: 126479
I have a following state machine. enable is an input comiing from a
accumulate core. Now the total number of inputs to be accumulated
varies but is always greater than 5.so the maximum frequency of
enable becoming high is every 5th cycle or more.
I just want to find out if I have to provide a constraint on enable so
that the synthesis tool understands that the enable1 doesnt become
high every clock cycle and that the state machine wont miss any
enable='1' input coming in and the desing would funtion properly ? or
is it that synthesis and post sysnthesis tools dont care about this at
all?
process(clock,reset)
begin
if reset = '1' then
state1 <= IDLE;
.....................
...................................
elsif clock'event and clock = '1' then
case state1 is
when IDLE1 =>
if enable= '1' then
state1 <= M1 ;
else
state1 <= IDLE1;
end if;
when M1 =>
TD <= numout;
state1 <= M3;
when M3 =>
................
.................................
state1 <= M4;
...................
................................
when M4 =>..
...................................
state <= IDLE1;
end case;
end if;
end process;
regards
ng
Article: 126480On 11=D4=C224=C8=D5, =CF=C2=CE=E712=CA=B108=B7=D6, Peter Alfke <al...@sbcglo= bal.net> wrote: > On Nov 23, 7:44 pm, wxy0...@gmail.com wrote: > > > > > > > On 11=D4=C224=C8=D5, =C9=CF=CE=E711=CA=B122=B7=D6, Peter Alfke <al...@sb= cglobal.net> wrote: > > > > On Nov 23, 7:06 pm, wxy0...@gmail.com wrote: > > > > > On 11=D4=C223=C8=D5, =C9=CF=CE=E73=CA=B157=B7=D6, hal-use...@ip-64-1= 39-1-69.sjc.megapath.net (Hal > > > > > Murray) wrote: > > > > > In article <4b0dadd1-4bdb-4825-ad06-6d8ca2c6d...@i29g2000prf.googl= egroups.com>, wxy0...@gmail.com writes: > > > > > > >In a design, I have to generate several clocks with precisely pha= se > > > > > >relationship, I'd like to useDCM. But the clock_input is not stab= le. > > > > > >It could possiblely change frequency, even stop for a while. I do= nt > > > > > >have input signal to resetDCM. How can I useDCMin this condition?= > > > > > >Or, if don't useDCM, how can I chieve precise phase relationship?= > > > > > > What sort of frequency range are you interested in? > > > > > > This isn't "phase" as measured in degrees, but have you > > > > > considered an external delay line? If you pick the delays > > > > > for the fastest frequency the logic should still work when > > > > > the clock slows down. But it might not give you the output > > > > > you want. > > > > > > Have you looked at clock generator chips? Some of them > > > > > have multiple outputs at different speeds. You might get > > > > > lucky and find something that fits you needs. > > > > > > In the old days, the do-it-yourself clock generator was > > > > > a PAL clocked at twice the highest speed you needed. > > > > > (Or a '374 and a few gates.) > > > > > > -- > > > > > These are my opinions, not necessarily my employer's. I hate spam= . > > > > > Thank you, Murray > > > > > It's my fault that I didn't make a clear description. > > > > > My whole project is based on a virtex-4 SX55 FPGA, only one > > > > clock_input, frequency up to 300MHz, and may chang to any frequency > > > > slower, but not under my control. So, in FPGA, I have to use some > > > > logic to generate some slower clock in the FPGA to feed internal > > > > logic, which have precisely phase relationship. > > > > > As the clock may change frequency while not even notified, how can I= > > > > use DCM wihout any UNLOCKED problem? Or, how can I got the clocks wi= th > > > > given phase relationship without DCM? Can I use the LOCKED signal to= > > > > reset DCM? Is it reliable? > > > > > Thanks! > > > > So you have an incoming clock that can be any frequency up to 300 MHz,= > > > and may also stop completely. > > > Can you run your logic off another, stable oscillator? > > > A DCM is not the only way to reduce the clock rate: You can use a > > > simple binary counter for that. > > > > Your question is incomplete. Therefore it is tough to suggest > > > solutions. > > > Peter Alfke, Xilinx Applications- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4= =D7=D6 - > > > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - > > > Hi, Peter > > > First, I don't have any other oscillators. > > > Second, as I know, it is tough to achieve phase relationship using > > binary counters. > > Phase relationship can change dramticly while frequency changs.Do you > > have any suggestions? > > > Third,can I use LOCKED signal to reset DCM? Is it reliable? > > > Thanks > > If you want meaningful suggestions, you must tell us more about your > design and its constraints. > When you say that you have no continuously running oscillator: You can > buy one for about $1.00. > Peter Alfke- =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - I just have one question Whenever DCM is UNLOCKED, LOCKED signal is low, is that sure? ThanksArticle: 126481
"fl" <rxjwg98@gmail.com> wrote in message news:ccb086d1-775c-44cf-8666-bc357a309d93@b15g2000hsa.googlegroups.com... > Hi, > I want to learn the implementation of CORDIC. I find the following > website has some code which I would like begin with it. > > > http://www.ht-lab.com/freecores/cordic/cordic.html > > But I cannot simply simulate it in my Modelsim PE (student version) > because of the setup problem. Could you, the FPGA and VHDL experts can > tell me how to simulate it? Especially could you tell me how its > structure about the behaviour and synthesis files arranged? > > > Thanks in advance. Send me an email and I will create a standalone Modelsim version for you. I wrote this code some time ago using HDL Designer and Modelsim. Regards, Hans www.ht-lab.comArticle: 126482
On Fri, 23 Nov 2007 23:00:52 -0800 (PST), nbg2006@gmail.com wrote: >I have a following state machine. enable is an input comiing from a >accumulate core. Now the total number of inputs to be accumulated >varies but is always greater than 5.so the maximum frequency of >enable becoming high is every 5th cycle or more. >I just want to find out if I have to provide a constraint on enable so >that the synthesis tool understands that the enable1 doesnt become >high every clock cycle and that the state machine wont miss any >enable='1' input coming in and the desing would funtion properly ? or >is it that synthesis and post sysnthesis tools dont care about this at >all? You don't need to provide a special constraint on 'enable'. It's a synchronous signal like any other, and the general clock-period constraint is probably all you need. However, if you're going for a very fast clock you may wish to take advantage of the fact that 'enable' is infrequent. The logic associated with the 'enable' signal itself looks pretty simple, and should be left with the standard clock constraint. But what about "numout"? If that result signal is at the end of a long combinational path, you may wish to apply a multi-cycle path constraint to it - probably not 5 clocks, but perhaps 2 or 3 depending on the logic that creates it. The question you must ask is: How many clock cycles do I have between the clock that causes a source register taking up its final settled value, and the clock that causes the result to be captured in another register? That's not obvious from your state machine, because it depends on the nature of the pipelining in the logic that creates "numout". Personally I very much dislike using multi-cycle constraints because they're hard to get right, and even harder to maintain correctly as the design changes. If you can avoid it, so much the better. But if you must, take a really close look at your synthesis tool's documentation on multi-cycle constraints. Some of the FPGA tools can automatically infer multi-cycle constraints in some simple cases, but I'd guess that your logic is too involved for that to work. There are (high-cost) tools based on formal technology that can automatically generate multi-cycle constraints in a very sophisticated way; FishTail and BluePearl are worth a look. If you're going to use multi-cycle constraints, be sure to apply them *before* synthesis so that they affect both synthesis and P&R. If you leave it until after synthesis, not only will it be unreasonably hard to locate all the paths that need constraining, but also the synth tool will have made inappropriate decisions about optimization. >process(clock,reset) > begin > if reset = '1' then > state1 <= IDLE; > ..................... > elsif clock'event and clock = '1' then > > case state1 is > when IDLE1 => > if enable= '1' then > state1 <= M1 ; > end if; > > when M1 => > TD <= numout; > state1 <= M3; [...] -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 126483
Hello, I have generated a block-ram based FIFO queue (2 independent clocks, 2 inputs, 1 output) with the use of Core Generator. In the creator I used version without registered outputs (1 clock latency). I tested it by this code: process(P_I_CLK,P_I_RESET_N) variable v_state : integer := 0; variable licznikX : integer range 0 to 255 := 0; begin if P_I_RESET_N = '0' then v_state :=0; elsif P_I_CLK'event and P_I_CLK = '1' then sig_set_counter<='0'; case v_state is when 0 => sig_data_to_fifo <= sig_counter; sig_set_counter<='1'; sig_push_fifo <= '1'; sig_pop_fifo <= '0'; v_state := 1 ; when 1 => sig_data_to_fifo <= sig_counter; sig_push_fifo <= '1'; sig_pop_fifo <= '0'; v_state := 2 ; when 2 => sig_data_to_fifo <= sig_counter; sig_push_fifo <= '0'; sig_pop_fifo <= '1'; v_state := 3 ; when 3 => sig_data_to_fifo <= sig_counter; sig_push_fifo <= '0'; sig_pop_fifo <= '1'; v_state := 4 ; when 4 => sig_data_to_fifo <= sig_counter; sig_push_fifo <= '0'; sig_pop_fifo <= '1'; v_state := 5 ; when 5 => sig_data_to_fifo <= sig_counter; sig_push_fifo <= '1'; sig_pop_fifo <= '1'; v_state := 6 ; when 6 => sig_data_to_fifo <= sig_counter; sig_push_fifo <= '1'; sig_pop_fifo <= '1'; v_state := 7 ; when 7 => sig_data_to_fifo <= sig_counter; sig_push_fifo <= '0'; sig_pop_fifo <= '1'; v_state := 8 ; when 8 => sig_data_to_fifo <= sig_counter; sig_push_fifo <= '0'; sig_pop_fifo <= '1'; v_state := 0 ; when others => sig_data_to_fifo <= sig_counter; sig_push_fifo <= '0'; sig_pop_fifo <= '0'; v_state := 0 ; end case; end if; end process ; Signal sig_counter is output of counter. And I ran ChipScopePro. I shown this: http://www.elektroda.pl/rtvforum/download.php?id=272487 On the picture signal sig_data_to_fifo equels sig_dane_do_fifo and signal sig_data_from_fifo equels sig_dane_z_fifo. Output of FIFO I think works well. But I do not understand how does fifo set port EMPTY. Could anyone tell me that all is correctly? Clock is 50MHz, device is virtex2pro. Thanks, zlotawyArticle: 126484
"HT-Lab" <hans64@ht-lab.com> wrote in message news:8HS1j.43310$9Y3.1560@newsfe1-win.ntli.net... > > "fl" <rxjwg98@gmail.com> wrote in message > news:ccb086d1-775c-44cf-8666-bc357a309d93@b15g2000hsa.googlegroups.com... .. snip >> >> Thanks in advance. > > Send me an email and I will create a standalone Modelsim version for you. Use this procedure: 1) Navigate to the work_mti directory in a DOSbox/cygwin/Msys shell etc 2) Issue the following command vlib Cordic vmap work Cordic vcom -work Cordic -just p ..\hdl\*.vhd vcom -work Cordic -just b ..\hdl\*.vhd vcom -work Cordic -just e ..\hdl\*.vhd vcom -work Cordic -just a ..\hdl\*.vhd vsim -c -do tb.scr And you should get something like: # Angle=60101B Sin=3FD815 Expected=3FD816 Cos=0476E0 Expected=0476E3 PASS # Angle=612E10 Sin=3FE98D Expected=3FE98B Cos=035976 Expected=035978 PASS # Angle=624C04 Sin=3FF603 Expected=3FF604 Cos=023BCB Expected=023BCB PASS # Angle=6369F8 Sin=3FFD7E Expected=3FFD81 Cos=011DF3 Expected=011DF0 PASS # ** Failure: *** End of Test *** Next remove all the std_logic_arith/std_logic_unsigned package references and replace them with the recommended numeric_std package :-) Regards, Hans. www.ht-lab.comArticle: 126485
hi, i would like to use a small fpga (or cpld) on a pcb to make direct bidirectional connections between pins. basically it should act like a programmable "cable". is this kind of application possible using programmable logic? regards jArticle: 126486
On Sat, 24 Nov 2007 12:56:34 +0100, joe <nospam@gmail.com> wrote: >i would like to use a small fpga (or cpld) on a pcb to make direct >bidirectional connections between pins. >basically it should act like a programmable "cable". >is this kind of application possible using programmable logic? Not with a conventional CPLD. You would need to know enough about the signal flow to control the CPLD's output buffers. There are plenty of bidi switch devices around (QuickSwitch and suchlike). It might be a good idea to build a crosspoint matrix of such switches, and then use a small CPLD to control the enables. Lattice have a really interesting product that might suit your needs: http://www.latticesemi.com/products/digitalinterconnect/ispgdx2.cfm I have no idea about price, availability and development tools for those parts. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 126487
Hi,
How many long Xilkernel take to startup with microblaze (System
Clock : 50 MHz).
On my design, the Microblaze need more than 30 second to create the
first thread after xil_kernel_main().
Regards,
Yannick
From m.nguyen@arcor.de Sat Nov 24 05:17:01 2007
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Message-Id: <474823d0$0$27140$9b4e6d93@newsspool1.arcor-online.net>
From: Minh Nguyen <m.nguyen@arcor.de>
Subject: Re: can't read/load memory contents
Newsgroups: comp.arch.fpga
Date: Sat, 24 Nov 2007 14:17:01 +0100
References: <a237d8ac-8862-4f20-8996-274dd3149101@d61g2000hsa.googlegroups.com>
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On Fri 23 Nov 2007 15:35 dartanian wrote:
> Hello there, one of new members around here.
>
> I've got a problem while i try to retrieve/pass over some values to
> memory. I use EDK 9.1 and a system of microblaze, opb bus and opb
> bram
> memory.
> I try to retrieve some values from memory through a vhdl testbench,
> which is port mapped in the PORT B of Bram (by making Bram's PORT B
> external) and then write back these contents in other blocks - after
> some processing.
> I use Eclipse SDK 9.1 for that and write the following code (load and
> store instructions) within a loop:
>
>
> asm(" lwi r8,r8,0x7a810001 ");
^^
What is the value of r8? Here you load the contents of address (r8 +
0x7a810001) into register r8.
To load addr's contents you should better write you should write:
lwi r8, r0, addr
So you don't need to set r8 to 0 first.
Unfortunately you cannot load a word from an unaligned location anyway. So
addr must be divisible by 4.
> asm(" sw r8,r8(r8) ");
>
>
> I don't seem to get the contents of 0x7a810001 address (which is
> 'bbbbbbbb' - given by vhdl testbench) into the simulation outcome.
> Is there sth wrong with the use of instructions? Should i use an OR/
> ORI as well? Any problems with 16 or 32 bit values?
As I mentioned above lwi needs a word-aligned address. If you really have to
load a word beginning at 0x7a810001 you coud read the words at 0x7a810000
and 0x7a810004 and do some shift magic than.
> Thank you very much guys in advance!
Article: 126488> > I just have one question > Whenever DCM is UNLOCKED, LOCKED signal is low, is that sure? > > Thanks Not necessarily. At least in a Virtex II DCM, the LOCKED signal is not valid if the input clock stops. There is another signal in the STATUS outputs that indicates a loss of input clock, so you have to AND this with LOCKED to have an indicator of when your DCM is "working". Other FPGAs' DCMs or PLLs probably work differently than this, so you need to study the user guide to find out. BarryArticle: 126489
See the extremely bad opinion of Joe Costello as former CEO of CADENCE: http://xputers.informatik.uni-kl.de/staff/hartenstein/karlHistory.html#Costello Archimedes Neutrino psihodelia@googlemail.com wrote: > Just look at its syntax. It is so archaic that anyone who had any deal > with Python will just laugh. Try, say, to create a simple VGA > controller, which is simply readable. > > VHDL's Ada syntax is also very error prone. Instead of having all this > archaic constructions and surplus operators, it would be much more > productive just to start thinking about to create another hi-level HDL > that has absolutely another conceptual design and simple syntax. > > Any good language should be so simple as possible and any program in > this language should be short and clear. Such language should support > associative arrays, that should help designing large FSMs; should > support simple mechanism of type conversions and so on... > > Conceptually VHDL is not bad at all, it supports a lot of things, well > in theory. But in praxis ... > > And don't forget about future FPGAs, about future SoCs, which will > have integrated MEMS arrays, and other stuff. Try to understand how > much complexer they are to be designed in so unproductive way using so > primitive languages.Article: 126490
Hi all I am using Xilinx dual processor reference design suite to develop dual processor (xapp996) system on virtex-2 pro. I want to port an operating system on to this design Is it possible to port an OS that uses this dual-core system. Please help if anybody worked with this reference design ThanksArticle: 126491
joe wrote: > hi, > > i would like to use a small fpga (or cpld) on a pcb to make direct > bidirectional connections between pins. > basically it should act like a programmable "cable". > is this kind of application possible using programmable logic? > > regards > j If you are looking for analog-switch crosspoint operation, no. You will need direction control signals, and then you can build a digital buffered crosspoint system. How many nodes and what delays can you tolerate ? A 128MC device could get close to 16x16 crosspoint. Some CPLDs are RAM based, loaded at power up, and those variants can be RAM reloaded - meaning you could re-spin the logic itself, via the JED info, in order to get maximum crosspoint choice, in a small device. Makes more sense in higher volume apps, as there is more engineering needed. -jgArticle: 126492
joe wrote: > i would like to use a small fpga (or cpld) on a pcb to make direct > bidirectional connections between pins. > basically it should act like a programmable "cable". > is this kind of application possible using programmable logic? http://www.intersil.com/cda/deviceinfo/0,1477,CD22M3494,00.html#data is one of many devices made for this purpose. Though some have built in buffers, and so are not bidirectional, others are. You can use tristate drivers in most FPGAs, so that you could select the direction, but internally the datapaths are programmed directionally. -- glenArticle: 126493
dilip wrote: > is there any software that converts 'c' program to a 'vhdl' program?? There is always a C compiler generating a ROM for a processor implemented in VHDL ready to synthesize. That might not be what you meant. The thought process is different between serial C and "everything happens all the time" HDL's. A VHDL program is more like wire and gates, and very little like a C program. -- glenArticle: 126494
Ved wrote: > How can we measure setup and hold time of a flip-flop on FPGA in lab ? Configure a device with one FF connected to I/O pins. The clock likely connects to a dedicated clock input pin. Put in signals with varying delay and see what the output looks like. As someone else mentioned, a stripline with a movable tap could probably do it. -- glenArticle: 126495
Matt The EPCS should be programmed using the 'Active Serial Programming' mode, not JTAG. André Nevo wrote: > I'm soldering up my first FPGA design and I'm getting discouraged. > > I'm using an Altera Cycline with an EPCS1 serial configuration device. I've > soldered up the passives and the power supply but the only active part I've > put on the board is the configuration PROM. > > I've connected my ByteBlaster to my board, and it doesn't see the PROM > device. I get the error "Unable to scan device chain. Can't scan JTAG > chain." Quartus will, however, see the Cyclone device on another (also > not-working) board of mine. > > I've checked and double-checked the connections per Figure 4-2 of the Serial > Configuration Devices datasheet, and the continuity tester says it all > checks out. I've tried the PROM soldered in both ways, but no success. > > Are there any magical troubleshooting steps out there I don't know of? It's > quite discouraging that I've spent this money to have custom boards made, > paid for parts, etc. and find that I can't program the PROM. > > Thanks in advance for any tips. > > -Matt > >Article: 126496
Wolfgang Grafen wrote:
> MyHDL is a one man show.
MyHDL is set up as a typical open-source project. It is as open as possible
and encourages people to contribute. People do contribute when it's useful
to them, and they do so for MyHDL. Of course, there is a benevolent dictator
(yours truly) to set the pace and to arbitrate.
So the statement above is disrespectful to all those who contributed in some
form to MyHDL. I immediately add that I'll take the blame: I haven't
acknowledged these contributions explicitly enough in the past. I'll try
to fix that, and I apologize to all those concerned.
> I doubt that Python is the ideal language based for
> hardware description. I believe it is possible to design a very concise dynamic
> language for hardware design. But this will significantly more than one person
> to bring it up. My impression is MyHDL is not very suitable for large projects now.
doubt, believe, impression ... instead of spreading FUD, why not just
tell us about our complaints and the features you are missing. (Not in this
newsgroup of course.)
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 126497Andre, From within Quartus, I'm going to the Tools menu, selecting Programmer, then clicking on Auto Detect. Is that not appropriate for the EPCS device? If not, then how do I program the device from within Quartus? -Mat "Andre" <avsaway@hotmail.com> wrote in message news:e2fcd$47494ed9$541ef477$6219@cache6.tilbu1.nb.home.nl... > Matt > > The EPCS should be programmed using the 'Active Serial Programming' mode, > not JTAG. > > André > > Nevo wrote: >> I'm soldering up my first FPGA design and I'm getting discouraged. >> >> I'm using an Altera Cycline with an EPCS1 serial configuration device. >> I've soldered up the passives and the power supply but the only active >> part I've put on the board is the configuration PROM. >> >> I've connected my ByteBlaster to my board, and it doesn't see the PROM >> device. I get the error "Unable to scan device chain. Can't scan JTAG >> chain." Quartus will, however, see the Cyclone device on another (also >> not-working) board of mine. >> >> I've checked and double-checked the connections per Figure 4-2 of the >> Serial Configuration Devices datasheet, and the continuity tester says it >> all checks out. I've tried the PROM soldered in both ways, but no >> success. >> >> Are there any magical troubleshooting steps out there I don't know of? >> It's quite discouraging that I've spent this money to have custom boards >> made, paid for parts, etc. and find that I can't program the PROM. >> >> Thanks in advance for any tips. >> >> -MattArticle: 126498
Never mind. Found it. Thank you for pointing that out. I wouldn't have figured that out on my own! "Nevo" <nevo@nevo.com> wrote in message news:Brh2j.40740$Pt.1121@trnddc02... > Andre, > > From within Quartus, I'm going to the Tools menu, selecting Programmer, > then clicking on Auto Detect. > > Is that not appropriate for the EPCS device? If not, then how do I program > the device from within Quartus? > > -Mat > > "Andre" <avsaway@hotmail.com> wrote in message > news:e2fcd$47494ed9$541ef477$6219@cache6.tilbu1.nb.home.nl... >> Matt >> >> The EPCS should be programmed using the 'Active Serial Programming' mode, >> not JTAG. >> >> André >> >> Nevo wrote: >>> I'm soldering up my first FPGA design and I'm getting discouraged. >>> >>> I'm using an Altera Cycline with an EPCS1 serial configuration device. >>> I've soldered up the passives and the power supply but the only active >>> part I've put on the board is the configuration PROM. >>> >>> I've connected my ByteBlaster to my board, and it doesn't see the PROM >>> device. I get the error "Unable to scan device chain. Can't scan JTAG >>> chain." Quartus will, however, see the Cyclone device on another (also >>> not-working) board of mine. >>> >>> I've checked and double-checked the connections per Figure 4-2 of the >>> Serial Configuration Devices datasheet, and the continuity tester says >>> it all checks out. I've tried the PROM soldered in both ways, but no >>> success. >>> >>> Are there any magical troubleshooting steps out there I don't know of? >>> It's quite discouraging that I've spent this money to have custom boards >>> made, paid for parts, etc. and find that I can't program the PROM. >>> >>> Thanks in advance for any tips. >>> >>> -Matt > >Article: 126499
Argh. I just discovered that my ByteBlaster MV clone can't program an EPCS configuration PROM, but the ByteBlaster II can. Google led me to a web forum that suggests an MV can be converted to a II, but I haven't been able to find any details. Does anyone know if it's possible to convert a ByteBlaster MV into a ByteBlaster II, and if so what the details are? Thanks, -Nevo
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