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On 2 Nov., 15:46, giorgos.puik...@gmail.com wrote: > Hello, > > I want to synthesize my VHDL code targeting an ASIC design, and I want > to do this using as primitive elements only NAND gates and d-flip- > flops. > > So, basically what I think I have to do is either build a new library > for the synthesizer containing only what I want to use, or use an > existing library excluding all the "building-blocks" I don't want. I > should make clear that I am only interested in getting an RTL > schematic of my synthesized-design, and not getting any back- > annotation information. You are contradicting yourself. The RTL level description usually is technology independant. Mapping to your nand only library will be performed in a later step called "techology mapping". (First there are likely to be a few other technology indpendant optimization.) The result will be a gate level netlist. Many technolgy mappers start with a representation that only consists of nand gates, inverters and DFFs. If you find a way of telling your tool to output that netlist you are done. Or use SIS: http://www1.cs.columbia.edu/~cs4861/s07-sis/sis.1.html Kolja SulimmaArticle: 125751
EDK 9.2 is being released today. "Dave" <dhschetz@gmail.com> wrote in message news:1194024413.469876.12700@50g2000hsm.googlegroups.com... > When is EDK 9.2 supposed to be released? I had heard October, but > WebUpdate still tells me that there are no updates right now > (currently using ISE 9.1 nad EDK 9.1) >Article: 125752
Kolja, I see it differently: A weak keeper has two disadvantages: It is weak, and might be overridden by crosstalk It consumes constant power when the signal is pulled Low. The intelligent output driver is stronger in pulling High, thus offering better protection against crosstalk, and it consumes no power when it has been pulled Low. Obviously, any external driver must be strong enough to overcome the active driver foe a few ns. That's the balancing act. Peter Alfke On Nov 2, 11:04 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > Why not use a weak keeper instead? > Older Xilinx part used that internally on tristate lines. You have a > weak buffer that drives the line to the voltage seen on the line. > An undriven line will quickly be driven to either 1 or 0 due to > initial noise. Another circuit driving the line will need to overcome > the keeper current (similar to a switching sram cell). The upside is: > There is no static current (unlike the pullup resistor). > > Kolja SulimmaArticle: 125753
Peter Alfke wrote: > Kolja, I see it differently: > A weak keeper has two disadvantages: > It is weak, and might be overridden by crosstalk > It consumes constant power when the signal is pulled Low. What you have described is a pullup ? Keepers, also called Bus-hold, or PinKeepers (depends on which vendor you are), are snap-action positive feedback 'very light' drivers, and they draw no power in either state. (typically hundreds of uA) Of course, a disadvantage of that, is the Pin state is now undefined at PowerUP, and that may be a bad thing. The smarter CPLDs allow you to choose Pullup/PinKeep on a per pin basis. -jgArticle: 125754
Mike, Thanks for the help. I checked the register values. They are correct. Also, I tried several memory addresses and they are accessible. After trying to reload several times, I found that sometimes, one processor stopped at the beginning as it should be, but the other processor still failed to do so. Now I'm really lost. --CathyArticle: 125755
The only thing that really matters is the best combination of logic, circuitry, and transistor technology that achieves the smallest incremental carry delay per bit. And everybody can easily do a static timing analysis to calculate that incremental delay. I think it is about 30 ps per bit. Peter Alfke, XilinxArticle: 125756
Hi, there My design needs a 16X16 matrix, each of 32-bit. The matrix must be read row by row or column by column each in one clock.. Direct register implementation takes a lot of resources and routing can be difficult. Will 256 pieces of 32-bit RAM with single address work in Xilinx? TIA!Article: 125757
brianwfarmer@gmail.com wrote: > I am mainly looking to make my ModelSim test bench simulation > creations easier/faster. How does Xilinx's System Generator versus > Mathworks' Link for Modelsim compare for that? Unless you are using MATLAB for a dsp application, I don't see a reason to evaluate either one. -- Mike TreselerArticle: 125758
"G Iveco" <G.Iveco@google.com> wrote in message news:fgi30n$245$1@reader01.singnet.com.sg... > Hi, there > > My design needs a 16X16 matrix, each of 32-bit. The matrix must > be read row by row or column by column each in one clock.. > > Direct register implementation takes a lot of resources and routing can > be difficult. Will 256 pieces of 32-bit RAM with single address work > in Xilinx? > Yes. You write the code to implement whatever logic function you require. Start wirting some code and simulating it until it's functionally working the way you want it to be. As a BACKGROUND task start running your code through the synthesis process and look to see how what you've written is being implemented and what sort of clock cycle performance you can expect. If it's not to your liking then start perusing for other more elegant ways of implementing your logic but don't get so focused on the synthesis task that you forget to handle the primary task which is to get functionally correct code. KJArticle: 125759
"KJ" <kkjennings@sbcglobal.net> wrote in message news:dF2Xi.13969$Pv2.11194@newssvr23.news.prodigy.net... > > > Yes. You write the code to implement whatever logic function you require. > > Start wirting some code and simulating it until it's functionally working > the way you want it to be. As a BACKGROUND task start running your code > through the synthesis process and look to see how what you've written is > being implemented and what sort of clock cycle performance you can expect. > If it's not to your liking then start perusing for other more elegant ways > of implementing your logic but don't get so focused on the synthesis task > that you forget to handle the primary task which is to get functionally > correct code. > > KJ > Thank you KJ. I understand in large designs simulation and synthesis had better go concurrently to make sure the design passes both steps nicely. But my question is, for memory based systems, For very large memory, register implementation takes N times silicon than RAM. For a small memory, RAM have overheads like RW, sensing, amplifier, etc which may be equivalent to a few hundred registers in terms of silicon and power. as a result, in the 2nd case, how much is this RAM overhead comparing to a 32-bit register in Xilinx? If there are good comparisons, then I can skip the trouble of testing..Article: 125760
"G Iveco" <G.Iveco@google.com> wrote: >Hi, there > >My design needs a 16X16 matrix, each of 32-bit. The matrix must >be read row by row or column by column each in one clock.. > >Direct register implementation takes a lot of resources and routing can >be difficult. Will 256 pieces of 32-bit RAM with single address work >in Xilinx? I'd suggest using the LUT rams as much as possible. Look in the datasheet. AFAIK Xilinx is one of the few FPGA vendors that has RAM in the logic slices. If you use these lut rams in a smart way, you can cram many times more logic in a device with lut ram than in a device without lut ram. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 125761
"G Iveco" <G.Iveco@google.com> wrote in message news:fgibec$2b5$1@reader01.singnet.com.sg... > > > But my question is, for memory based systems, > For very large memory, register implementation takes N times silicon than > RAM. > > For a small memory, RAM have overheads like RW, sensing, amplifier, etc > which may > be equivalent to a few hundred registers in terms of silicon and power. > > as a result, in the 2nd case, how much is this RAM overhead comparing to a > 32-bit register in > Xilinx? > But it really doesn't matter. When you follow the proper template, your code can be synthesized to use internal RAM or LUTs. That decision will be made by the synthesis tool. So look up the form of VHDL that will infer memory, write your code in that fashion, avoid use of wizards and such, and your code will synthesize to fit into the resources that are on the chip. It makes no difference whether the memory gets implemented in logic cells or memory arrays as long as it - implements the intended function - meets the performance requirements - Fits in the targetted device. > If there are good comparisons, then I can skip the trouble of testing.. > Testing which 'method' is better is pointless. Write code that can be inferred properly to the targetted part and leave the rest for the tools to implement. KJArticle: 125762
Hi all,
I have spent quite some time on the net trying to find info on how to
get the xilinx usb download cable to work with linux and I have
reached a dead end. :(
I have installed the usb-driver from http://www.rmdir.de/~michael/xilinx
and I have managed to light up the green led to the usb download cable
on the spartan 3e starter kit. The green led is going black every 6-8
second and then green again. I don't manage to get a connection to the
board using Impact. lsusb gives me the following:
Bus 005 Device 012: ID 03fd:0008 Xilinx, Inc.
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
idVendor 0x03fd Xilinx, Inc.
idProduct 0x0008
bcdDevice 0.00
iManufacturer 1
iProduct 2
iSerial 0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 32
bNumInterfaces 1
bConfigurationValue 2
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 280mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 255 Vendor Specific Class
bInterfaceSubClass 0
bInterfaceProtocol 0
iInterface 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x86 EP 6 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
can't get device qualifier: Operation not permitted
can't get debug descriptor: Operation not permitted
cannot read device status, Operation not permitted (1)
and Impact says:
Connecting to cable (Usb Port - USB21).
Checking cable driver.
File version of /usr/share/xusbdfwu.hex = 1025(dec), 0401.
libusb-driver.so version: 2007-10-08 15:43:55.
Cable connection failed.
Reusing B406EC01 key.
Reusing 3806EC01 key.
Reusing B506EC01 key.
Reusing 3906EC01 key.
Reusing B606EC01 key.
Reusing 3A06EC01 key.
Reusing B706EC01 key.
Reusing 3B06EC01 key.
PROGRESS_END - End Operation.
Elapsed time = 0 sec.
Cable autodetection failed.
WARNING:iMPACT:923 - Can not find cable, check cable setup !
Any idea where to look??
Thanks!
/Roger
Article: 125763Hi all, I want to create a clock of 40MHz and 10MHz on my ACTEL ProASIC3 evaluation board, I try to use the Static PLL macro from the Libero IDE since in the documentation of ACTEL they tell us to use this macro's for best performance,... But I can't get this system working anyone has some experience with this Macro? (An example will be fine) Kind regards and thanks for the help, VinceArticle: 125764
On Nov 3, 12:33 pm, n...@puntnl.niks (Nico Coesel) wrote: > "G Iveco" <G.Iv...@google.com> wrote: > >Hi, there > > >My design needs a 16X16 matrix, each of 32-bit. The matrix must > >be read row by row or column by column each in one clock.. > > >Direct register implementation takes a lot of resources and routing can > >be difficult. Will 256 pieces of 32-bit RAM with single address work > >in Xilinx? > > I'd suggest using the LUT rams as much as possible. Look in the > datasheet. AFAIK Xilinx is one of the few FPGA vendors that has RAM in > the logic slices. If you use these lut rams in a smart way, you can > cram many times more logic in a device with lut ram than in a device > without lut ram. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nl Here is my best-case estimate: You obviously need 16 x 32 = 512 parallel outputs In Virtex-5 each LUT can be used with 5 address bits and 2 outputs ( 32 x 2 RAM) That means you need 256 LUTs = 32 CLBs. And nothing else. This optimized packing requires that the software is smart enough to configure the LUTs appropriately. Worst-case, that is not yet the case, and you need 64 CLBs total. And nothing else. Even the small 'LX50 has 3600 CLBs total, (but not all of them can be used as memory). Just so you can have an educated guess. Let the software do the crunching... Peter AlfkeArticle: 125765
>> If I were designing the circuit board, I'd put in pads for snubbers. I'm >> buying from a 'group buy' on a DIY Christmas lights forum and the >> existing boards don't have snubbers designed in. I'll provide this >> feedback for next year's designs. :) > > How about a URL so that others interested could follow along? > > -- glen Sure! The software that most DIY'ers are using can be downloaded from http://www.vixenlights.com. The main website for most of the community is http://www.doityourselfchristmas.com. Most follks there have drifted over from http://www.computerchristmas.com, which is still active and has the genesis of many of the projects. There are several designs for driving lights from parallel ports and serial ports. My FPGA board is going to emulate the 'Horning Dimmer' design.Article: 125766
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1194147178.863589.141780@t8g2000prg.googlegroups.com... > On Nov 3, 12:33 pm, n...@puntnl.niks (Nico Coesel) wrote: >> "G Iveco" <G.Iv...@google.com> wrote: >> >Hi, there >> >> >My design needs a 16X16 matrix, each of 32-bit. The matrix must >> >be read row by row or column by column each in one clock.. >> >> >Direct register implementation takes a lot of resources and routing can >> >be difficult. Will 256 pieces of 32-bit RAM with single address work >> >in Xilinx? >> >> I'd suggest using the LUT rams as much as possible. Look in the >> datasheet. AFAIK Xilinx is one of the few FPGA vendors that has RAM in >> the logic slices. If you use these lut rams in a smart way, you can >> cram many times more logic in a device with lut ram than in a device >> without lut ram. >> >> -- >> Reply to nico@nctdevpuntnl (punt=.) >> Bedrijven en winkels vindt U opwww.adresboekje.nl > > Here is my best-case estimate: > You obviously need 16 x 32 = 512 parallel outputs > In Virtex-5 each LUT can be used with 5 address bits and 2 outputs > ( 32 x 2 RAM) > That means you need 256 LUTs = 32 CLBs. And nothing else. > This optimized packing requires that the software is smart enough to > configure the LUTs appropriately. > Worst-case, that is not yet the case, and you need 64 CLBs total. And > nothing else. > Even the small 'LX50 has 3600 CLBs total, (but not all of them can be > used as memory). > Just so you can have an educated guess. > Let the software do the crunching... > Peter > Alfke > > Thank you nico and Alfke. I tried using registers coded by RTL and estimate the hardware requirement and found my gigantic math module can fit in a Virtex 2, V3000.. It's old technology though. In Virtex 4, will XC4VLX40 be able to handle this? The documentation of two specs are different, only Slice count can be used as references. IOs are no issue here.Article: 125767
On Nov 3, 4:44 pm, "G Iveco" <G.Iv...@google.com> wrote: > Hi, there > > My design needs a 16X16 matrix, each of 32-bit. The matrix must > be read row by row or column by column each in one clock.. > > Direct register implementation takes a lot of resources and routing can > be difficult. Will 256 pieces of 32-bit RAM with single address work > in Xilinx? > > TIA! It may be possible to implement this structure using RAM's, and thus far fewer resources, but that will depend on a couple things. First, does each 16x16 matrix need to be accessed using both row and colomn addressing? Second, how is data written into the matrix - do entire rows/cols need to be written in a single cycle as well? The first requirement is easy to deal with. The second one, in conjunction with the first, makes life difficult. If you can handle writing data in one element at a time then you can construct a pair of ram structures one of which handles column addressing while the other handles row addressing. Both get written with the same data. Thanks, Andy.Article: 125768
On Nov 1, 1:08 pm, John McCaskill <jhmccask...@gmail.com> wrote: > On Nov 1, 1:42 pm, fazulu deen <fazulu.v...@gmail.com> wrote: > > > Dear all, > > > Is it possible to implement power management unit(idle and active) in > > FPGA? > > > pls give suggestions to implement clock generation unit in FPGA.... > > > regards, > > fazal > > If you mean can you reduce the power in the FPGA when it is idle by > adjusting the clock, yes. If you mean if you can reduce the power in the FPGA turning OFF unused banks, the answer is no. There are a lot of Xilinx and Altera engineers on this list. Just for them: as long many DSP's and SDRAMs have power management units allowing partial refresh, partial power supply etc, why this feature is not implemented in the FPGA ? thx, VasileArticle: 125769
>I want to create a clock of 40MHz and 10MHz on my ACTEL ProASIC3 >evaluation board, I try to use the Static PLL macro from the Libero >IDE since in the documentation of ACTEL they tell us to use this >macro's for best performance,... But I can't get this system working >anyone has some experience with this Macro? (An example will be fine) ACTEL don't give an example? It doesn't compile? It compiles but gives the wrong clock rates? It compiles but doesn't work at all? What exactly have you done? Imagine you fix TVs. A customer walks in, leaves their TV on the counter, says "Doesn't work" and leaves. What kind of starting point is that? The TV man can at least switch the set on and see what happens. We can't even do that. How can you imagine that we know where to begin?Article: 125770
There is only 8 bit interface wrapper(pcie_gt_wrapper.v) from Xilinx PCI-Express Endpoint Block IP. it means that it needs 250MHz clk.In general,it is impossible to achieve 250Mhz clk with large design.So,we need 16bit interface wrapper so that the clk can be reduced 125Mhz. it is very easy to implement.is there avaliable 16bit wrapper?Article: 125771
There are some MAXDELAY=1ns constrain for TX signals inside PCIE
coregen.
eg:
(* MAXDELAY="1.0" *) wire [1:0] tile0_txcharisk0_r;
(* MAXDELAY="1.0" *) wire tile0_txdetectrx0_r;
(* MAXDELAY="1.0" *) wire tile0_txelecidle0_r;
(* MAXDELAY="1.0" *) wire [1:0] tile0_txchardispmode0_r;
(* MAXDELAY="1.0" *) wire [15:0] tile0_txdata0_r;
(* MAXDELAY="1.0" *) wire [1:0] tile0_txchardispmode1_r;
(* MAXDELAY="1.0" *) wire [1:0] tile0_txchardispval1_r;
(* MAXDELAY="1.0" *) wire tile0_txdetectrx1_r;
(* MAXDELAY="1.0" *) wire [19:0] tile0_txdata1_r;
(* MAXDELAY="1.0" *) wire tile0_txelecidle1_r;
but,my core_clk is 4ns(250MHz) and user_clk is 8ns(125MHz). does it
still meet the MAXDELAY=1ns timing requirement?
Article: 125772Hi all, I have a simple question - is the APU controller is part of the FPGA/ PPC silicon or is it a soft-core that is added only when used ? Thanks, Mordehay.Article: 125773
On Nov 3, 9:03 pm, "G Iveco" <G.Iv...@google.com> wrote: > "Peter Alfke" <al...@sbcglobal.net> wrote in message > > news:1194147178.863589.141780@t8g2000prg.googlegroups.com... > > > > > On Nov 3, 12:33 pm, n...@puntnl.niks (Nico Coesel) wrote: > >> "G Iveco" <G.Iv...@google.com> wrote: > >> >Hi, there > > >> >My design needs a 16X16 matrix, each of 32-bit. The matrix must > >> >be read row by row or column by column each in one clock.. > > >> >Direct register implementation takes a lot of resources and routing can > >> >be difficult. Will 256 pieces of 32-bit RAM with single address work > >> >in Xilinx? > > >> I'd suggest using the LUT rams as much as possible. Look in the > >> datasheet. AFAIK Xilinx is one of the few FPGA vendors that has RAM in > >> the logic slices. If you use these lut rams in a smart way, you can > >> cram many times more logic in a device with lut ram than in a device > >> without lut ram. > > >> -- > >> Reply to nico@nctdevpuntnl (punt=.) > >> Bedrijven en winkels vindt U opwww.adresboekje.nl > > > Here is my best-case estimate: > > You obviously need 16 x 32 = 512 parallel outputs > > In Virtex-5 each LUT can be used with 5 address bits and 2 outputs > > ( 32 x 2 RAM) > > That means you need 256 LUTs = 32 CLBs. And nothing else. > > This optimized packing requires that the software is smart enough to > > configure the LUTs appropriately. > > Worst-case, that is not yet the case, and you need 64 CLBs total. And > > nothing else. > > Even the small 'LX50 has 3600 CLBs total, (but not all of them can be > > used as memory). > > Just so you can have an educated guess. > > Let the software do the crunching... Easy. In Virtex-4, you again need 512 outputs, each driven by a 32-bit RAM. In Virtex-4, each 32 x 1 RAM consists of two LUTs plus a free multiplexer. Call out RAM32x1S as shown in the "CLB Overview" fig 5-6 on page 219 of the Virtex-4 Handbook. That consumes 1024 LUTs, or 128 CLBs. The LX40 has 128 x 36 CLBs, which is 36 times more than you need. Peter Alfke, Xilinx Applications =============================== > > Peter > > Alfke > > Thank you nico and Alfke. > > I tried using registers coded by RTL and estimate the hardware > requirement and found my gigantic math module can fit in a Virtex 2, > V3000.. It's old technology though. > > In Virtex 4, will XC4VLX40 be able to handle this? The documentation > of two specs are different, only Slice count can be used as references. > > IOs are no issue here.Article: 125774
On Nov 2, 4:19 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Peter Alfke wrote: > > Kolja, I see it differently: > > A weak keeper has two disadvantages: > > It is weak, and might be overridden by crosstalk > > It consumes constant power when the signal is pulled Low. > > What you have described is a pullup ? > Keepers, also called Bus-hold, or PinKeepers (depends on which vendor > you are), are snap-action positive feedback 'very light' drivers, and > they draw no power in either state. (typically hundreds of uA) > > Of course, a disadvantage of that, is the Pin state is now undefined at > PowerUP, and that may be a bad thing. > > The smarter CPLDs allow you to choose Pullup/PinKeep on a per pin basis. > > -jg Since Xilinx FPGAs never had weak keepers on the user I/O, I got the nomenclature confused. Sorry. You can of course emulate a weak keeper by using the output driver at its weakest setting, but that may still be too strong in some applications (but not for switch debouncing). BTW, I should have mentioned that the switch must be break-before-make (obviously). Peter Alfke
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