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fpgazone@gmail.com wrote: > Hi, > > I have a Cyclone III FPGA. I have created a circuit on it whose > performance I want to observe under the influence of supply voltage > variations and glitches. > > I want to create intentional glitches of this cyclone iii development > board. Any ideas? For testing Logic under Supply variations, I fed a Signal generator into the ADJ pin on the regulator, via a resistor. This allows you to modulate Vcc at various speeds, and also ramp it slowly. That can be useful for margin testing: If your design fails at VccNOM-2%, you probably have work to do. If it work past VccMIN on the data sheet, you can have more confidance. -jgArticle: 125276
Alan Nishioka wrote: > On Oct 18, 3:27 am, xenix <last...@gmail.com> wrote: > >>Hello all, I would like to ask if i can install in my computer 2 >>different versions of EDK, one older than the other. >> > to switch between them, edit the xilinx and xilinx_edk environment > variables. i always have this setup because sometimes the new version > breaks my compile. and sometimes the difference is subtle and i don't > notice for months. And in a Linux environment this is trivial, you just source the appropriate settings.sh scripts for EDK and ISE. With consistently named installation dirs you can have as many versions as you like, and just script the selection process. $ XIL_VER=9.2 source /etc/profile.d/xilinx_tools.sh Cheers, JohnArticle: 125277
On Oct 18, 6:17 pm, Neil Steiner <neil.stei...@vt.edu> wrote: > > I would like to get advises about good books in dynamic > > reconfiguration using FPGAs. I need theoretical (algorithms, methods) > > as well as practical information. > > Don't we all!? ;) > > I think those "books" are still being written, and presently exist > mainly in the form of conference papers and journal articles. yes! I downloaded many many ieee (and other) papers on the subject. But you know that papers are good for some purposes and books for others! Reading a paper is good to get answer some precise question ... not for getting state of the art. Papers are for researchers. But I'm searching for some books for students and newcomers even to FPGA but who would like to get answers concerning reconfigurable computing.Article: 125278
On Oct 18, 7:17 pm, Neil Steiner <neil.stei...@vt.edu> wrote: > > I would like to get advises about good books in dynamic > > reconfiguration using FPGAs. I need theoretical (algorithms, methods) > > as well as practical information. > > Don't we all!? ;) > > I think those "books" are still being written, and presently exist > mainly in the form of conference papers and journal articles. All, I chanced to see a book, when i started my work on dynamic partial reconfiguration back in 2005 (for M.S thesis). Let me know if you understand any thing from the book . ;-) The detail of the book is: Dynamic Reconfiguration, Architectures and Algorithms By: Ramachndran Vaidyanathan and Jerry L. Trahan Kluwer Academic Press, 2004Article: 125279
On 18 Okt., 09:49, Antti <Antti.Luk...@googlemail.com> wrote: > the failing desing was made with S 8.8A1 and was not tested with other > version of synthesis tools > > after my quiz1 issue, that looked like tool error or faulty FPGA, I > was not to belive that another problem so close the first one is > related to tools making a mess, so I was very hard trying to find > problem in my design. > > I have made backup of the "known failing with 8.8" design, when i have > time, i will retest it with 8.6.2 Which technology are you using? Do you read the Actel customer notifications? "FSM Bug - Synplify=AE 8.6.2H in Libero=AE IDE 7.3, 7.3 SP1, and 7.3 SP2" This notification states also that you need to use 8.8A2 instead of 8=2E8A1 for Axcelerator design due to another bug. bye ThomasArticle: 125280
On Oct 19, 9:00 am, mh <moazzamhuss...@gmail.com> wrote: > On Oct 18, 7:17 pm, Neil Steiner <neil.stei...@vt.edu> wrote: > > > > I would like to get advises about good books in dynamic > > > reconfiguration using FPGAs. I need theoretical (algorithms, methods) > > > as well as practical information. > > > Don't we all!? ;) > > > I think those "books" are still being written, and presently exist > > mainly in the form of conference papers and journal articles. > > All, > I chanced to see a book, when i started my work on dynamic partial > reconfiguration back in 2005 (for M.S thesis). Let me know if you > understand any thing from the book . ;-) > > The detail of the book is: > > Dynamic Reconfiguration, Architectures and Algorithms > > By: > Ramachndran Vaidyanathan and Jerry L. Trahan > > Kluwer Academic Press, 2004 I have it ;) I don't have big difficulties reading it. )) But I think that it's not trivial to realize such things (R-mesh) on FPGA even using Xilinx ISE PREA.Article: 125281
Jonathan Bromley wrote: > 1) Break the bad habit of using nasty obsolete flaky > arithmetic packages, and switch to NUMERIC_STD. Jonathan, thanks for tips like that - I'm still looking for a good _current_ reference guide on VHDL (I own the "Designers guide to VHDL 2nd edition", but although it's often recommended, I'm not quite satisfied with it) where you would find stuff like that. > Instead, consider a procedural loop: Thanks (also to the others who suggested that), seems that i filed that under "not synthesizable" a few years ago when that was still the fact. - Philip -- Have you ever parked your motorcycle in a hotel room? (+3)Article: 125282
On Oct 18, 4:20 pm, cpan...@yahoo.com wrote: > We are using V5LX110T and V5L330 FPGAs. Are there decent pin swapping > utilities so that we do not have to spend a lot of time in PCB Laout > to do the pin swapping? I am hoping that the tool shows the BGA view > of the FPGA and lets the user to swap pins such that there is good > break out from the FPGA. > > Thanks. > > CP Xilinx Planahead does just that. I have successfully used this for a V5LX50-FF1153 design. This has several features apart from pin planning (PinAhead), including easy definition of placement constraints for meeting timing etc. Handy for pin planning is the ability to output a CSV file of the pins and I/O standards, which could then easily be imported into your PCB program (without scripting etc.). You can also reimport the CSV file and it will update the UCF. This is downloadable from the Xilinx website. According to Avnet Silica this software is being made free, even though it doesn't appear like that from the Xilinx site. The only irritation is that you have to download a new eval licence each month (have done this for the last 5 months). AndrewArticle: 125283
Jonathan Bromley wrote: > onehot_to_binary: process (onehot) is > variable OH: std_logic_vector (one_hot'length-1 downto 0); > variable result: unsigned(address'range); > begin > -- Paranoia: Normalize the onehot vector > -- so that you don't care how the original > -- was defined. Leftmost bit is number N-1, > -- rightmost bit is number 0. > OH := onehot; > -- start the OR-tree > result := (others => '0'); > -- build the OR-tree > for i in OH'range loop > if OH(i) = '1' then > result := result OR to_unsigned(i, result'length); > end if; > end loop; > -- copy result to your output signal > address <= result; > end process; You could do a similar thing with a generate loop containing a "when" statement - what's the advantage (or downside) to using a process? - Philip -- Have you ever parked your motorcycle in a hotel room? (+3)Article: 125284
On 18 Oct, 15:50, Bryan <bryan.fletc...@avnet.com> wrote: > Colin, > > A MAC+PHY costs more then a PHY, but you save the MAC IP cost and > gates in the FPGA. It is a good alternative to consider. > > Xilinx has a MicroBlaze interface to this type of device, called the > EPC. They also have an application note that describes how to use it: > http://www.xilinx.com/bvdocs/appnotes/xapp924.pdf > > The app note uses a piece of hardware that is no longer available > (Avnet P160 Comm 3 module), but you can look at the Spartan-3 Mini- > Module which also has the 91C111 MAC+PHY. > > Bryan > > > > colin wrote: > > Hi > > > Does anyone have any experiences with connecting a MAC rather than a > > PHY to a spartan(3e). > > > I don't know yet whether to use a microblaze or my own state machine > > to connect to the ethernet. For microblaze, xilinx cores seem to want > > just an external PHY but surely a MAC would offload more stuff from > > the FPGA. > > > Any thoughts appreciated. > > > Regards > > > Colin- Hide quoted text - > > - Show quoted text - Bryan Thanks for your reply, as a result I've made a much better job of searching the xilinx website. ColinArticle: 125285
+----------* +3,3V output
---
| | R=66 ohm
| |
---
|
----
\ / CDBU00340 or similar Vf=0.6
\/
----
|
FPGA +2,5V input *----+
GND *---------------* GND
Is it possible to use the above construction to adapt a 3,3V signal to a
level acceptable for 2,5V FPGA Vccaux input ..?
And thus eliminate or significantly reduce the need for a shunt resistor as
mentioned in XAPP453 page 5 "Managing Reverse Current" ..?
Maybe one could use R=1000 ohm to further reduce the reverse current.
As (3.3-2.5-Vf)/I_leak = 8000 ohm. I_leak = 0.000025 Amp (ds099.pdf p58).
The original idea was to not need any resistor at but as a component with a
suitable Vf seems hard to find. I thought this solution will at least reduce
the problem.
http://www.xilinx.com/bvdocs/appnotes/xapp453.pdf
Article: 125286aravind <aramosfet@gmail.com> wrote: >Hi, > I'm building a S/PDIF Receiver for implementation on spartan 3 . . > So what could be the possible cause of these glitches? I can >understand glitches near the edges which could be due to metastability >but in the middle of stable 1's and 0's there could be no issue of >metastability. I have used 2 flop synchroniser like the ones used in >asynchronous fifo's. What else can i do the eliminate the glitches? Try a schmitt trigger on input?, and possible some small capacitance?Article: 125287
pbFJqKD@ludd.invalid wrote: > +----------* +3,3V output > --- > | | R=66 ohm > | | > --- > | > ---- > \ / CDBU00340 or similar Vf=0.6 > \/ > ---- > | > FPGA +2,5V input *----+ > > GND *---------------* GND > Is it possible to use the above construction to adapt a 3,3V signal to a > level acceptable for 2,5V FPGA Vccaux input ..? > And thus eliminate or significantly reduce the need for a shunt resistor as > mentioned in XAPP453 page 5 "Managing Reverse Current" ..? > Maybe one could use R=1000 ohm to further reduce the reverse current. > As (3.3-2.5-Vf)/I_leak = 8000 ohm. I_leak = 0.000025 Amp (ds099.pdf p58). > The original idea was to not need any resistor at but as a component with a > suitable Vf seems hard to find. I thought this solution will at least reduce > the problem. Use level-Shifters, like 74LVC8T245 or "translating bus switches" like SN74CB3T1. They don't cost that much, require a single footprint and have much better signal integrety. E.g. you diode solution above will have long fall times, leading to irregular switching caused by noise and to current surges in the input buffer caused by the input drifting slowly through the linear region. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 125288
Hello folk! Hello, I have just bought Spartan 3E-1600E Microblaze Development kit and I am complete beginner. Really want to learn FPGA programming but have no idea what this board is for. For example, the LEDs (all are green) - what they really represent?... and LCD? Can I print something on it?Article: 125289
Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: >pbFJqKD@ludd.invalid wrote: >> +----------* +3,3V output >> --- >> | | R=66 ohm >> | | >> --- >> | >> ---- >> \ / CDBU00340 or similar Vf=0.6 >> \/ >> ---- >> | >> FPGA +2,5V input *----+ >> >> GND *---------------* GND >> Is it possible to use the above construction to adapt a 3,3V signal to a >> level acceptable for 2,5V FPGA Vccaux input ..? >> And thus eliminate or significantly reduce the need for a shunt resistor as >> mentioned in XAPP453 page 5 "Managing Reverse Current" ..? >> Maybe one could use R=1000 ohm to further reduce the reverse current. >> As (3.3-2.5-Vf)/I_leak = 8000 ohm. I_leak = 0.000025 Amp (ds099.pdf p58). >> The original idea was to not need any resistor at but as a component with a >> suitable Vf seems hard to find. I thought this solution will at least reduce >> the problem. >Use level-Shifters, like 74LVC8T245 or "translating bus switches" like >SN74CB3T1. They don't cost that much, require a single footprint and have >much better signal integrety. E.g. you diode solution above will have long >fall times, leading to irregular switching caused by noise and to current >surges in the input buffer caused by the input drifting slowly through the >linear region. Would it work for 6 MHz frequency as a simple solution ..? What chip do you recommend for 5,0V -> 3,3V ..?Article: 125290
On Fri, 19 Oct 2007 10:55:16 +0200, Philip Herzog <phq@arcor.de> wrote: >You could do a similar thing with a generate loop containing a "when" >statement - what's the advantage (or downside) to using a process? Multiple passes around a generate loop give rise to multiple processes, and therefore to multiple drivers if you try to drive the same signal (even conditionally) from the generate loop's body. A process, on the other hand, constructs only one driver for each signal that it writes; so you can write a signal many times within a process - starting with a "most likely" default, and then progressively mopping-up various special cases in various conditionals - and you still get only one driver. Your "software-like" description has implicitly defined the transfer function of the process. In fact, I actually *don't* think I could "do a similar thing" with generate... and conditional signal assignment, unless it were to apply hi-Z values when the condition is false. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 125291
Hi, I'm a student using Altera Quartus II v6.1 to program a Cyclone II on a DE2 development board. I'm starting to build a library of Verilog modules to re-use in future projects (mostly simple things like adders, flip-flops, etc. - I don't want to use MegaFunctions too much to avoid getting locked into Altera products) and I was wondering the best way to do this. I notice that, when I compile a project with a library folder (containing another project for, say, an adder), I get a warning that the compiler is using abc.v (or whatever the verilog file is called) as a design file although it is not included in the current project - which is what I want it to do. However, this implies that it is "compiling in" abc.v into the current project, which seems a waste. So... is there an equivalent of "object code" in C++ that I can include in my projects? So, for example, I could compile my full adder module, copy some file (not the verilog code, but a compiled/partially compiled binary file) into my library folder, and then use it in future projects without making Quartus recompile it. Based on file size, I'd say the *.sof file is the best bet, but I haven't found any information as to what this file is for. In any case, I'd like to know what all the other files are for (apart from the *.rpt files, which I know are the reports from the compiler, simulator, etc.). Can someone point me in the right direction? Thanks in advance, Allan Lewis.Article: 125292
Jonathan Bromley wrote: > A process, on the other hand, constructs only > one driver for each signal that it writes; Thanks again, Jonathan. - Philip -- Have you ever parked your motorcycle in a hotel room? (+3)Article: 125293
On Oct 19, 6:07 am, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > Hello folk! > > Hello, I have just bought Spartan 3E-1600E Microblaze Development kit > and > I am complete beginner. Really want to learn FPGA programming but have > no idea what this board is for. For example, the LEDs (all are green) > - what > they really represent?... and LCD? Can I print something on it? I have a Spartan-3E starter kit ($150 - 3S500E chip). It came with test software already loaded. It lit up LEDs and displayed stuff on the LCD. Your kit should come with a quick start quide or something similar to help you get started. -Dave PollumArticle: 125294
On Oct 19, 1:18 pm, Dave Pollum <vze24...@verizon.net> wrote: > On Oct 19, 6:07 am, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > > > Hello folk! > > > Hello, I have just bought Spartan 3E-1600E Microblaze Development kit > > and > > I am complete beginner. Really want to learn FPGA programming but have > > no idea what this board is for. For example, the LEDs (all are green) > > - what > > they really represent?... and LCD? Can I print something on it? > > I have a Spartan-3E starter kit ($150 - 3S500E chip). It came with > test software already loaded. It lit up LEDs and displayed stuff on > the LCD. Your kit should come with a quick start quide or something > similar to help you get started. > -Dave Pollum Yeah, it does. There is a small brochure called 'Start Here' where it's suggested to plug power adapter in, turn power on and self-diagnostic starts. It should finish soon and show either 'PASS' or 'FAIL' on LCD. With my board it was not so simple really coz it lasted for days. LEDs were flashing, some 'count=number' was shown on LCD and it would lasted forever..until I have realised that wrong brochure perhaps was put into box. In fact, it never finish until I press North button...Article: 125295
pbFJKD@ludd.invalid wrote: ... > Would it work for 6 MHz frequency as a simple solution ..? Without a pulldown on the cathode side of the diode, I guess it will not work at 6 MHz. > What chip do you recommend for 5,0V -> 3,3V ..? If the 5 V side also receives signals from the 3.3 Volt side, a 74LVC8T245 (or 1T or 2T) will deliver true 5 Volt CMOS signals on the 5 Volt side. This makes sense it current consumption is an issue for you. Otherwise a FET switch like the sn74cbtd3861 doesn't need a direction signal. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 125296
> I downloaded many many ieee (and other) papers on the subject. But you > know that papers are good for some purposes and books for others! > Reading a paper is good to get answer some precise question ... not > for getting state of the art. Agreed. > Papers are for researchers. But I'm searching for some books for > students and newcomers even to FPGA but who would like to get answers > concerning reconfigurable computing. One book that may be worth taking a peek at is "Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays" by Maya Gokhale and Paul Graham, ISBN-10: 0387261052, ISBN-13: 978-0387261058, Springer 2005.Article: 125297
Why is there a diode in your schematic? It is not mentioned in the app note, nor is it needed. The input clamp will prevent an overvoltage on the input, and all that is required is a series resistor to limit the total injected current into all inputs from "pushing up" the Vcco supply. Yes, a level translator is best for higher speeds, but at the speed you mentioned, a simple single resistor per input is all you need. AustinArticle: 125298
The shunt, Is only required if the Vcco is not drawing enough current, and is sourced from all IO's when they are high. Best at a slow speed is to plan on increasing the series R until the Vcco is not pushed up when inputs drive high. Or, use ONE resistor across Vcco to ground to keep Vcco from going higher than 2.5V. Why add one diode per pin, when one resistor (shunt to ground from Vcco) per FPGA only is all that you need to add? And, the answer to your question "will this circuit work" is no, as the diode is only 0.6v, and 3.3-0.6=2.7, and you may still be pushing your Vcco out of regulation when all inputs are high (and you may still need a shunt to ground on Vcco). Austin austin wrote: > Why is there a diode in your schematic? > > It is not mentioned in the app note, nor is it needed. > > The input clamp will prevent an overvoltage on the input, and all that > is required is a series resistor to limit the total injected current > into all inputs from "pushing up" the Vcco supply. > > Yes, a level translator is best for higher speeds, but at the speed you > mentioned, a simple single resistor per input is all you need. > > AustinArticle: 125299
scouselad wrote:
> So... is there an equivalent of "object code" in C++ that I can
> include in my projects? So, for example, I could compile my full adder
> module, copy some file (not the verilog code, but a compiled/partially
> compiled binary file) into my library folder, and then use it in
> future projects without making Quartus recompile it.
Not exactly.
Synthesis converts a source code module to a netlist
of vendor-specific primitives.
That netlist is routed and Fmax is checked.
It is possible to lock down a placed netlist
but this is not without it's own annoyances.
Quartus is pretty smart about not duplicating
every step on a recompile, so I just recompile.
However I spend most of my time in the
edit/simulate loop.
You can reuse source code modules, functions, templates
etc at the editor level.
-- Mike Treseler
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