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John_H <newsgroup@johnhandwork.com> wrote: >Nico Coesel wrote: >> >> Xilinx could buy such a circuit as IP and integrate it. The parts >> containing non-volatile configuration memory would benefit greatly and >> could potentially replace microcontrollers. A PLL would even be better >> and also reduces the range of crystal frequencies that need to be >> supported. 4MHz to 16MHz would be enough. >> > >Given the trouble getting a fast process to work in the `04 series, do >you *seriously* believe that just "buying IP" would be more effective >than having the extreme-silicon experts in a world-class organization >such as Xilinx design the same things? I think you are overrating Xilinx here. If they where experts on crystal oscillators, they would be selling crystal oscillators! >Most systems I'm working in have a central timing scheme where the FPGA >is nowhere near the center of the timing universe. If the more >expensive chips (PLLs, trained timing) are the only ones that can afford Probably, but I'm talking 'simple' circuits here. Imagine a microblaze with some dedicated logic to replace a microcontroller + some dedicated logic. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 124676
Don't use casex or casez at all.
When I coded an FSM using casez, XST's optimizer simply removed the entire
FSM
(and any downstream logic driven by the FSM.) In your case, I see you have
nested
case+casex statements, so XST's output was a bit better (but ultimately,
incorrect.)
Anyway, I had this problem in XST (Webpack) 9.1.03 -- I'm guessing it still
hasn't
been fixed as of XST 9.2.03?
<heinerlitz@googlemail.com> wrote in message
news:1190810372.118750.309440@d55g2000hsg.googlegroups.com...
> Hi,
>
> i have a state machine like this
>
> always @( * )
> case(state)
> IDLE:
> casex(SOME_STATEMENTS)
> {inputs}:
> next = NEXT_STATE1;
> {inputs}:
> next = NEXT_STATE3;
> default:
> next = IDLE;
> STATE1;
> casex(SOME_STATEMENTS)
...
Article: 124677On Sep 29, 5:31 am, Antti wrote: > hm, i browsed your website and found interesting things :) > and hints for more interesting thing without download links :( I have some random stuff at http://www.merlintec.com/download/ but unfortunately that doesn't include any HDL code yet. I will try to find the NTSC test next week (in VHDL) and make it available. > hm by 4 resistor you mean 4 bit 2N DA stage or something else I considered the output to be a 75 ohm resistor to ground, so just had 4 resistors (N, 2*N, 4*N and 8*N) between the FPGA pins and the RCA connector. Video quality was not a requirement for this project (the video output was only used by me during development and not by the end customers) so I didn't bother adding capacitors to filter things a bit. The DA was calculated to go from 0 to 1.5V in 0.1V steps with the FPGA i/o programmed for 3.3V TTL levels. For black and white going to 1V would be enough, but for color you have to add a sine and need to go higher. > on the test PCB I included 5 bit R-2R network, that could be little > better then 4 resistors, You would get twice the brightness levels and twice the sine amplitudes (saturations) for a total of four times as many colors. You would also reduce the noise level, which would improve the image considerably. > but if delta sigma with high clock gives nice results I would go with > it, or then 4 R version ;) It is interesting to see what the delta sigma DAC can do, but it might introduce too much jitter for the color circuits to work properly. On the other hand, real TV circuits have limited bandwidth and might just ignore all the extra noise. > ah, the results of the 2 resistor PWM greyscale also look better on TV > set then on usb capture device. > the 16 grey bars are all visible nicely. That is what normally happens. A digital video capture circuit is probably more picky about the signals it accepts. One cute trick I came up with (but did not implement in the test circuit I mentioned) was using Xilinx 16 bit shift register slices to generate phase modulated sines for the chroma circuit. For each bit you cascade two of them, where the first is always 16 bits long and feeds back to itself (at reset it gets the correct pattern to repeat) and the second one varies from 1 to 16 bits of delay. You can do a four bit generator with only 8 slices. -- JecelArticle: 124678
John Adair wrote: > Austin > > Might be worth making the suggestion to your sister grouping of GPD of > adding a dedicated oscillator crcuit to their range of products. Given > a lot of micros do that already there would be some logic in adding > such a circuit in the future to the low cost sector FPGA families. > This is fine if the expected range of frequencies is pretty narrow, as it is with microprocessors. It is a whole lot harder to do reliably when the crystal frequency can range over 2 orders of magnitude or more, and using any of a variety of different crystals. At best it is a hack, and can be off the stated crystal frequency by a fair amount. Sure, you can tune it with some variable caps, but as soon as you add tweaks like that your alignment costs will quickly swamp any parts cost savings. If you want reliable on-frequency clock, then use a purpose designed oscillator and be done with it.Article: 124679
johnp wrote: > > I'd be happy if Xilinx would simply provide a free running, loosely > spec'd clock in the FPGAs > that a designer could use for non-critical design. They could spec it > as "it runs at some > frequency between 5 and 30 MHz and will drift with temperature/ > voltage, you can't set it, > you can only use it." If they would let you use the Master Mode > programming clock inside > the design, I'd be happy. I don't care about the frequency, I just > want a free running clock. > > No crystal pads, no clock divider, just a ring oscillator within a > reasonable frequency range. > > John Providenza > Virtex4 actually has this. It isn't well documented, but it is there. Xilinx uses it for the NBTI fix in V4 devices. It does have an internal purpose, I think it was for one of the configuration download modes. I don't recall off-hand the magic incantation to use it, I'd have to find it in my design files. I think you have to make a hard macro in FPGA editor to get at it.Article: 124680
On 30 Sep., 03:24, Ray Andraka <r...@andraka.com> wrote: > johnp wrote: > > > I'd be happy if Xilinx would simply provide a free running, loosely > > spec'd clock in the FPGAs > > that a designer could use for non-critical design. They could spec it > > as "it runs at some > > frequency between 5 and 30 MHz and will drift with temperature/ > > voltage, you can't set it, > > you can only use it." If they would let you use the Master Mode > > programming clock inside > > the design, I'd be happy. I don't care about the frequency, I just > > want a free running clock. > > > No crystal pads, no clock divider, just a ring oscillator within a > > reasonable frequency range. > > > John Providenza > > Virtex4 actually has this. It isn't well documented, but it is there. > Xilinx uses it for the NBTI fix in V4 devices. It does have an internal > purpose, I think it was for one of the configuration download modes. > > I don't recall off-hand the magic incantation to use it, I'd have to > find it in my design files. I think you have to make a hard macro in > FPGA editor to get at it.- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - yes PMV primitive can be used as free running clock, but its tricky to use it as it xilinx undocumented feature AnttiArticle: 124681
looks like the website is down, any info if it that is temporary or not? AnttiArticle: 124682
On Sep 29, 4:31 pm, Nicolas Matringe <nicolas.matri...@fre.fre> wrote: > drop...@gmail.com a =E9crit :> Just interesting, how often some company i= s able to develope their own > > RISC soft-core processor for their needs, without any need to publish > > that fact or reveal any details? > > Hi > I did develop a RISC a few weeks ago, mainly for fun and to see how it's > done. The problem I am now facing is that there is absolutely *no* tool > that supports it, and I am unable to write a compiler. You may use GCC compiler with specially build back-end for your processor, that's how it done for Nios II. http://en.wikipedia.org/wiki/GNU_Compiler_Collection#Back_endArticle: 124683
> > I did develop a RISC a few weeks ago, mainly for fun and to see how it's > > done. The problem I am now facing is that there is absolutely *no* tool > > that supports it, and I am unable to write a compiler. > > You may use GCC compiler with specially build back-end for your > processor, that's how it done for Nios II.http://en.wikipedia.org/wiki/GNU_Compiler_Collection#Back_end Of course, but that's a lot more work than it sounds. You'll need to add support for you architecture to binutils. And test it. Then write a new backend to GCC. And test it. GDB also. Finally you need to port a libc, like glibc or newlib. Just _how_ much work this requires depends on how close to an existing architecture you are, eg. making a MIPS variant with just a few more instructions is a lot easier than a completely new architecture - especially if the latter has funny irregularities. For many architectures, writing the softcore implementation is much less work than writing the software tool chain support.Article: 124684
On Sep 29, 2:31 pm, Nicolas Matringe <nicolas.matri...@fre.fre> wrote: > done. The problem I am now facing is that there is absolutely *no* tool > that supports it, and I am unable to write a compiler. Of course, if you are developing many processors then using an architectural tool like LISATek may help considerably. This has the advantage of being able to direcly create an ISS and compiler. (not withstanding arguments about whether the result would be efficient, at least it is quicker than the manual route) I believe this was the reason that ARM acquired Axsys a couple of years ago. AndrewArticle: 124685
Could some one please let me know what does Walking 1's means and what is it used for? Thanks in advance, WaltersArticle: 124686
On Sat, 29 Sep 2007 12:52:23 -0000, "stephen.craven@gmail.com" <stephen.craven@gmail.com> wrote: >I can't speak about obtaining the board, but it is a very good board >with few negatives. > >However, bare in mind that the free webpack will not program the >xc2vp30 on the board. (At least WebPack 9.1 won't.) So that may mean >$2,400 in tool costs. Webpack 9.2 claims to support the XC2VP30. Also supports V5LX50, unlike 9.1 which only supports V5LX30. However it doesn't support the S3A DSP3400, while 9.1 does... Odd... - BrianArticle: 124687
On Sun, 30 Sep 2007 11:25:30 -0400, PeteS <axkz70@dsl.pipex.com> wrote: >Walters wrote: >> Could some one please let me know what does >> Walking 1's means and what is it used for? > >Walking 1s is a term used (generally) for memory testing, although it >has other applications. In more detail: use a pattern of address or data that has 0 in every bit position but one; and as you run your test, progressively shift the 1 bit along the data so that you put it on each data line in turn. Easy to implement and check, and very useful to test whether you've got all your data and address lines wired up correctly. Be careful about *where* you do your checking, to avoid missing errors in one part of the data path that are corrected later in another part because you have the same mis-wiring error in two places. Walking-1s are also good for locating "stuck-at" bits, but it's usually quicker to find them by using just two test patterns: all-1 and all-0. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 124688
On Sat, 29 Sep 2007 17:16:30 GMT, John_H <newsgroup@johnhandwork.com> wrote: >johnzulu[at]yahoo.com wrote: >> Ouch ouch ouch. I am not willing to fork out that amount for just >> testing water... Any other recommendation? >> >> I found the following on the site: >> >> Spartan-3 Starter Board >> Spartan 3E Starter Board >> Nexys-2 >> >> Any opinions on the boards? Pros and cons? >> >> Thanks, >> John > >I like the digilent Spartan-3E and 3A boards. I own a 3E500 myself, and >a 3E1600 at work. I also have the Spartan-3 PCIe board at work but >never quite got to where I needed it for development. > >The biggest question: what do you want to do with them? > >If you want memory, for instance, look at the Xilinx Memory Interface >Generator (MIG) for supported starter boards. > >- John_H What do I want to do with them? Educate myself on FPGA. Hence I like to use the following: 1) Standard JTAG interfaces from Xilinx. I would like to be able to copy some of the existing schematics from the protoboard to my designs and work with it from standard JTAG. For example: - proprietary USB-JTAG interface on the nexys boards is a no no. 2) A speedy memory interface. 3) A large space for multiple cores.... Essentially the board must have most of the capabilities for the following work: 1) Plenty of i/o and adequate memory speed. example logic analyzer 2) Enough stuff for video and audio work. 3) DSP work..... So far this is the kind of work I am aiming for on the board. So the first project on the board as exercise would be NTSC output :) Regards, JohnArticle: 124689
>> Could some one please let me know what does Walking 1's means and what >> is it used for? >Walking 1s is a term used (generally) for memory testing, although it >has other applications. "Walking ones" refers to a set of data patterns where, in each data word, a single bit is set to one and the rest to zero. Similarly, "walking zeroes" refers to a set of data patterns where, in each data word, a single bit is set to zero and the rest to one. Such sets of data patterns have been used to test (or diagnose) memory faults. For example, where the data width is eight bits, we may try to write a set of patterns: 00000001 00000010 00000100 00001000 (The "one" bit "walks" along the data word) 00010000 00100000 01000000 10000000 and, in each case, read the same memory location to check that the same data is recovered. The choice of such patterns is based on their simplicity and on the ease of diagnosing (from the recovered data) any faults which they detect. They are most useful for the detection and diagnosis of interconnection faults where two data signals are shorted together (or show "crosstalk"). Other data patterns may be chosen according to the type of fault thought to be likely with a particular memory technology. For example, in the case of magnetic "core" memory, certain patterns are chosen on the basis that they are considered to be the most likely to expose faults in that type of memory. Such data patterns may be referred to as "disturb" patterns and may extend over several data words. Note that a simple "walking ones" or "walking zeroes" pattern is usually of limited use in detection of memory addressing faults (e.g. where a memory address signal is shorted to a fixed logic level or two memory address signals are shorted together). In practice, almost all memory faults are "hard" failures, which can be identified simply by writing all ones or all zeroes to each address. "Soft" failures can be identified and corrected in working systems by use of error-correction (e.g. Hamming) codes, without disturbance of the running program. Ideally, where this is done, the occurrence of a corrected or uncorrected fault is notified (by interrupt) to the system error handler, so that appropriate action can be taken. For example, the system error handler will usually begin the procedure of logging the fault. For these reasons, walking ones and walking zeroes are of limited use, except to detect shorted data signals in manufacturers' tests. MikeArticle: 124690
> What do I want to do with them? > Educate myself on FPGA. Hence I like to use the following: > 1) Standard JTAG interfaces from Xilinx. I would like to be able to > copy > some of the existing schematics from the protoboard to my designs > and work with it from standard JTAG. For example: > - proprietary USB-JTAG interface on the nexys boards is a no no. That's easy if you are satisfied with the standard Xilinx LPT jtag cable. The jtag connector is onboard. The schematic is here: http://www.xilinx.com/support/programr/jtag_cable.pdf The user guide is here: http://www.xilinx.com/bvdocs/publications/ds097.pdf Device family support and miscelanous: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-PC4 Vasile > 2) A speedy memory interface. > 3) A large space for multiple cores.... > > Essentially the board must have most of the capabilities for the > following work: > > 1) Plenty of i/o and adequate memory speed. example logic analyzer > 2) Enough stuff for video and audio work. > 3) DSP work..... > > So far this is the kind of work I am aiming for on the board. So the > first project > on the board as exercise would be NTSC output :) > > Regards, > John- Hide quoted text - > > - Show quoted text -Article: 124691
Walters wrote: > Could some one please let me know what does Walking 1's means and what > is it used for? > > Thanks in advance, > Walters > Walking 1s is a term used (generally) for memory testing, although it has other applications. Cheers PeteSArticle: 124692
You can't see it directly. For early phases of design I make sure caches stay turned off and just follow memory fetches. It will be a mix of instructions and data of course, but it's better than nothing. Note 99% of my PPC simulation experience has been with Freescale's MPC8245 full-functional model. That chip does have a neat feature where some additional debugging status pins help you trace the execution. motty wrote: > I am simulating the PowerPC and can't find the damn program counter. > I have looked in the reference manuals that come with the EDK but > can't find any helpful info!! > > Anyone know where to point me? I am using ModelSim by the way. > > Thanks! >Article: 124693
<theanonymous83@gmail.com> wrote in message news:1191077233.087547.325100@w3g2000hsg.googlegroups.com... > On Sep 29, 3:56 pm, "Symon" <symon_bre...@hotmail.com> wrote: > > Hi Symon, > > Yes, were are tough to look for information on the Internet. I am a > frequent visitor at cwjobs, eures, etc. It seems that there is plenty > of jobs but: > 1. most of them are dupes (an agency is posting the same offer every > day) > 2. yet I have to find one that does not require commercial experience > (I am not browsing all offers, just the one with lowest salary > proposals, as these are usually entry/junior jobs; I agree, I might > have missed the post I am looking for). > > Don't get me wrong. I am not whining or begging. Moreover I am not > asking anyone to look for a job for me. I simply asked If anyone knows > about entry/trainee job out there, that is not offered via job boards. > > Still, thanks for response. > Yeah, sorry, suggesting Google was a bit glib. It seems daunting starting out, but I'm sure you'll be ok! John M., makes a good point, you might be able to get something through your Uni's career service. That worked for me (if I can remember that far back), but in the end my first 'proper' job was advertised in my local newspaper. I guess you tried trawling big companies' websites. They often have graduate programs. Good luck! Syms.Article: 124694
Hi , Currently i am working with a Semiconductor Design House as a PDK Application Engineer. My primary job function is to support the design teams with PDK(this icludes, DRC/LVS, LPE ,models, techfiles..etc) related issues. I have been working in this filed for almost 3 years. I am interested in exploring Synthesis, Place & Route more than compared to what i am doing right now. Recently I got an opportunity in FPGA domain. This new job offers exposure to synthesis and P&R in FPGA domain. I dont have much knowledge about FPGA, i am not sure how different will it be from the ASIC world. Will this add to my earlier work experience that i have in Semi Custom/Asic domain ? To be more specific, will a Designer who has been working on FPGAs be acceptable in ASIC world, will he have the almost same market value in ASIC domain ? If i switch then will my earlier wrk exp be scraped. If anybody could help me evaluate/(provide some feedback) on these concerns, it would be highly appreciated. That would help me make a right move for my career. Thanks & Regards LuckyArticle: 124695
On Tue, 11 Sep 2007 13:59:16 -0700, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote: >How do you get messages from comp.arch.fpga archives? > >Google brings up headings that I may want to read, however, >when I click on those headings I go to the archives that >are listed by year and month. There isn't a clear way >to find the message that I wanted to read. > >Brad Smallridge >Ai Vision Google indexes both the article pages, and the month indexes, and the author indexes at http://www.fpga-faq.com/archives/index.html Unfortunately, when it returns searc results, it sometimes gives the index pages, rather than the article pages. I have not found a way to avoid this. What you can do, once you get to one of the index pages, is just do a text search on the page (ctrl-f) to find a link to the related article page. From there you can follow the articles by topic, by author, or cronologically. Cheers, Philip Freidin =================== Philip Freidin philip.freidin@fpga-faq.org Host for WWW.FPGA-FAQ.ORGArticle: 124696
I have a design which uses around 80% of an XC5V330. Synthesis to EDIF is via Synplicity and it's pretty quick. MAP is another story. It takes around six hours and uses upwards of 6GByte (not a typo) of memory. Actually MAP claims to have used 6GB, but Linux/LSF reports that MAP has used 12GB. The machine has 16GB installed. Since the Synplicity EDIF is essentially a bunch of LUT definitions, I cannot see what MAP could be doing that needs this immense slug of memory and time. The target speed is 20MHz, which is DC on an XC5V part, and Synplicity believes it has achieved it. Are there any hints and tips out there for switches or whatever that could cut the processing resources? For the future, Smartguide looks good. But first the design has to be stable.Article: 124697
On Sep 30, 2:06 am, Andrew Burnside <andrew.burns...@sli- institute.ac.uk> wrote: > Of course, if you are developing many processors then using an > architectural tool like LISATek may help considerably. > This has the advantage of being able to direcly create an ISS and > compiler. (not withstanding arguments about whether the result would > be efficient, at least it is quicker than the manual route) > I believe this was the reason that ARM acquired Axsys a couple of > years ago. As long as the processor matches the underlying assumptions of LISATek. Presumedly, a classic style MIPS-like RISC processors is fairly trivial, but how about a, say, VLIW? Or a true exotic like IA64? Or a graph reduction machine like TRIPS? A massively parallel machine like RAW? TommyArticle: 124698
On Sep 30, 2:24 pm, Ken Ryan <newsr...@leesburg-geeks.org> wrote: > You can't see it directly. > > For early phases of design I make sure caches stay turned off and just > follow memory fetches. It will be a mix of instructions and data of > course, but it's better than nothing. > > Note 99% of my PPC simulation experience has been with Freescale's > MPC8245 full-functional model. That chip does have a neat feature where > some additional debugging status pins help you trace the execution. > > > > motty wrote: > > I am simulating the PowerPC and can't find the damn program counter. > > I have looked in the reference manuals that come with the EDK but > > can't find any helpful info!! > > > Anyone know where to point me? I am using ModelSim by the way. > > > Thanks!- Hide quoted text - > > - Show quoted text - Check out answer records 17088 and 17013. Unfortunately the example file in the answer record will not compile with ModelSim 6.2f. Got a webcase open for that.Article: 124699
Tommy Thorn wrote: > As long as the processor matches the underlying assumptions of > LISATek. Presumedly, a classic style MIPS-like RISC processors is > fairly trivial, but how about a, say, VLIW? Or a true exotic like > IA64? Or a graph reduction machine like TRIPS? A massively parallel > machine like RAW? > Looking back at what happened, LISA as part of Axys went to ARM. LISATek became Coware Processor Designer. >From Coware's latest webpage: Processor Designer is used to develop a wide range of processor architectures, including architectures with DSP-specific and RISC- specific features as well as SIMD and very long instruction word (VLIW) processors Obviously, such tools have their constraints. However, the OP asked about developing soft processor cores for FPGA.
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