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On Sep 25, 12:00 pm, jinke...@hotmail.com wrote: > Sorry to hear you had a bad experience. I would like to help now if I > can. First, Quartus II Subscription Edition includes a free 30-day > trial (no license needed - just download and install). This should get > you up an running with compiling a 2S60. Compiling perhaps, but it explicitly says no programming file support, and the problem is that were at the point in the project where we need to program real devices. > Second, our sales team should > be able to cut you an additional 60-day evaluation license. I'm happy > to do so now - just email me your NIC ID. I can also help you with > license you purchased. Fortunately our distributor seems to have managed to sort out the difference in timeframe between emailing a temporary license and sending a box with a CD and dongle, as a result of which I've been able to program the device and get signals through it.Article: 124526
On Sep 25, 9:31 pm, Gabor <ga...@alacron.com> wrote: > On Sep 25, 2:12 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > On Sep 25, 8:51 am, Wei Wang <camww...@gmail.com> wrote: > > > > All I can find is a one-page specification of "Kingston > > > KVR100X64C2/128", but I do not know about the input and output > > > interface of this SDRAM, e.g., what are the input and output signals, > > > and how the input and output signals are wired into each Synchronous > > > DRAM (Infineon HYB39S128800CT-8) module. Many thanks, -Wei > > > Hi, > > Go to Infineon or Micron, or Samsung to search for similar SDRAM > > chips. > > > Kingston is not a chip manufacture, but a DIMM manufacture. > > > All SDRAM chips are almost same with Micron having the tighest > > requirements. > > > You may print Micron 128800CT-8 SDRAM to see if there is a document > > over there. Maybe they are all out of date. > > > Weng > > A good source for DIMM data is JEDEC. On their website, jedec.org, > you > can find standard connections for all standard DIMM types. If you > know > the type of chip and number of chips on your module you can generally > narrow down the choices to one JEDEC standard. > > Their website is a little hard to navigate, but the search feature > generally gets you to the information you need, and all of the > standards > include reference schematics so you can see the chip connections. > > HTH, > Gabor- Hide quoted text - > > - Show quoted text - Thanks Tianxiang and Gabor for your inputs, but I was a little confused with the description in Kingston KVR100X64C2/128 "The components on this module include sixteen 8M x 8-bit (2M x 8-bit x 4 Bank / PC100 components) SDRAM in TSOP packages", but when I look at Infineon HYB39S128800CT-8, the chip has four banks inside, each bank is 8 bits wide with 4M address, so each chip is 4Mx8bitx4, which is 16MB. As the Kingston is 128 MB big and it has 8 Infineon chips fitted, so I don't see why the KVR specification says the module contains sixteeen 8Mx8-bit SDRAM. Should it be 8 16Mx8-bit SDRAM, then I could not find this in JEDEC standard while I could find the JEDEC standard for sixteen 8Mx8bit? Could somebody give me some hints on this, thanks!!!Article: 124527
On Sep 25, 9:00 am, jinke...@hotmail.com wrote: > On Sep 25, 6:51 am, cs_post...@hotmail.com wrote: > > > > > Ordered a license for Quartus a month ago. Order is processed, rep > > says she needs NIC ID and host ID from PC, we explain that a new PC is > > on order and we will need to license software to old machine now, then > > move it. She says we have to wait. > > > Okay, not good as a project is already behind schedule, but can live > > with that. > > > New computer comes in. Get rep to clarify that host ID means volume > > serial number. Provide it. No response. Wait four days and ask what > > happened - told that LICENSE CANNOT BE ISSUED FOR AT LEAST ANOTHER > > FOUR DAYS. > > > What the ???? > > > I have work to do here, and you guys can't email me a tiny text file ? > > > Going back to Xilinx... project is already halfway working on their > > eval board, which has a chip supported by their web version. > > Mike, > > Sorry to hear you had a bad experience. I would like to help now if I > can. First, Quartus II Subscription Edition includes a free 30-day > trial (no license needed - just download and install). This should get > you up an running with compiling a 2S60. Second, our sales team should > be able to cut you an additional 60-day evaluation license. I'm happy > to do so now - just email me your NIC ID. I can also help you with > license you purchased. > > Happy to get you up and runnning today. > > Jordon Inkeles > Altera Software Marketing > jinke...@altera-nospam-.com <remove the -nospam-> Somebody PLEASE explain to me why a license key is needed for software that does one thing only: implement designs in the vendor's specific logic family. I can't use Altera's software to do Xilinx chips, nor can I use it to play Doom 3, nor can I use it to make my morning coffee. So why why why why why do the FPGA vendors insist on license keys for their tools? -aArticle: 124528
"Andy Peters" <google@latke.net> wrote in message news:1190763448.554163.146770@57g2000hsv.googlegroups.com... > > I can't use Altera's software to do Xilinx chips, nor can I use it to > play Doom 3, nor can I use it to make my morning coffee. So why why > why why why do the FPGA vendors insist on license keys for their > tools? > > -a > Hi Andy, I guess economics? The FPGA company has to pay to develop their silicon and to develop their software. As the customer, we have to pay for both of these, one way or another. If they gave the software away, they'd have to charge more for the devices. This would be unfair to customers that use a lot of devices in their products over customers that use fewer parts. HTH., Syms.Article: 124529
Weng Tianxiang wrote: > "Shift registers can be counted as a state machine only when only one > bit is set or reset among all its bits. Otherwise it cannot be counted > as a state machine." > > "I don't understand this restriction at all. > B.S. For example, a shift register can be used in a bargraph manner so that the states are 000001 000011 000111 001111 011111 111111 This has an advantage over the one-hot shift register state machine you described in that it has fewer terms feeding each register. That can make a big difference in the maximum clock rate of the state machine.Article: 124530
On Sep 25, 5:06 pm, Ray Andraka <r...@andraka.com> wrote: > Weng Tianxiang wrote: > > "Shift registers can be counted as a state machine only when only one > > bit is set or reset among all its bits. Otherwise it cannot be counted > > as a state machine." > > > "I don't understand this restriction at all. > > B.S. For example, a shift register can be used in a bargraph manner so > that the states are > > 000001 > 000011 > 000111 > 001111 > 011111 > 111111 > > This has an advantage over the one-hot shift register state machine you > described in that it has fewer terms feeding each register. That can > make a big difference in the maximum clock rate of the state machine. Hi Ray, OK, thank you for your example. Your shift register is a state machine if we define different bit patterns appeared in your example as individual states. I have changed my mind to accept non one-hot encoding for shift registers based on glen's suggestion. My state machine definition is still right without any violations with your example. WengArticle: 124531
Symon wrote: > If they gave the software away, they'd have to > charge more for the devices. No - the money they make off development tools is a drop in the ocean compared to that made from selling silicon. I - for the life of me - cannot work out why they'd even _want_ to charge for development tools. They're in the business of moving silicon - and I would've thought the _best_ way to do that is get as many people as possible programming that silicon?!? And the best way to do that is give away free development tools. Ditto for the obscene price they charge for USB Blasters... I guess their argument is that the web edition is free - but that only goes so far, as the OP has discovered. We need an OQPE program (One Quartus Per Engineer)! ;) Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 124532
>I guess economics? The FPGA company has to pay to develop their silicon and >to develop their software. As the customer, we have to pay for both of >these, one way or another. If they gave the software away, they'd have to >charge more for the devices. This would be unfair to customers that use a >lot of devices in their products over customers that use fewer parts. They have to pay for the software development anyway. I think the economics term is "sunk costs". Support is a different matter. It might make sense to give away the software and charge for support. But then, they would get complaints about buggy software or lousy documentation. Another argument is that if you are buying a lot of chips, the cost of software is not important to your total cost. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124533
Mark McDougall wrote: > Symon wrote: > >> If they gave the software away, they'd have to >> charge more for the devices. > > No - the money they make off development tools is a drop in the ocean > compared to that made from selling silicon. > > I - for the life of me - cannot work out why they'd even _want_ to charge > for development tools. They're in the business of moving silicon - and I > would've thought the _best_ way to do that is get as many people as > possible programming that silicon?!? And the best way to do that is give > away free development tools. > > Ditto for the obscene price they charge for USB Blasters... > > I guess their argument is that the web edition is free - but that only > goes so far, as the OP has discovered. > > We need an OQPE program (One Quartus Per Engineer)! ;) > > Regards, Have you ever priced support? With the software license comes an expectation for quick, accurate support. If anybody and their brother got support free of charge, the cost to support the hobbyist in designs becomes severe. The free tools don't come with bottomless phone support as far as I'm aware. Serious users need serious support. They could go to a pricing model where the tools are free but support costs. Not many businesses are happy to pay for this model since "the product should be doing everything I want in the first place so why should I pay?" - John_HArticle: 124534
Hi, I'm making my way through the Virtex 4 user guide trying to get to grips with FPGAs, although I'm only a few pages in and already have a few questions: - Why are there 32 global clock lines for a chip? It seems quite a lot... - It states 8 global clock lines can be used in a single region, although why would you want 8 lines going into a single region? How does the region then know which clock signal to use? - If each region is running at a different clock speed, how is communication between regions (and so different clock speeds) handled? My apologies, I think that I'm asking questions which I should already know the answers to before I venture into the FPGA world. Looking at the previous questions in this newsgroup, these questions seem out of place; perhaps somebody could suggest some resources (books. etc...) to answer what appear to be basic questions that I have. Thanks for your time, Nick.Article: 124535
> - Why are there 32 global clock lines for a chip? It seems quite a > lot... Because it looks better than the 16 or 24 that the opposition offer! Realistically, a design is unlikley to use anywhere near 32 clocks, though the global clock lines can also be used for other global signals if you so wish. I guess one case where lots of clocks would be needed is if you have a number of indepdendent serial channels, each with a recovered clock. > - It states 8 global clock lines can be used in a single region, > although why would you want 8 lines going into a single region? How > does the region then know which clock signal to use? Which clock is used is determined entirely by your design. All this feature does is ensure that in any region (quadrant?) of the chip one can mix logic using up to eight different clocks. The place and route tools typically handle the distribution of logic around the chip for you. > - If each region is running at a different clock speed, how is > communication between regions (and so different clock speeds) handled? Carefully ;-) If you Google something like "multiple clock domains", or "crossing clock domains" then you should find a whole wealth of information on the subject. Typically you will need FIFOs or dual port RAM for data paths and synchronizing flip-flops for control paths.Article: 124536
On Sep 25, 4:30 pm, dudesinmex...@gmail.com wrote: > I am looking for open source software for logic minimization (a la > espresso) targeted to a lookup table based architecture that can take advantage > of six inputs LUTs (as you can imagine I have in mind a LUT6/Virtex 5 > implementation). Is there such a beast? Howdy, You peaked my curiosity. Could you explain why you need this? Synthesis tools do this for you, and with probably much greater speed, accuracy, and intelligent trade-off's than you'd be able to do manually - especially when you start considering registers rather than just pure combinational logic. Thanks, MarcArticle: 124537
On Sep 26, 4:42 am, "David Spencer" <davidmspen...@verizon.net> wrote: > <snip> Thank you very much for the quick reply. :)Article: 124538
>Have you ever priced support? >With the software license comes an expectation for quick, accurate >support. If anybody and their brother got support free of charge, the >cost to support the hobbyist in designs becomes severe. The free tools >don't come with bottomless phone support as far as I'm aware. Serious >users need serious support. I've been on the other end of support at time. My memory is that a smart user who provides good test cases is worth a lot. Support for a (possibly large) group of users with an internal wizard who filters dumb questions and relays the interesting ones is a lot different from the case where the vendor has to process the dumb ones too. I don't know how to put that into a contract. >They could go to a pricing model where the tools are free but support >costs. Not many businesses are happy to pay for this model since "the >product should be doing everything I want in the first place so why >should I pay?" I've seen several comments about costs of things. One key idea is predicting the cost. Bean counters would rather pay a guaranteed 2X rather than a probable 1X with a chance of 3X. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 124539
Hi, > - Why are there 32 global clock lines for a chip? It seems quite a > lot... Yes, this may seem high at first. And it's indeed unlikely a design will use all of them. But that's on purpose, so that it doesn't become a limitation. In a real life design, the number of BUFG tends to grow quickly. Let's take a "simple" design where you receive a gigabit network flow, store it in DDR2, do some processing an display the result on a DVI screen : - The gigabit ethernet is gonna take you 3 BUFG, one for the RX clock, one for the TX clock and one for your reference clock. - The DDR2 controller can take up to 5 BUFG (clock 125 MHz, clock 250 MHz, each one in phase 0 and in phase 90 + 1 BUFG for the IDELAY 200MHz clock) ... - The processing might be done at another higher frequency, so that's another BUFG - The DVI will also need it's BUFG. So you see I'm already at 10 BUFG with a not so complex design ... > - It states 8 global clock lines can be used in a single region, > although why would you want 8 lines going into a single region? How > does the region then know which clock signal to use? Each synchronous element in a region (FF, BRAM, ...) can choose independently what clock to use from those 8 lines. > - If each region is running at a different clock speed, how is > communication between regions (and so different clock speeds) handled? You can cross clock inside region too ... and when you need to cross clock domain, you need to be careful. Depending on what must cross, the techniques vary ... SylvainArticle: 124540
Weng, you are free to invent as many technical and mathematical constructs as you like. BUT: It is utterly stupid to use the same name for it as a well established construct. Finite State Machines are extremely well understood since decades. http://en.wikipedia.org/wiki/Finite_state_machine And I can assure you: In digital electronics anything that has state is a state machine. In general: - State machines do not need to have a reset. There are machines that return to the reset state if a certain input sequence is applied. I posted links to papers about that, which you apperently ignored. Any FPGA around has a state machine that works without reset: The JTAG- controller. - Names in state machine do not need to have names. - State machines can be combined to larger machines. These are still state machines, but the states are not mutual exclusive anymore. - In complexity therory an important class of state machines are non deterministic state machines. These can be in mutliple states at the same time. Quantum computing provides a real world implementation for another type of state machines that are in multiple states at the same time. - While state machines with a single state are not very useful, theory becomes a lot simpler if you still allow them to be state machines. This means that for the well establish name "State Machine" ALL OF YOUR ASSUMPTIONS ARE FALSE! Please find a new name for the strange thing that you are talking about. And please: Listen to people, and believe them. Most of this has been posted before and you ignored it. You are extraordinarily stubborn. As far as your original question goes: A set of state memories (flip-flops, memory cells) can be more or less arbitrarily partitiones into state machines. The extremes beeing one machine per state bit, or one big machine for the whole chip. Both extremes often are not useful. What you described is a central controller updating a set of state machines in memory. It is valid to call that a set of state machines. But if you allow for that construct, a software implementation of Conways game of live easily beats your example by orders of magnitude. You have two state bits for each pixel and a central controller updating the states of the machines. Kolja Sulimma On 21 Sep., 21:26, Weng Tianxiang <wtx...@gmail.com> wrote: > It must meet state machine requirements: > A state machine can be defined in such a scientific way: > 1. All states in a state machine have their own names; > 2. All states in a state machine are mutually exclusive; > 3. Only one state is active in any cycle; > 4. The number of states in a state machine must be 2 or more; > 5. There must be clear asynchronous or a synchronous reset signal, or > hidden procedure for the state machine. After their assertion or initialization > the state machine must be in known initial state.Article: 124541
Andy Peters <google@latke.net> wrote: ... > Somebody PLEASE explain to me why a license key is needed for software > that does one thing only: implement designs in the vendor's specific > logic family. Because Altera buys part of the tool chain from third parties. These third parties want to see real money for each installation and require the dongle. Xilinx own all parts of the ISE Webpack Toolcahin and so can have a relaxed licensing scheme. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 124542
"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message news:PIKdnXcxULmDJ2TbnZ2dnUVZ_t_inZ2d@megapath.net... > >>I guess economics? The FPGA company has to pay to develop their silicon >>and >>to develop their software. As the customer, we have to pay for both of >>these, one way or another. If they gave the software away, they'd have to >>charge more for the devices. This would be unfair to customers that use a >>lot of devices in their products over customers that use fewer parts. > > They have to pay for the software development anyway. > I think the economics term is "sunk costs". > Hi Hal, Well, I think your resoning is maybe flawed. They have to pay for the engineering design on the silicon 'anyway'. Yet you're not asking for devices which don't take that NRE cost into account. Someone has to pay for the costs, sunk or otherwise. Cheers, Syms.Article: 124543
"Mark McDougall" <markm@vl.com.au> wrote in message news:46f9aa72$0$4534$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > Symon wrote: > >> If they gave the software away, they'd have to >> charge more for the devices. > > No - the money they make off development tools is a drop in the ocean > compared to that made from selling silicon. > Hi Mark, I guess you have some data to back up your statement? I'm sure you wouldn't just spout off on usenet without doing some research. ;-) I bet you spent the couple of minutes I just did to find this post:- http://groups.google.com/group/comp.arch.fpga/msg/1019f19f4aef68ea where Austin mentions that Xilinx has 250k seats installed. Or this news release from 2003 with 175k seats:- http://www.xilinx.com/prs_rls/software/03113ise6.1.htm Now, I guess that includes a lot of free seats from the web download thingy, but the press release is talking about seats 'sold'. I would contend that this is more than a 'drop in the ocean'. Cheers, Syms. p.s. John and Hal make some good points about support, which I agree with.Article: 124544
Symon wrote: > "Mark McDougall" <markm@vl.com.au> wrote in message > news:46f9aa72$0$4534$5a62ac22@per-qv1-newsreader-01.iinet.net.au... > >>Symon wrote: >> >> >>>If they gave the software away, they'd have to >>>charge more for the devices. >> >>No - the money they make off development tools is a drop in the ocean >>compared to that made from selling silicon. >> > > Hi Mark, > I guess you have some data to back up your statement? I'm sure you wouldn't > just spout off on usenet without doing some research. ;-) I bet you spent > the couple of minutes I just did to find this post:- > http://groups.google.com/group/comp.arch.fpga/msg/1019f19f4aef68ea > where Austin mentions that Xilinx has 250k seats installed. Or this news > release from 2003 with 175k seats:- > http://www.xilinx.com/prs_rls/software/03113ise6.1.htm > Now, I guess that includes a lot of free seats from the web download thingy, > but the press release is talking about seats 'sold'. I would contend that > this is more than a 'drop in the ocean'. [ "Last quarter, Xilinx saw a sequential 33% increase in design seats sold raising our cumulative number of installed software seats to 175,000 users,"] Be very careful when reading press releases! :) Sold only applies to a 3% increase, at no stage do Xilinx reveal the actual sold number, but they certainly try to create the impression, they have 175,000 users. Oops, even there, careful reading shows 'installed' - and I am sure the many copies I have here, and counted many times in that 175,000, and not just once. Microchip use a similar 'elasticity' with their development tools stats. A better number (that does not multiple-count SW versions), can sometimes be found in the Annual reports, - this from Altera's 2004 one as an example ["Altera serves over 14,000 customers in four primary market segments: communications, industrial, consumer, and computer and storage.] Many of those will be using free web-tools, and yes, a few will be using multiple seats of keyed/paid tools. -jgArticle: 124545
On Sep 25, 6:48 pm, Wei Wang <camww...@gmail.com> wrote: > On Sep 25, 9:31 pm, Gabor <ga...@alacron.com> wrote: > > > > > On Sep 25, 2:12 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > On Sep 25, 8:51 am, Wei Wang <camww...@gmail.com> wrote: > > > > > All I can find is a one-page specification of "Kingston > > > > KVR100X64C2/128", but I do not know about the input and output > > > > interface of this SDRAM, e.g., what are the input and output signals, > > > > and how the input and output signals are wired into each Synchronous > > > > DRAM (Infineon HYB39S128800CT-8) module. Many thanks, -Wei > > > > Hi, > > > Go to Infineon or Micron, or Samsung to search for similar SDRAM > > > chips. > > > > Kingston is not a chip manufacture, but a DIMM manufacture. > > > > All SDRAM chips are almost same with Micron having the tighest > > > requirements. > > > > You may print Micron 128800CT-8 SDRAM to see if there is a document > > > over there. Maybe they are all out of date. > > > > Weng > > > A good source for DIMM data is JEDEC. On their website, jedec.org, > > you > > can find standard connections for all standard DIMM types. If you > > know > > the type of chip and number of chips on your module you can generally > > narrow down the choices to one JEDEC standard. > > > Their website is a little hard to navigate, but the search feature > > generally gets you to the information you need, and all of the > > standards > > include reference schematics so you can see the chip connections. > > > HTH, > > Gabor- Hide quoted text - > > > - Show quoted text - > > Thanks Tianxiang and Gabor for your inputs, but I was a little > confused with the description in Kingston KVR100X64C2/128 "The > components on this module > include sixteen 8M x 8-bit (2M x 8-bit x 4 Bank / PC100 components) > SDRAM in TSOP packages", but when I look at Infineon HYB39S128800CT-8, > the chip has four banks inside, > each bank is 8 bits wide with 4M address, so each chip is 4Mx8bitx4, > which is 16MB. As the Kingston is 128 MB big and it has 8 Infineon > chips fitted, so I don't see why the KVR specification says the module > contains sixteeen 8Mx8-bit SDRAM. Should it be 8 16Mx8-bit SDRAM, then > I could not find this in JEDEC standard while I could find the JEDEC > standard for sixteen 8Mx8bit? Could somebody give me some hints on > this, thanks!!! The data sheet also notes: "Note: The module defined in this data sheet is one of several configurations available under this part number. While all configurations are compatible, the DRAM combination and/or the module height may vary from what is described here." I'm not sure what they consider "compatible" in the case of modules with different memory organizations under the same part number, but I also noticed that they offer "Free Technical Support". Perhaps someone at Kingston can address the issue? Regards, GaborArticle: 124546
Hi,
i have a state machine like this
always @( * )
case(state)
IDLE:
casex(SOME_STATEMENTS)
{inputs}:
next = NEXT_STATE1;
{inputs}:
next = NEXT_STATE3;
default:
next = IDLE;
STATE1;
casex(SOME_STATEMENTS)
{inputs}:
next = STATE2;
{inputs}:
next = STATE4;
default:
next = STATE1;
default:
next = IDLE;
In functional simulation everything is fine. After XST synthesis
magical things happen. THe FSM just doesn't work correctly anymore
logically. Some inputs are misinterpreted causing the FSM to jump into
wrong states. It's ridiculous. The output signals for the specific
states however are correct.
FSM encoding USER did not help however disabling FSM encoding by
setting it to NONE in the XST properties helped. Now the design runs
fine after XST. It is however 3 MHz slower. Worse is that you cannot
trust the XST anymore at all.
Is this a known problem? Maybe its just the coding style which
confuses the XST.
Article: 124547heinerlitz@googlemail.com wrote: > Hi, > > i have a state machine like this [snip] > In functional simulation everything is fine. After XST synthesis > magical things happen. THe FSM just doesn't work correctly anymore > logically. [snip] > Is this a known problem? Maybe its just the coding style which > confuses the XST. > How about that old classic: Are your inputs synchronized to the state machine clock? --- Joe Samson Pixel VelocityArticle: 124548
> How about that old classic: Are your inputs synchronized to the state > machine clock? Hi yes all inputs are synchornized to the FSM clock. I can further add that I am doing a non timing anotated simulation.Article: 124549
On Sep 26, 7:39 am, "heinerl...@googlemail.com"
<heinerl...@googlemail.com> wrote:
> Hi,
>
> i have a state machine like this
>
> always @( * )
> case(state)
> IDLE:
> casex(SOME_STATEMENTS)
> {inputs}:
> next = NEXT_STATE1;
> {inputs}:
> next = NEXT_STATE3;
> default:
> next = IDLE;
> STATE1;
> casex(SOME_STATEMENTS)
> {inputs}:
> next = STATE2;
> {inputs}:
> next = STATE4;
> default:
> next = STATE1;
> default:
> next = IDLE;
>
> In functional simulation everything is fine. After XST synthesis
> magical things happen. THe FSM just doesn't work correctly anymore
> logically. Some inputs are misinterpreted causing the FSM to jump into
> wrong states. It's ridiculous. The output signals for the specific
> states however are correct.
>
> FSM encoding USER did not help however disabling FSM encoding by
> setting it to NONE in the XST properties helped. Now the design runs
> fine after XST. It is however 3 MHz slower. Worse is that you cannot
> trust the XST anymore at all.
>
> Is this a known problem? Maybe its just the coding style which
> confuses the XST.
You have simplified your example code to the point that you do not
even show the clock. The sample code describes an asynchronous state
machine, which I doubt is what you want based on other messages.
Instead of:
always @( * )
Do you have:
always @( posedge clk)
If not, that is a problem. If you do, I would suggest posting a more
complete example.
Regards,
John McCaskill
www.fastertechnology.com
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