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Messages from 124475

Article: 124475
Subject: Re: help! ACTEL PROASIC PLUS clock buffer
From: Thomas Stanka <usenet_10@stanka-web.de>
Date: Sun, 23 Sep 2007 23:00:15 -0700
Links: << >>  << T >>  << A >>
On 21 Sep., 20:09, Mike Treseler <mike_trese...@comcast.net> wrote:
> merche wrote:
> > GL2 is the name instanciated, the entity is a GL33. I put in the
> > global pin, but in the chipplanner I see that don=B4t use de global
> > macro, becouse the tool (sinplicity) put other signal. the edif
> > netlist  is only for the pins (external pad)?
>
> If you have Synplicity why not let it
> infer the buffers? You shouldn't
> have to instance any buffers in your code.

Thats right. Unfortunately I don't know how to force synplicity to
choose the right buffer without constraining it in the code for those
designs synplicity chooses the wrong buffer.
In the APA technology you have global nets for inputs with high fan-
out like clock or reset. But sometimes you have to specify which four
nets should be threated as global nets.

bye Thomas



Article: 124476
Subject: Re: help! ACTEL PROASIC PLUS clock buffer
From: Thomas Stanka <usenet_10@stanka-web.de>
Date: Sun, 23 Sep 2007 23:05:49 -0700
Links: << >>  << T >>  << A >>
On 21 Sep., 12:09, merche <dora...@gmail.com> wrote:
> On Sep 21, 7:19 am, Thomas Stanka <usenet...@stanka-web.de> wrote:
>
>
>
> > On 20 Sep., 11:36, merche <dora...@gmail.com> wrote:
>
> > > On Sep 20, 7:26 am, Thomas Stanka <usenet...@stanka-web.de> wrote:
>
> > > > On 19 Sep., 17:56, merche <dora...@gmail.com> wrote:
>
> > > > > Hi!, I have a big problem:
>
> > > > > I use Libero to Proasic Plus Family of Actel. My FPGA has got 4 g=
lobal
> > > > > pin (4 GL macro), I need put a clock in a global buffer but I can=
=B4t
> > > > > because I have  others signals with highest fanout. what can I do?
>
> > > > Explain your real problem. Do you need more global inputs or is it a
> > > > problem of synthesis? Then instantiate a GL Buffer for the clk in y=
our
> > > > code
>
> > > thanks Thomas Stanka! But...
>
> > > In my code I have instantiated a GL Buffer (is a fast clock). But in
> > > the synthesis: the log say...
>
> > > Automatic dissolve during optimization of view:work.w_r9(w_r9) of
> > > GL2(GL)
>
> > There exist no GL2 in the APA library AFAIK. Try GL25 instead.
> > Instantiating the clk-Buffer in code should work for Synplify.
>
> > If nothing helps, you could edit the edif netlist to get a clk-buffer
> > for the clk input, but this should be done _very_ carefully.
>
> > bye Thomas- Hide quoted text -
>
> > - Show quoted text -
>
> GL2 is the name instanciated, the entity is a GL33. I put in the
> global pin, but in the chipplanner I see that don=B4t use de global
> macro, becouse the tool (sinplicity) put other signal. the edif
> netlist  is only for the pins (external pad)?

You shouldn't mix up the tools.
Synplicity is the synthesis tool building a netlist (edif) out of your
code. If the edif netlist contains a GL33 for the input, you could
place it with Actel Chipplanner. If not, you couldn't place a global
buffer, because it is not there.

bye Thomas


Article: 124477
Subject: BRAM bytewide write enable problem
From: bharat_in <ecbharat@gmail.com>
Date: Mon, 24 Sep 2007 00:11:30 -0700
Links: << >>  << T >>  << A >>
I have created two BRAM using coregen (BLK_MEM_GEN_V2_4) , out of them
#1 is not supporting byte enable
#2 supports byte enable
Both of them are of same size 512x32

Now, during simulation the read data coming out of the BRAM #2 is not
the one which has been written.
In BRAM #1, the read_data is same as written data.
The only difference in between them is usage of byte wide write
enable.

I can't find why this is happening? can anyone please help me in
finding out the real problem.

ISE Version : 9.2i

Below are the files which i am using...

===================================================
BRAM #1,
===================================================
`timescale 1ns/1ps

module xil_syn_ram(
	clka,
	dina,
	addra,
	ena,
	wea,
	//clkb,
	addrb,
	enb,
	doutb);


input clka;
input [31 : 0] dina;
input [8 : 0] addra;
input ena;
input [0 : 0] wea;
//input clkb;
input [8 : 0] addrb;
input enb;
output [31 : 0] doutb;

// synthesis translate_off

      BLK_MEM_GEN_V2_4 #(
		.C_ADDRA_WIDTH(9),
		.C_ADDRB_WIDTH(9),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(9),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(1),
		.C_HAS_MEM_OUTPUT_REGS(0),
		.C_HAS_MUX_OUTPUT_REGS(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_SSRA(0),
		.C_HAS_SSRB(0),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(512),
		.C_READ_DEPTH_B(512),
		.C_READ_WIDTH_A(32),
		.C_READ_WIDTH_B(32),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_SINITA_VAL("0"),
		.C_SINITB_VAL("0"),
		.C_USE_BYTE_WEA(0),
		.C_USE_BYTE_WEB(0),
		.C_USE_DEFAULT_DATA(0),
		.C_USE_ECC(0),
		.C_USE_RAMB16BWER_RST_BHV(0),
		.C_WEA_WIDTH(1),
		.C_WEB_WIDTH(1),
		.C_WRITE_DEPTH_A(512),
		.C_WRITE_DEPTH_B(512),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("NO_CHANGE"),
		.C_WRITE_WIDTH_A(32),
		.C_WRITE_WIDTH_B(32),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.DINA(dina),
		.ADDRA(addra),
		.ENA(ena),
		.WEA(wea),
		.CLKB(clka),
		.ADDRB(addrb),
		.ENB(enb),
		.DOUTB(doutb),
		.REGCEA(),
		.SSRA(),
		.DOUTA(),
		.DINB(),
		.REGCEB(),
		.WEB(),
		.SSRB(),
		.DBITERR(),
		.SBITERR());


// synthesis translate_on

endmodule

===================================================
BRAM #2,
===================================================

`timescale 1ns/1ps

module xil_syn_ram_be(
	clka,
	dina,
	addra,
	ena,
	wea,
//	clkb,
	addrb,
	enb,
	doutb);


input clka;
input [31 : 0] dina;
input [8 : 0] addra;
input ena;
input [3 : 0] wea;
//input clkb;
input [8 : 0] addrb;
input enb;
output [31 : 0] doutb;

// synthesis translate_off

      BLK_MEM_GEN_V2_4 #(
		.C_ADDRA_WIDTH(9),
		.C_ADDRB_WIDTH(9),
		.C_ALGORITHM(1),
		.C_BYTE_SIZE(8),
		.C_COMMON_CLK(0),
		.C_DEFAULT_DATA("0"),
		.C_DISABLE_WARN_BHV_COLL(0),
		.C_DISABLE_WARN_BHV_RANGE(0),
		.C_FAMILY("virtex5"),
		.C_HAS_ENA(1),
		.C_HAS_ENB(1),
		.C_HAS_MEM_OUTPUT_REGS(0),
		.C_HAS_MUX_OUTPUT_REGS(0),
		.C_HAS_REGCEA(0),
		.C_HAS_REGCEB(0),
		.C_HAS_SSRA(0),
		.C_HAS_SSRB(0),
		.C_INIT_FILE_NAME("no_coe_file_loaded"),
		.C_LOAD_INIT_FILE(0),
		.C_MEM_TYPE(1),
		.C_PRIM_TYPE(1),
		.C_READ_DEPTH_A(512),
		.C_READ_DEPTH_B(512),
		.C_READ_WIDTH_A(32),
		.C_READ_WIDTH_B(32),
		.C_SIM_COLLISION_CHECK("ALL"),
		.C_SINITA_VAL("0"),
		.C_SINITB_VAL("0"),
		.C_USE_BYTE_WEA(1),
		.C_USE_BYTE_WEB(1),
		.C_USE_DEFAULT_DATA(1),
		.C_USE_ECC(0),
		.C_USE_RAMB16BWER_RST_BHV(0),
		.C_WEA_WIDTH(4),
		.C_WEB_WIDTH(4),
		.C_WRITE_DEPTH_A(512),
		.C_WRITE_DEPTH_B(512),
		.C_WRITE_MODE_A("WRITE_FIRST"),
		.C_WRITE_MODE_B("READ_FIRST"),
		.C_WRITE_WIDTH_A(32),
		.C_WRITE_WIDTH_B(32),
		.C_XDEVICEFAMILY("virtex5"))
	inst (
		.CLKA(clka),
		.DINA(dina),
		.ADDRA(addra),
		.ENA(ena),
		.WEA(wea),
		.CLKB(clka),
		.ADDRB(addrb),
		.ENB(enb),
		.DOUTB(doutb),
		.REGCEA(),
		.SSRA(),
		.DOUTA(),
		.DINB(),
		.REGCEB(),
		.WEB(),
		.SSRB(),
		.DBITERR(),
		.SBITERR());


// synthesis translate_on

endmodule

===================================================
Testbench, both above modules are instantiated in it
===================================================

module design_top_tb_v;

	// Inputs
	reg clka;
	reg clkb;
	reg [31:0] dina;
	reg [8:0] addra;
	reg wea;
	reg [3:0] wea_be;
	reg [8:0] addrb;
	reg ena;
	reg enb;

	// Outputs
	wire [31:0] doutb;
	wire [31:0] doutb_be;

	parameter PERIOD = 20;
                parameter DUTY_CYCLE = 0.5;


	// Instantiate the Unit Under Test (UUT)
	xil_syn_ram uut (
		.clka(clka),
		//.clkb(clkb),
		.dina(dina),
		.addra(addra),
		.wea(wea),
		.addrb(addrb),
		.ena(ena),
		.enb(enb),
		.doutb(doutb)
	);

	xil_syn_ram_be uut_be (
		.clka(clka),
		//.clkb(clkb),
		.dina(dina),
		.addra(addra),
		.wea(wea_be),
		.addrb(addrb),
		.ena(ena),
		.enb(enb),
		.doutb(doutb_be)
	);

	// Clock Stimulus
		always begin
         clka = 1'b0;
         #(PERIOD-(PERIOD*DUTY_CYCLE)) clka = 1'b1;
         #(PERIOD*DUTY_CYCLE);
			end

		// Clock Stimulus
		always begin
         clkb = 1'b0;
         #(PERIOD-(PERIOD*DUTY_CYCLE)) clkb = 1'b1;
         #(PERIOD*DUTY_CYCLE);
			end


	initial begin
		// Initialize Inputs
		clka = 0;
		clkb = 0;
		dina = 0;
		addra = 0;
		wea = 0;
		wea_be = 0;
		addrb = 0;
		enb = 0;
		ena = 0;

		// Wait 100 ns for global reset to finish
		#120;
		ena = 1;
		enb = 1;

		wea_be = 4'b0001;
		wea = 1'b1;

                                // 120 ns
		addra = 4'b0000;
		addrb = 4'b1111;

		// 140 ns
		#20
		addra = 4'b0001;
		addrb = 4'b1110;

		// 160 ns
		#20
		addra = 4'b0010;
		addrb = 4'b1101;

		// 180 ns
		#20
		addra = 4'b0011;
		addrb = 4'b1100;

		// 200 ns
		#20
		addra = 4'b0100;
		addrb = 4'b1011;

		// 220 ns
		#20
		addra = 4'b0101;
		addrb = 4'b1010;

		// 240 ns
		#20
		addra = 4'b0110;
		addrb = 4'b1001;

		// 260 ns
		#20
		addra = 4'b0111;
		addrb = 4'b1000;

		// 280 ns
		#20
		addra = 4'b1000;
		addrb = 4'b0111;

		//Overwrite of memory from INIT Values
		#280

		// 570 ns
		#10
		addra = 4'h0;
		dina = 16'h1010;

		addrb = 4'h0;

		// 590 ns
		#20
		addra = 4'h2;
		dina = 16'h23F2;

		addrb = 4'h2;

		// 610 ns
		#20
		addra = 4'h4;
		dina = 16'h2514;

		addrb = 4'h4;

		// 630 ns
		#20
		addra = 4'h6;
		dina = 16'h1616;

		addrb = 4'h6;

		// 650 ns
		#20
		addra = 4'h8;
		dina = 16'h1818;

		addrb = 4'h8;

		// 670 ns
		#20
		addra = 4'hA;
		dina = 16'h1A1A;

		addrb = 4'hA;

		// 690 ns
		#20
		addra = 4'hC;
		dina = 16'h1C1C;

		addrb = 4'hC;

		// 710 ns
		#20
		addra = 4'hE;
		dina = 16'h1E1E;

		addrb = 4'hE;

		// 730 ns
		#20
		$finish;
	end

endmodule


Article: 124478
Subject: [ANN] FPGAOptim - Do you know where your slices are going...?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Mon, 24 Sep 2007 14:16:05 +0100
Links: << >>  << T >>  << A >>
Hi all,

I now have the opportunity to make available to the wider world an
internal tool I developed to focus my area-optimisation efforts.  It
simply displays the hierarchy of your design, sorted by total LUT
count (or flipflop count, number of rams, multipliers etc.).  There
are various text-based tools around (indeed this started out as one)
but I found the interactive ability to navigate the design from a GUI
more useful.

You can read more and get the installer from:

http://www.conekt.net/fpgaoptim.html

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 124479
Subject: Re: CRC calculation of Virtex 4 bitstream
From: lembke.stefan@googlemail.com
Date: Mon, 24 Sep 2007 06:38:46 -0700
Links: << >>  << T >>  << A >>
i have already implemented an algorithm, which calculates a checksum
from given data.
and it works correct.

virtex4 configuration guide:
As the configuration data frames are loaded, the device calculates a
Cyclic Redundancy
Check (CRC) value from the configuration data packets.

i extracted these configuration data frames from the bit file and
calculated the checksum of it,
once with my implemented algorithm and once with an external program
(CrcSfv 1.3) and both checksums
are the same, but they are not the ckecksum, which is written down in
the bit file.

has anyone an idea, why?


Article: 124480
Subject: Re: Answer: maximum number of state machines in a current chip: > 500k
From: neilla@pipstechnology.co.uk
Date: Mon, 24 Sep 2007 07:14:21 -0700
Links: << >>  << T >>  << A >>
On 22 Sep, 15:49, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> Here is the answer to the maximum number of state machines in a
> current chip: > 500k.
>
> My original answer posing has some errors.
>

And there is also one more big error.

> 3. Please visit Intel product website to get the latest news:http://download.intel.com/products/processor/xeon/7300_prodbrief.pdf
>
> 4. "with up to 8 MB of L2 cache per processor" and 4 processors.
> It means 4*8MB = 32MB L2 cache;
>

If you read the product brief again, you should see that there is only
8MB of L2 on the whole chip.  This is split into 2 sets of 4MB which
can then be accessed by 2 cores.  Where Intel says processor they are
referring to the whole chip, and core is used to refer to the 4
processors on the chip.


Article: 124481
Subject: partial reconfiguration, par error
From: gilbert1219com@gmail.com
Date: Mon, 24 Sep 2007 14:14:26 -0000
Links: << >>  << T >>  << A >>
When I implement the reconfigure module, after ngdbuild, map and
continue with par there show some error but look like the same thing.
Did I place the busmacro in wrong place? My environment is
ISE9.1.02_PR2. Follow are error messages. Could any one tell me how to
fix these error, thanks.



ERROR: Net rst_n_b1_bm2prm crosses a region boundary and is not part
of a slice
macro.
       Nets crossing region boundaries must be part of a slice macro

   Static: rst_n_b1_bm2prm/PSEUDO_DRIVER
   Module: dataOut0_b1_prm2bm
   Module: dataOut1_b1_prm2bm
   Module: dataOut2_b1_prm2bm
   Module: dataOut3_b1_prm2bm

ERROR: Net dataIn0_b1_bm2prm crosses a region boundary and is not part
of a slic
e macro.
       Nets crossing region boundaries must be part of a slice macro

   Static: dataIn0_b1_bm2prm/PSEUDO_DRIVER
   Module: dataOut0_b1_prm2bm

ERROR: Net dataIn1_b1_bm2prm crosses a region boundary and is not part
of a slic
e macro.
       Nets crossing region boundaries must be part of a slice macro

   Static: dataIn1_b1_bm2prm/PSEUDO_DRIVER
   Module: dataOut1_b1_prm2bm

ERROR: Net dataIn2_b1_bm2prm crosses a region boundary and is not part
of a slic
e macro.
       Nets crossing region boundaries must be part of a slice macro

   Static: dataIn2_b1_bm2prm/PSEUDO_DRIVER
   Module: dataOut2_b1_prm2bm

ERROR: Net dataIn3_b1_bm2prm crosses a region boundary and is not part
of a slic
e macro.
       Nets crossing region boundaries must be part of a slice macro

   Static: dataIn3_b1_bm2prm/PSEUDO_DRIVER
   Module: dataOut3_b1_prm2bm

ERROR: Net dataOut0_b1_prm2bm crosses a region boundary and is not
part of a sli
ce macro.
       Nets crossing region boundaries must be part of a slice macro

   Static: dataOut0_b1_prm2bm/PSEUDO_LOAD
   Module: dataOut0_b1_prm2bm

ERROR: Net dataOut1_b1_prm2bm crosses a region boundary and is not
part of a sli
ce macro.
       Nets crossing region boundaries must be part of a slice macro

   Static: dataOut1_b1_prm2bm/PSEUDO_LOAD
   Module: dataOut1_b1_prm2bm

ERROR: Net dataOut2_b1_prm2bm crosses a region boundary and is not
part of a sli
ce macro.
       Nets crossing region boundaries must be part of a slice macro

   Static: dataOut2_b1_prm2bm/PSEUDO_LOAD
   Module: dataOut2_b1_prm2bm

ERROR: Net dataOut3_b1_prm2bm crosses a region boundary and is not
part of a sli
ce macro.
       Nets crossing region boundaries must be part of a slice macro

   Static: dataOut3_b1_prm2bm/PSEUDO_LOAD
   Module: dataOut3_b1_prm2bm


Article: 124482
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: "comp.arch.fpga" <ksulimma@googlemail.com>
Date: Mon, 24 Sep 2007 15:41:10 -0000
Links: << >>  << T >>  << A >>
On 19 Sep., 17:51, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi KS, jg,
> "A synchronous or an asynchronous reset signal is vital, either with
> clear routing or a hidden procedure within other initial procedures."

No, it is not.
See entries 2 and 3 on this page:
http://www.ics.uci.edu/~eppstein/pubs/misc.html

Kolja Sulimma


Article: 124483
Subject: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost to user!!!
From: Antti <Antti.Lukats@googlemail.com>
Date: Mon, 24 Sep 2007 15:45:41 -0000
Links: << >>  << T >>  << A >>
On 23 Sep., 21:54, Eric Smith <e...@brouhaha.com> wrote:
> Antti <Antti.Luk...@googlemail.com> writes:
> > If this is really so - this can only be verified when buying Actel M1
> > silicon and non-M1 at same time from same vendor, then it means that
> > there really is no hidden fee any more in the ARM softcore.
>
> No, it may mean that the chip vendor is absorbing the license cost, and
> making more profit on the non-M1.

well, no, as the non-M1 silicon was available before the Cortex
agreement.
so if the actel FPGA have now M1 option, and the price of normal
silicon
has not changed then it would mean there are no hidden cost at all.

but it is to be seen, what the prices will be when M1 enabled chips
actually become available

Antti



Article: 124484
Subject: Re: Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
From: "comp.arch.fpga" <ksulimma@googlemail.com>
Date: Mon, 24 Sep 2007 15:51:57 -0000
Links: << >>  << T >>  << A >>
On 20 Sep., 20:54, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Sep 19, 9:05 pm, John_H <newsgr...@johnhandwork.com> wrote:
>
> > Weng Tianxiang wrote:
> > > Hi Hal,
> > > 8b/10b is perfect for scrambling function. PCI-e uses 8b/10b
> > > technology.
>
> > > Scramble technology still uses randomized serial and XOR now? After 8b/
> > > 10b technology, I think other randomized XOR scramble technology is
> > > dying out, is it right?
>
> > > IBM got one patent for 8b/10b technology in 1981, Xilinx filed for 23
> > > patents on 8b/10b implementation in FPGA on one day in 2004.
>
> > > I think that IBM is really a technology leader in almost all respects
> > > in computer industry. Xilinx is the leader of FPGA.
>
> > > Weng

> Scrambler cannot be counted as a state machine in any sense.
Wrong. Again.

> The most important factor for a circuit counted as a state machine is
> that its states are mutually exclusive and only one state is active in
> any cycle.
Hmm. Any deterministic system can only be in one state. That is the
whole
meaning of "state". Of course there are non deterministic systems. And
also
non deterministic state machines. Just because you cannot code them in
VHDL
does not mean they do not exist. But I am sure you can provide an
extension to
VHDL that supports quantum computing. My suggestion:
if (condition) maybe
  dosomething;
anyways
  do somethin
beginning of the end;

> Scrambler cannot meet the requirements. If it were, every circuit
> would be counted as a state machine.

No, just any sequential circuit. Any circuit with state. Wait, maybe
that's
what the name comes from?
http://en.wikipedia.org/wiki/Finite_state_machine

> Shift registers can be counted as a state machine only when only one
> bit is set or reset among all its bits. Otherwise it cannot be counted
> as a state machine.

You still insist on your reset? Read the JTAG specification for gods
sake.

Kolja Sulimma



Article: 124485
Subject: Re: Gated Clock Problems
From: "Mike Lewis" <someone@micrsoft.com>
Date: Mon, 24 Sep 2007 11:52:31 -0400
Links: << >>  << T >>  << A >>

"vasile" <piclist9@gmail.com> wrote in message 
news:1190530279.201364.13380@y42g2000hsy.googlegroups.com...
> On Sep 20, 5:41 am, "Mike Lewis" <some...@micrsoft.com> wrote:
>> "vasile" <picli...@gmail.com> wrote in message
>>
>> news:1190286570.416365.21640@19g2000hsx.googlegroups.com...
>>
>> > Data on D must be stable before CLK, else you'll got garbage,
>> > scientificaly called "metastability" problems.
>> >http://www.interfacebus.com/Design_MetaStable.html
>>
>> > Vasile
>>
>> I feel I need to argue this morning ... you won't get garbage. If you
>> violate setup, the output will go metastable for a short period of time 
>> and
>> then settle on either the previous value or the new value.
>
> Right. This could be defined as a glitch if it's short enough and a
> glitch is garbage if it's propagate further in the logic design. Is
> just a way of interpretation.
>
> I think we have not argued at all.
>
> Vasile
>
>
> The metastability
>> will be so short in duartion you may as well ignore is effect unless you
>> have a clock period above 500Mhz.
>>
>> Mike
>
>

My window for arguing has past ... I no longer feel like it.
Mike 



Article: 124486
Subject: Re: Answer: maximum number of state machines in a current chip: > 500k
From: "Mike Lewis" <someone@micrsoft.com>
Date: Mon, 24 Sep 2007 11:58:06 -0400
Links: << >>  << T >>  << A >>

"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message 
news:1190472575.025542.322800@w3g2000hsg.googlegroups.com...
> Hi,
> Here is the answer to the maximum number of state machines in a
> current chip: > 500k.
>
> My original answer posing has some errors.
>
> 1. It is L2 cache that uses a lot of state machines;
> http://en.wikipedia.org/wiki/Cache_coherence
>
> 2. IBM/Intel uses MESI protocol (4 states: Modified, Exclusive, Shared
> and
> Invalid);
> http://en.wikipedia.org/wiki/MESI_protocol
>
>
> 3. Please visit Intel product website to get the latest news:
> http://download.intel.com/products/processor/xeon/7300_prodbrief.pdf
>
>
> 4. "with up to 8 MB of L2 cache per processor" and 4 processors.
> It means 4*8MB = 32MB L2 cache;
>
> 5. L2 cache is divided into data L2 cache and instruction L2 cache and
> only data L2 cache uses MESI protocol.
>
> 6. Each 32Bytes is a cache line;
>
> 7. 32MB/2/32 = 500k cache lines in data L2 cache and 500k state
> machines using MESI protocol.
>
> 8. L1/L3 cache and instruction L2 cache use several independent 1-bit
> flip-flops to recode their states so that they are not counted as
> state machines.
>
> The final answer is:
> There is at least 500k state machines in Intel chip.
>
> a. It is available to every users in the topics groups;
> b. They are written in Verilog, not in VHDL;
> c. FPGA has never had a design using L2 cache.
>
> Weng
>

saying that there are more than 500K state machines has not stated what the 
maximum number can be. 



Article: 124487
Subject: Re: Answer: maximum number of state machines in a current chip: > 500k
From: ghelbig@lycos.com
Date: Mon, 24 Sep 2007 15:58:08 -0000
Links: << >>  << T >>  << A >>
On Sep 22, 7:49 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> Here is the answer to the maximum number of state machines in a
> current chip: > 500k.
>
> My original answer posing has some errors.
>

It all depends on how you look at it; from a certain point of view,
the correct answer is one (1).

What you are calling state machines are just subordinate pieces of one
grand state machine.

G.


Article: 124488
Subject: Re: Gated Clock Problems
From: Jon Elson <elson@wustl.edu>
Date: Mon, 24 Sep 2007 13:00:42 -0500
Links: << >>  << T >>  << A >>


Hal Murray wrote:
>> If you are working with traditional synchronous logic,
> it's probably simplest to send both external signals through
> the standard pair of FFs and then make the decision with normal
> logic.  You can keep an extra bit of state and alternate
> the answer if both arrive during the same cycle.
> 

But, this doesn't answer the problem he is trying to, which is which 
signal arrives first.  If the two songlas both have edges within the 
same synchronous system clock, you get no answer, ie. they both changed 
dufing the same sample interval.  Entirely depending on what he is 
really trying to do here, an occasional metastable hangup may be 
perfectly fine, as long as you get the before/after decision 99% of the 
time.  By the way, you can probably ONLY do this in Xilinx parts, many 
other architectures won't let you connect FF clocks to combinatorial or 
non-clock nets without contortions.  For pure digital, synchronous 
systems, that is fine, for these special cases, Xilinx saves the day.
(It also allows the neophyte to dig himself a BIG hole!)

Jon


Article: 124489
Subject: Re: Gated Clock Problems
From: Jon Elson <elson@wustl.edu>
Date: Mon, 24 Sep 2007 13:01:59 -0500
Links: << >>  << T >>  << A >>


vasile wrote:
> Data on D must be stable before CLK, else you'll got garbage,
> scientificaly called "metastability" problems.
> http://www.interfacebus.com/Design_MetaStable.html
Actually, the metastability window on modern FPGA flip-flops
is INCREDIBLY small, probably less than 10 ps on most modern architectures.

Jon


Article: 124490
Subject: Re: Gated Clock Problems
From: Jon Elson <elson@wustl.edu>
Date: Mon, 24 Sep 2007 13:12:32 -0500
Links: << >>  << T >>  << A >>
> 
> So far I've only seen talk of violated setup times in relation with the
> metastability problem. No problems with hold times?
> 
> I've done a resonable amount of logic designs (TTL/CPLD/FPGA), but never
> have run into this problem. Maybe because most of my designs run fairly
> slow and I always like to clock everithing through dff's anyway. :-)
> 

If you want to actually see metastability, it is bets to start with a 
slow technology, like the 74HC74.  Build a clock circuit that pulses the 
clock input at 1 MHz, say, then arrange a circuit that can adjust the 
state change of the D input + or - of the clock by a couple ns.  Make it 
a very small range, because even on these slow FFs the sampling window 
is really small.  When you hit that timing window, the output will not 
change from 1 to 0 abruptly, but will statistically give a % of 1's and 
0's.  With a good analog scope or a fast digital phosphor scope, you 
will see some changes that are later than the time-clock-to-output. 
Those were the metastable events, where the FF did not settle on one 
state immediately.  If you try to do this with an FPGA FF, you will 
spend all day with exotic lab gear trying to get one event.

Jon


Article: 124491
Subject: Re: Gated Clock Problems
From: "Symon" <symon_brewer@hotmail.com>
Date: Mon, 24 Sep 2007 19:18:32 +0100
Links: << >>  << T >>  << A >>
"Mike Lewis" <someone@micrsoft.com> wrote in message 
news:c3041$46f7dd42$401a86c3$3487@PRIMUS.CA...
> My window for arguing has past ... I no longer feel like it.
> Mike
Fail! 



Article: 124492
Subject: Automotive Electronic Control
From: icegray <icegray@gmail.com>
Date: Mon, 24 Sep 2007 13:08:37 -0700
Links: << >>  << T >>  << A >>
Hi,
I'm looking for a control unit (plc, control card, control module) for
construction equipment (excavator). It should contain digital and
analog inputs and digital outputs. Any body have experience or know
brand (like as axiomatic) about this subject?
Thanks all


Article: 124493
Subject: Re: Configuring Impact on any version of linux
From: "MM" <mbmsv@yahoo.com>
Date: Mon, 24 Sep 2007 16:50:30 -0400
Links: << >>  << T >>  << A >>
Ankit,

> I have tried installing Windriver
> many times but most of the times the kernel version of the linux which
> i have does not matches with 1

Don't mess with the Windriver. It might work, but the effort is not worth 
it. There is a much better user space driver by Michael Gernoth, which you 
should use.

The below instructions overall worked for me, although I might have had to 
tweak something on the way:
http://www.itee.uq.edu.au/~listarch/microblaze-uclinux/archive/2007/03/msg00101.html

The Michael Gernoth's driver is supposedly included in the latest ISE.


/Mikhail




Article: 124494
Subject: Re: Actel Cortex FPGAs, real change of ARM licensing - 0.000 cost
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Tue, 25 Sep 2007 08:52:21 +1200
Links: << >>  << T >>  << A >>
Antti wrote:
> On 23 Sep., 21:54, Eric Smith <e...@brouhaha.com> wrote:
> 
>>Antti <Antti.Luk...@googlemail.com> writes:
>>
>>>If this is really so - this can only be verified when buying Actel M1
>>>silicon and non-M1 at same time from same vendor, then it means that
>>>there really is no hidden fee any more in the ARM softcore.
>>
>>No, it may mean that the chip vendor is absorbing the license cost, and
>>making more profit on the non-M1.
> 
> 
> well, no, as the non-M1 silicon was available before the Cortex
> agreement.
> so if the actel FPGA have now M1 option, and the price of normal
> silicon
> has not changed then it would mean there are no hidden cost at all.
> 
> but it is to be seen, what the prices will be when M1 enabled chips
> actually become available

Yes, it's only really free, if they Paid ARM nothing for it :)

Anything else has to be paid for somehow!

Even the existance of a special device and part number, is a cost
for customers and distributors.

Note this is a simpler M1 core, not an M3 core. There was
also a comment IIRC about the Debug option being quite large,
so that pushes up your FPGA size, as most designs will want to
have debug ability...

-jg


Article: 124495
Subject: Re: [ANN] FPGAOptim - Do you know where your slices are going...?
From: "MM" <mbmsv@yahoo.com>
Date: Mon, 24 Sep 2007 16:57:01 -0400
Links: << >>  << T >>  << A >>
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message 
news:u3ax4p5ka.fsf@trw.com...
> Hi all,
>
> I now have the opportunity to make available to the wider world an
> internal tool I developed to focus my area-optimisation efforts.  It
> simply displays the hierarchy of your design, sorted by total LUT
> count (or flipflop count, number of rams, multipliers etc.).  There
> are various text-based tools around (indeed this started out as one)
> but I found the interactive ability to navigate the design from a GUI
> more useful.
>
> You can read more and get the installer from:
>
> http://www.conekt.net/fpgaoptim.html
>

Is it based on Andreas Ehliar's xdlanalyze Perl script?


Thanks,
/Mikhail 



Article: 124496
Subject: Re: Verilog simple dual port memory with different input and output
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Mon, 24 Sep 2007 15:32:08 -0600
Links: << >>  << T >>  << A >>
davew wrote:
> Has anyone got any example Verilog code for this?  I'm currently using
> Quartus wizard generated code and wrapping it up in a Verilog module
> so I can use my own parameters instead of running the wizard each time
> I need a new variation (which is a complete pain).  I thought that
> perhaps inferring the memory might yield better and more efficient
> results.
> 
> Ta.
> 
I have such a piece of code but it only works for Xilinx parts.  (Which 
you should use.)  Most likely the synthesizer will not infer RAMs of 
different port widths from a behavioral description.  My code takes 
Verilog parameters that are passed in and then uses 'generates' to 
instantiate an array of the correct blockRAM primitives with the 
primitive parameters set for asymmetric port widths if necessary. 
You'll probably need to do something similar if you want an HDL 
solution.  I'm not sure why the tools don't support this yet.  A 
behavioral description of an asymmetric RAM is slightly awkward, but 
definitely doable.
-Kevin

Article: 124497
Subject: Re: Gated Clock Problems
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 25 Sep 2007 00:31:44 +0100
Links: << >>  << T >>  << A >>
"Jon Elson" <elson@wustl.edu> wrote in message 
news:46F7FE10.90107@wustl.edu...
>
>  If you try to do this with an FPGA FF, you will spend all day with exotic 
> lab gear trying to get one event.
>
> Jon
>
Hi Jon,
Thanks for your post, but sorry, but that last statement is bollocks. It's 
easy to get metastable events in an FPGA. X, A, L or otherwise. Email Xilinx 
and ask about Virtex 4 fifos. Or search through this newsgroup's archive. Or 
do the maths.
HTH., Syms. 



Article: 124498
Subject: Re: [ANN] FPGAOptim - Do you know where your slices are going...?
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Tue, 25 Sep 2007 09:24:01 +0100
Links: << >>  << T >>  << A >>
"MM" <mbmsv@yahoo.com> writes:

>
> Is it based on Andreas Ehliar's xdlanalyze Perl script?

No, Andreas announced the availability of his script just about the
time I was working on the first text-mode version of this tool (which
was called xdlanalyse at the time!)

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 124499
Subject: Re: Automotive Electronic Control
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Tue, 25 Sep 2007 09:26:28 +0100
Links: << >>  << T >>  << A >>
icegray <icegray@gmail.com> writes:

> Hi,
> I'm looking for a control unit (plc, control card, control module) for
> construction equipment (excavator). It should contain digital and
> analog inputs and digital outputs. Any body have experience or know
> brand (like as axiomatic) about this subject?

If the rest of the group can excuse the advert, is this any use?

http://www.conekt.net/docs/CAN-click1%20flexible%20ECU.pdf

It's not FPGA based, so may be off-topic :-)

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html



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