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Martin Thompson <martin.j.thompson@trw.com> writes: Anyone who downloaded this utility and is experiencing crashes on large designs, please download a new installer from the same location, or send me a mail if you need the link again. I've fixed a bug which was crashing the tree viewer - sorry about that! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html From laurent.pinchart@skynet.be Mon Oct 08 04:08:53 2007 Path: newssvr13.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!ecngs!feeder2.ecngs.de!novso.com!news.skynet.be!195.238.0.222.MISMATCH!newsspl501.isp.belgacom.be!tjb!not-for-mail Message-Id: <470a0fc5$0$22313$ba620e4c@news.skynet.be> From: Laurent Pinchart <laurent.pinchart@skynet.be> Subject: Re: [ANN] FPGAOptim - Do you know where your slices are going...? Newsgroups: comp.arch.fpga Date: Mon, 08 Oct 2007 13:08:53 +0200 References: <u3ax4p5ka.fsf@trw.com> <ubqb9oql8.fsf@trw.com> User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 15 Organization: -= Belgacom Usenet Service =- NNTP-Posting-Host: 7445749a.news.skynet.be X-Trace: 1191841733 news.skynet.be 22313 194.78.198.49:49976 X-Complaints-To: usenet-abuse@skynet.be Xref: prodigy.net comp.arch.fpga:136823 Hi Martin, > Martin Thompson <martin.j.thompson@trw.com> writes: > > Anyone who downloaded this utility and is experiencing crashes on > large designs, please download a new installer from the same location, > or send me a mail if you need the link again. I've fixed a bug which > was crashing the tree viewer - sorry about that! Any plan for an open-source Linux version ? Cheers, Laurent PinchartArticle: 124851
Tony, The other great low-cost tool for JTAG Boundary Scan interconnect testing is the Universal Scan tool from http://www.ricreations.com/index.html JSCAN is a licensed version of the UniversalScan. UniversalScan looks like the Scanneer, but with much more feature as the possibility to remote SPI and parallel Flash upload via any JTAG pins, as the possibility to store SVF output format. Then the SVF can be replayed with the optimized amtsvfplayer ( Amontec SVF Player ) from http://www.amontec.com . Both Scaneer and Universal Scan can be used with Amontec JTAGkey with a real good performance, but Universal Scan takes all the advantages of the optimized amtxhal.dll ( Amontec Hardware Abstraction Layer ) allowing to be much faster. Laurent Burch wrote: > Hi, > I am looking at various alternatives for interconnect testing, especially > for prototype boards that have BGAs. I am very interested to know what other > people are using for JTAG interconnect testing, and what your debugging > experiences are? > > I have Scanseer, and I like it very much. I can do some interconnect testing > and real-time monitoring with Scanseer. Another one out there is JSCAN from > Macraigor Systems. I have not used JSCAN. The test script recorder stores in > SVF looks like it could be good. > > Does anyone do prototype interconnect testing with: > * Amontec JTAGkey? > * the Lattice tools - ispVM? > > Any other suggestions or experiences with interconnect testing (besides > X-ray:) )? > > Thanks & cheers, > Tony Burch > > > > >Article: 124852
how to merge multiple missed coverage files to see final uncoverd lines in one file? thanks in advance.Article: 124853
Laurent Pinchart <laurent.pinchart@skynet.be> writes: > Hi Martin, > >> Martin Thompson <martin.j.thompson@trw.com> writes: >> >> Anyone who downloaded this utility and is experiencing crashes on >> large designs, please download a new installer from the same location, >> or send me a mail if you need the link again. I've fixed a bug which >> was crashing the tree viewer - sorry about that! > > Any plan for an open-source Linux version ? > There may be a Linux version, you are the third person to ask (four including me). There are no plans to open-source it though - would that matter to people? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 124854
Corelis is a great tool for Interconnect testing, but I know that it is expensive. But may be one time investement on this tool is a fair deal because it saves you a whole lot of time in debugging opens and shorts. They have various test types -- for BGA's, memory (DIMMs, flash etc). Apart from these, you can also write your own tests. For example if you have a Clock Buffer connected to an FPGA and you want to program it to enable and disable some outputs, then you can create a test which basically writes to the registers to do the same. They also have products where in you can program the EEPROM's through JTAG. These are all what I used from Corelis and as Bob told their support is also good. -- parag On Oct 8, 7:10 am, "Amontec, Larry" <laurent.ga...@ANTI- SPAMamontec.com> wrote: > Tony, > > The other great low-cost tool for JTAG Boundary Scan interconnect > testing is the > Universal Scan tool fromhttp://www.ricreations.com/index.html > > JSCAN is a licensed version of the UniversalScan. UniversalScan looks > like the Scanneer, but with much more feature as the possibility to > remote SPI and parallel Flash upload via any JTAG pins, as the > possibility to store SVF output format. Then the SVF can be replayed > with the optimized amtsvfplayer ( Amontec SVF Player ) fromhttp://www.amontec.com. > > Both Scaneer and Universal Scan can be used with Amontec JTAGkey with a > real good performance, but Universal Scan takes all the advantages of > the optimized amtxhal.dll ( Amontec Hardware Abstraction Layer ) > allowing to be much faster. > > Laurent > > > > Burch wrote: > > Hi, > > I am looking at various alternatives for interconnect testing, especially > > for prototype boards that have BGAs. I am very interested to know what other > > people are using for JTAG interconnect testing, and what your debugging > > experiences are? > > > I have Scanseer, and I like it very much. I can do some interconnect testing > > and real-time monitoring with Scanseer. Another one out there is JSCAN from > > Macraigor Systems. I have not used JSCAN. The test script recorder stores in > > SVF looks like it could be good. > > > Does anyone do prototype interconnect testing with: > > * Amontec JTAGkey? > > * the Lattice tools - ispVM? > > > Any other suggestions or experiences with interconnect testing (besides > > X-ray:) )? > > > Thanks & cheers, > > Tony Burch- Hide quoted text - > > - Show quoted text -Article: 124855
Hi all, I'm designing a board based on a virtex5 (XC5VLX50). I'm surprised, I can't find virtex 5 symbols for using with orcad or kicad. I only found a post explaining how to create symbol in orcad using ISE pin file. But it requires Orcad Capture, and I plan tu use kicad (http://www.lis.inpg.fr/realise_au_lis/kicad/) for schematics, and only Cadence Allegro, the Orcad router for PCB. This is the first time I work with Xilinx, but I know for Altera FPGA, the Orcad symbol was freely downloadable.. So if anyone can help me, or have an interesting link.. Thanks by advance, Best regards, Michel.Article: 124856
On Oct 8, 6:48 pm, "beer...@gmail.com" <beer...@gmail.com> wrote: > Corelis is a great tool for Interconnect testing, but I know that it > is expensive. But may be one time investement on this tool is a fair > deal because it saves you a whole lot of time in debugging opens and > shorts. But comparing to Corelis the power of Scanseer or UniversalScan is that you do not need to write any tests or prepare some test vectors. All you need is a BSDL file and you are ready to go. You can just select a pin on graphical view and monitor its value, or manipulate with its value to test board interconnects.Article: 124857
On Oct 7, 7:43 pm, "Tony Burch" <t...@burched.com.au> wrote: > Hi, > I am looking at various alternatives for interconnect testing, especially > for prototype boards that have BGAs. I am very interested to know what other > people are using for JTAG interconnect testing, and what your debugging > experiences are? > > I have Scanseer, and I like it very much. I can do some interconnect testing > and real-time monitoring with Scanseer. Another one out there is JSCAN from > Macraigor Systems. I have not used JSCAN. The test script recorder stores in > SVF looks like it could be good. > > Does anyone do prototype interconnect testing with: > * Amontec JTAGkey? > * the Lattice tools - ispVM? > > Any other suggestions or experiences with interconnect testing (besides > X-ray:) )? > > Thanks & cheers, > Tony Burch I use onTAP by Flynn systems. See http://www.flynn.com/ I have been using it for about four or five years now and have always been very happy with it. We use it to generate the test vectors, and to run the test. To generate the vectors, we give it the BSDL files for the chips, an EDIF of the schematic. It then has a few GUI pages of set up to tell it about pins that are pulled high or low, and nets that are shorted through passives. After that, it generates the vectors and a coverage report. We use it with Xilinx FPGAs and the Xilinx parallel cable IV. Regards, John McCaskill www.fastertechnology.comArticle: 124858
Hi I have read on this group that it is required 4 pads space from LVDS differential signals to single-ended pin. Is this requirment concern also to PLL_OUTp/n pins? -- PGWArticle: 124859
I haven't gotten far with solving the problem yet, other than collecting more benchmarks. FWIW, Quartus has been multi-threaded since v7.0, although only certain tasks (quartus_fit and Timequest/quartus_sta) appear to do much with it. You can set the variable NUM_PARALLEL_PROCESSORS to a value between 1 and 4, (some of the docs imply up to 16, but my runs errored out when I tried 5-8). Among the things I noticed, with NUM_PARALLEL_PROCESSORS=1 and NO other jobs running on the machine, quartus_map was pinging back and forth between two CPUs; I suspect pinning that process to one CPU would not hurt the cause. After a while, it appeared to stick to one CPU, but i didn't watch long enough to call it a scientific observation. Also, with no other jobs running, quartus_map did not finish much faster (about 4% faster) than when five other jobs (up to 13 more threads) were running simultaneously. I guess the memory arbitration has to take place regardless of whether or not the other CPUs are accessing it. I would hope/expect that a company like Sun has some hardware workarounds to prevent the memory interface from being such a bottleneck; (e.g., with most processes fitting into under 2GB of memory, can/do they devote a few GB to each CPU for full-speed access w/o arbitration, and then only access a shared pool when you go over that limit?) Hardware being fixed as it is, I guess I'll have to dig deeper thru the AMD and RedHat docs on NUMA, etc...; one article I'm wading thru is this one from nOvell; http://www.novell.com/collateral/4622016/4622016.pdf (Optimizing Linux for Dual-core Opteron Processors) It's a good start, but maybe somewhat Suse and single-chip (one dual core) specific. If anyone has any links or suggestions more specific to Red Hat and more processors, I'm all ears. Thanks again1Article: 124860
Hi, I'm a Computer Science student and for my final year project I have chosen to implement a Neural Network Co-processor for the Power PC architecture using the Xilinx EDK. As I am relativley inexperienced in fpga development, I would love to hear some people thoughts on this idea as a final year project. Particularly on the suitability of the EDK as a development platform for this project. Thanks a lot, any input will be greatly appreciated MikeArticle: 124861
On Oct 8, 3:10 pm, "Amontec, Larry" <laurent.ga...@ANTI- SPAMamontec.com> wrote: > Both Scaneer and Universal Scan can be used with Amontec JTAGkey with a > real good performance, but Universal Scan takes all the advantages of > the optimized amtxhal.dll ( Amontec Hardware Abstraction Layer ) > allowing to be much faster. Larry, I do not agree to this point. Scanseer is much more faster (performs more samples per second) then UniversalScan. It seems like UniversalScan always makes about 10 samples per second independent of what JTAG cable is connected. Scanseer performance depends on cable type (and of course JTAG chain size). With Olimex USB cable based on FTDI FT2232 (compatible to Amontec JTAG-Key) I received about 1000 samples per second for chain consisting of one Atmel ATmega device. Scanseer also has a waveform viewer to record and display such fast changing signals.Article: 124862
On Oct 8, 9:19 am, michel.ta...@gmail.com wrote: > Hi all, > > I'm designing a board based on a virtex5 (XC5VLX50). I'm surprised, I > can't find virtex 5 symbols for using with orcad or kicad. > I only found a post explaining how to create symbol in orcad using ISE > pin file. But it requires Orcad Capture, and I plan tu use kicad > (http://www.lis.inpg.fr/realise_au_lis/kicad/) for schematics, and > only Cadence Allegro, the Orcad router for PCB. > > This is the first time I work with Xilinx, but I know for Altera FPGA, > the Orcad symbol was freely downloadable.. > > So if anyone can help me, or have an interesting link.. > > Thanks by advance, > > Best regards, Michel. You won't find an FPGA symbol; it isn't done that way anymore. You may find some (typically evaluation) boards where there is a symbol for each bank, but this gets clumsy, and thwarts any automated error checking. Common practice is to create a seperate symbol for each interface connected to the FPGA. So you would have (for instance) a symbol for the Virtex-5 connections to the ethernet phy, another symbol for the connections to the DRAM, another symbol for the dedicated programming pins, etc., etc. My advice: Learn how to create schematic symbols. G.Article: 124863
Hi friends I am working in a pvt concern.We are decided to purchase FPGA trainer kit. But we are confused with Xilinx-Virtex-5 and Altera-stratix-3. Which one will be the better in configuration? Feauture-wise which one will be better? And which altera device has the feature of ML505 in Virtex-5? Plz give up some ideas regarding thiz... thanksArticle: 124864
Tony Burch <tony@burched.com.au> wrote: > Hi, > I am looking at various alternatives for interconnect testing, especially > for prototype boards that have BGAs. I am very interested to know > what other people are using for JTAG interconnect testing, and > what your debugging experiences are? > I have Scanseer, and I like it very much. I can do some > interconnect testing and real-time monitoring with Scanseer. > Another one out there is JSCAN from Macraigor Systems. >I have not used JSCAN. The test script recorder stores in > SVF looks like it could be good. > Does anyone do prototype interconnect testing with: > * Amontec JTAGkey? > * the Lattice tools - ispVM? > Any other suggestions or experiences with interconnect testing (besides > X-ray:) )? On a similar subject: Any JTAG test software that is available for Linux and windows? Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 124865
On 9 oct, 03:53, ghel...@lycos.com wrote: > On Oct 8, 9:19 am, michel.ta...@gmail.com wrote: > > > > > Hi all, > > > I'm designing a board based on a virtex5 (XC5VLX50). I'm surprised, I > > can't find virtex 5 symbols for using with orcad or kicad. > > I only found a post explaining how to create symbol in orcad using ISE > > pin file. But it requires Orcad Capture, and I plan tu use kicad > > (http://www.lis.inpg.fr/realise_au_lis/kicad/) for schematics, and > > only Cadence Allegro, the Orcad router for PCB. > > > This is the first time I work with Xilinx, but I know for Altera FPGA, > > the Orcad symbol was freely downloadable.. > > > So if anyone can help me, or have an interesting link.. > > > Thanks by advance, > > > Best regards, Michel. > > You won't find an FPGA symbol; it isn't done that way anymore. > > You may find some (typically evaluation) boards where there is a > symbol for each bank, but this gets clumsy, and thwarts any automated > error checking. > > Common practice is to create a seperate symbol for each interface > connected to the FPGA. So you would have (for instance) a symbol for > the Virtex-5 connections to the ethernet phy, another symbol for the > connections to the DRAM, another symbol for the dedicated programming > pins, etc., etc. > > My advice: Learn how to create schematic symbols. > G. Thanks for your answer, it seems to be a nice approach to obtain a schematic easily readable. Best regards.Article: 124866
pgw pisze: > Hi > > I have read on this group that it is required 4 pads space from LVDS > differential signals to single-ended pin. > Is this requirment concern also to PLL_OUTp/n pins? > Hi, That's true. If you are not sure just try to fit it. But you can force this if LVDS is next to really slow signals like reset or slow I/O. AdamArticle: 124867
I need info about programm FLASH without external programmer.When I program this IC from I2C I rpogramm volatile configuration memory?Article: 124868
Górski Adam wrote: > pgw pisze: >> Hi >> >> I have read on this group that it is required 4 pads space from LVDS >> differential signals to single-ended pin. >> Is this requirment concern also to PLL_OUTp/n pins? > > That's true. If you are not sure just try to fit it. > But you can force this if LVDS is next to really slow signals like reset > or slow I/O. > > Adam I have just do that. This requirment don't concern to PLL_OUT. -- PGWArticle: 124869
i have downloaded the xilinx webpack and gone through a few tutorials on the software can anyone recommend a good starter board, that would cope with trying a small softcore microcontroller. If anyone has any good tutorials or educational material on FPGAs please could you email me. Any advice would be greatly appreciated. Dan WalmsleyArticle: 124870
hi ,
how can i save the coverage data , so that the output file
contains the missed coverage lines and/or coverage lines and how to
merge that files so that the final output file contains missed
coverage lines and/or coverage lines. please help me...
thanks in advance...
Article: 124871yeah wrote: > Hi friends > > I am working in a pvt concern.We are decided to purchase FPGA trainer > kit. > But we are confused with Xilinx-Virtex-5 and Altera-stratix-3. > Which one will be the better in configuration? > Feauture-wise which one will be better? > And which altera device has the feature of ML505 in Virtex-5? > > Plz give up some ideas regarding thiz... > > thanks You cannot receive appropriate guidance without communicating what you want to do with this board. General logic? Video? Embedded computing? Storage applications? PCIe peripherals? Let us know, please.Article: 124872
On Oct 9, 7:32 am, axalay <axa...@gmail.com> wrote: > I need info about programm FLASH without external programmer.When I > program this IC from I2C I rpogramm volatile configuration memory? The datasheet for the CY22393 says "Allows in-system programming into volatile configuration memory." There is no mention of in-system flash programming. I believe you need to use the external programmer to set up the power-on conditions. If you are not relying on the CY22393 at power-on, you could implement code to set it up using the volatile configuration registers at start-up time. Regards, GaborArticle: 124873
On Oct 9, 7:19 am, dan.walms...@gmail.com wrote: > i have downloaded the xilinx webpack and gone through a few tutorials > on the software can anyone recommend a good starter board, that would > cope with trying a small softcore microcontroller. > > If anyone has any good tutorials or educational material on FPGAs > please could you email me. > > Any advice would be greatly appreciated. > > Dan Walmsley Digilent (www.digilentinc.com) has the Xilinx starter boards. I think that Digilent also has tutorials, but I'm not sure. -Dave PollumArticle: 124874
On Oct 9, 8:13 am, John_H <newsgr...@johnhandwork.com> wrote: > yeah wrote: > > Hi friends > > > I am working in a pvt concern.We are decided to purchase FPGA trainer > > kit. > > But we are confused with Xilinx-Virtex-5 and Altera-stratix-3. > > Which one will be the better in configuration? > > Feauture-wise which one will be better? > > And which altera device has the feature of ML505 in Virtex-5? > > > Plz give up some ideas regarding thiz... > > > thanks > > You cannot receive appropriate guidance without communicating what you > want to do with this board. General logic? Video? Embedded computing? > Storage applications? PCIe peripherals? > > Let us know, please. I agree with John_H. What do you want to do with the FPGA? I curious why you chose the Virtex-5 FPGA and a Stratix-3 FPGA? Are you looking for specific features? Do you have a limit on how much money you can spend? If you are new to FPGAs, then you may be better off starting with a simpler and cheaper board, for example a Xlinix Sparta-3E stater board ($150USD), and then moving on to the more complex and expensive ML505 board ($11195USD). I'm not familiar with Altera products, but I assume that they also have FPGA boards. Just my 2 cents. -Dave Pollum
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