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Hi Sanjay, The Early Power Estimator requires Excel 2002 or higher, and I believe this error is due to using an older version of Excel that doesn't provide all the hooks the EPE needs. I suggest trying the EPE with a more recent version of Excel. Regards, Vaughn AlteraArticle: 124826
I was just eating some spicy food for lunch and I started wondering whether Xilinx would eventually come out with a Virtex 13 family or would they skip it due to superstitious reasons? Thanks. BobArticle: 124827
Thanks in advance for the help! ---------------------------------------- My employer just acquired a SunFire server w 16 dual-core Opterons (model 8220, 2.8 GHz) and 128GB of RAM. Despite the faster clock and memory interface, it's running my Quartus jobs slower than a 2-year old dual-core Opteron (2.4 GHz Model 250). I suspect my I.T. dept just did a generic configure, and missed out on some major performance tuning opportunities. Maybe they've left a power-saving mode (like PowerNow) in place? Can anyone suggest the biggest-bang-for-the-buck things to look at? I don't have root privelege, but I'm trying to help the I.T folks along. uname -a: Linux monster 2.6.9-55.ELlargesmp #1 SMP Fri Apr 20 16:46:56 EDT 2007 x86_64 x86_64 x86_64 GNU/Linux top: top - 16:58:22 up 1 day, 3:07, 3 users, load average: 1.98, 1.97, 2.17 Tasks: 174 total, 2 running, 172 sleeping, 0 stopped, 0 zombie Cpu(s): 9.0% us, 0.1% sy, 0.0% ni, 90.8% id, 0.0% wa, 0.0% hi, 0.0% si Mem: 131385408k total, 5031132k used, 126354276k free, 135848k buffers Swap: 41943032k total, 0k used, 41943032k free, 3417328k cached PID USER PR NI VIRT RES SHR S %CPU %MEM TIME+ COMMAND 13903 jjohnson 22 0 1111m 1.0g 49m R 100 0.8 3:22.81 quartus_eda 14059 jjohnson 15 0 137m 48m 39m S 46 0.0 0:03.08 quartus_cdb cat /proc/cpuinfo: (same repeated for all 16 processors) processor : 0 vendor_id : AuthenticAMD cpu family : 15 model : 65 model name : Dual-Core AMD Opteron(tm) Processor 8220 stepping : 3 cpu MHz : 2800.274 cache size : 1024 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 2 fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clf lush mmx fxsr sse sse2 ht syscall nx mmxext lm 3dnowext 3dnow pni cx16 bogomips : 5603.62 TLB size : 1088 4K pages clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management: ts fid vid ttp [4] [5]Article: 124828
On Oct 5, 9:27 am, "John_H" <newsgr...@johnhandwork.com> wrote: > "spartan3wiz" <magnus.wedm...@gmail.com> wrote in message > > news:1191594443.303849.241260@19g2000hsx.googlegroups.com... > <snip>> .... On the downside the external connector it uses a Hirose 100- > > pin FX2 connector that don't come cheap from a hobby-side view, like > > $25 for just a single connector if I remember correctly. ... > > <snip> > > I picked up a couple connectors from Digikey 1 year ago this Tuesday at > $6.79 each. They still show up at the same price: > > http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=H432... > > The Hirose connector form factor may be "inconvenient" for perf-board > hobbyists, but we're getting beyond the age of simple perf-board circuits. > > - John_H Why not get the FX2 expansion board from Digilent? http://www.digilentinc.com/Products/Detail.cfm?Prod=FX2WW&Nav1=Products&Nav2=Accessory It's got the Hirose connector, ground plane, 0.1" grid plated-thru holes, supply lines and lots of I/O capability and only costs about $20. I've been using one with my Spartan3E starter kit for a few months now and it works quite nicely. EBArticle: 124829
johnp wrote: > On Sep 28, 7:49 pm, Peter Alfke <al...@sbcglobal.net> wrote: > >>On Sep 28, 5:05 pm, John Adair <g...@enterpoint.co.uk> wrote:> Austin >> >> >>>Might be worth making the suggestion to your sister grouping of GPD of >>>adding a dedicated oscillator crcuit to their range of products. Given >>>a lot of micros do that already there would be some logic in adding >>>such a circuit in the future to the low cost sector FPGA families. >> >>John, "been there, done that". >>XC3000 used to have a single-stage dedicated inverter, exactly for >>that purpose. It caused us a lot of support grief. Between 32 kHz and >>100 MHz, there is a big variation in xtals, and there also was a >>sensitivity to Vcc ramp-up rate. Nobody wants a circuit to work "most >>of the time". >>I also remember that many of the Intel mask revisions of the 8051 were >>oscillator-related. (We second-sourced that at AMD) >>My advice has always been: spend a few pennies on an oscillator >>circuit made by specialists for a special purpose. And definitely do >>not abuse a multi-stage I/O circuit to be the xtal inverter circuit. >>Far too much gain and uncontrolled phase changes at very high >>frequencies. >>Peter Alfke > > > I'd be happy if Xilinx would simply provide a free running, loosely > spec'd clock in the FPGAs > that a designer could use for non-critical design. They could spec it > as "it runs at some > frequency between 5 and 30 MHz and will drift with temperature/ > voltage, you can't set it, > you can only use it." If they would let you use the Master Mode > programming clock inside > the design, I'd be happy. I don't care about the frequency, I just > want a free running clock. > > No crystal pads, no clock divider, just a ring oscillator within a > reasonable frequency range. You can build Ring osc in almost any Prog Logic device. We have done them in Atmel CPLDs, using foldback nodes, which avoids using a more valuable Macrocell. Crystal Osc with Schmitt pins are fragile at best, but LC osc work quite well - so if you need a precision better than a Ring Osc, but not as high as a Crystal, then LC is usable. SOT23 Digital Osc continue to advance, and tiny uC get better all the time in their analog-osc performance, so those are also OSC candidates -jgArticle: 124830
BobW wrote: > I was just eating some spicy food for lunch and I started wondering whether > Xilinx would eventually come out with a Virtex 13 family or would they skip > it due to superstitious reasons? Good question, could they name it XIII, or even 1101 to avoid the negative connotations of writing '13' directly ? :) -jgArticle: 124831
Bob, 13 is a lucky number in some cultures. 4 and 9 resemble the character 'death' in Chinese ideographs (I'm told) whereas 8 is a very lucky number in that culture. Personally, I rather like the number 13, and have no aversion to it whatsoever. 13 Base 13 would be an interesting diversion: the number 10 (base 13) would be 'unlucky' where 13 (base 13) would be 16 in base 10, and hence, lucky? So, what base numbering system is 13 unlucky in? Why? Is it unlucky in all base systems? Why or why not? AustinArticle: 124832
On Oct 5, 7:02 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > BobW wrote: > > I was just eating some spicy food for lunch and I started wondering whether > > Xilinx would eventually come out with a Virtex 13 family or would they skip > > it due to superstitious reasons? > > Good question, could they name it XIII, or even 1101 > to avoid the negative connotations of writing '13' directly ? :) Since I had spicy food for lunch today too, here's my navel gazing: it's infinitely more likely that the Virtex name won't even make it to gen 12, much less 13. Sometime in the next *decade*, a new architecture will replace the Virtex family - long before generation 12. The tech industry just moves too fast for an architecture to last 18 years (12 generations * 1.5 years per). Or maybe Xilinx will skip V7 through V12 and jump to XIII since it's such a cool name. Have fun, MarcArticle: 124833
jjohnson@cs.ucf.edu wrote: > Thanks in advance for the help! > ---------------------------------------- > > My employer just acquired a SunFire server w 16 dual-core Opterons > (model 8220, 2.8 GHz) and 128GB of RAM. > > Despite the faster clock and memory interface, it's running my Quartus > jobs slower than a 2-year old dual-core Opteron (2.4 GHz Model 250). > Quartus is single-threaded; in my experience the only things that matter is how much memory and how much cache you have on the one core that actually runs your job. In other words, your SunFire should be just a smidgen faster than your old Opteron, and a much worse value for the money. It shouldn't be *slower*, though, since it presumably has a faster memory system, so something is still wrong. -hpaArticle: 124834
austin wrote: > [...]whereas 8 is a very lucky number in that culture. I heard an amusing, possibly apocryphal story about Boeing's new airliner. It used to be named the 7E7. The story I heard was while the Boeing rep was pitching to the Chinese they asked what "E" stood for. The quick-thinking rep replied "Eight". And now we have the 787 coming soon... :-)Article: 124835
Would some one know why SOF/EOF of Fiber Channel frame is 4 bytes? Thanks WaltersArticle: 124836
On Oct 5, 3:00 pm, jjohn...@cs.ucf.edu wrote: > Thanks in advance for the help! > ---------------------------------------- > > My employer just acquired a SunFire server w 16 dual-core Opterons > (model 8220, 2.8 GHz) and 128GB of RAM. > > Despite the faster clock and memory interface, it's running my Quartus > jobs slower than a 2-year old dual-core Opteron (2.4 GHz Model 250). > > I suspect my I.T. dept just did a generic configure, and missed out on > some major performance tuning opportunities. Maybe they've left a > power-saving mode (like PowerNow) in place? > > Can anyone suggest the biggest-bang-for-the-buck things to look at? > > I don't have root privelege, but I'm trying to help the I.T folks > along. > > uname -a: > Linux monster 2.6.9-55.ELlargesmp #1 SMP Fri Apr 20 16:46:56 EDT 2007 > x86_64 x86_64 x86_64 GNU/Linux > I'm guessing that a 2.4G processor running 32-bit Linux is faster than a 2.8G processor running 64-bit Linux. Just a guess, G.Article: 124837
On Fri, 05 Oct 2007 22:58:39 -0700, Walters <hpsham@gmail.com> wrote: >Would some one know why SOF/EOF of Fiber Channel frame is 4 bytes? Pretty much everything in FC is in multiples of 4 bytes. I guess they were considering the performance on 32 bit platforms when they designed the protocol. This wastes a little bit of bandwidth on the line, but it does make the implementation easier. -- Nony.Article: 124838
Steven Derrien wrote: > So far, the best approach I came up with was to store in a LUT the > bitcount of a 3 bit wide vector (after xoring the 2 operand for > Hamming), and use an adder tree ot obtain the Hamming distance value. You mean two LUTs for the 1's and 2's bit of the sum? That is the first level of a carry save adder tree. For a true carry save adder tree you add the 1's to form a second set of 1's and 2's, add the 2's to form a set of 2's and 4's. Repeat as needed. -- glenArticle: 124839
In article <1191621614.063609.92350@57g2000hsv.googlegroups.com>, <jjohnson@cs.ucf.edu> wrote: > >Thanks in advance for the help! >---------------------------------------- > >My employer just acquired a SunFire server w 16 dual-core Opterons >(model 8220, 2.8 GHz) and 128GB of RAM. > >Despite the faster clock and memory interface, it's running my Quartus >jobs slower than a 2-year old dual-core Opteron (2.4 GHz Model 250). I'm afraid this is roughly what I'd expect; with eight physical processors each attached to its own memory pool, many memory accesses have to be preceded by asking all seven other processors whether they have any opinions on it, and this takes quite some time. >Can anyone suggest the biggest-bang-for-the-buck things to look at? Look in the documentation for any terms like 'NUMA' and 'process pinning'; Quartus is single-threaded, so will be helped out if the OS can be convinced to allocate the memory that it uses out of the pool of memory physically attached to the processor it's running on, and if the OS is told not to move the quartus process between processors if it can be avoided. TomArticle: 124840
On Fri, 05 Oct 2007 15:45:01 -0700, emeb <ebrombaugh@gmail.com> wrote: >On Oct 5, 9:27 am, "John_H" <newsgr...@johnhandwork.com> wrote: >> "spartan3wiz" <magnus.wedm...@gmail.com> wrote in message >> >> news:1191594443.303849.241260@19g2000hsx.googlegroups.com... >> <snip>> .... On the downside the external connector it uses a Hirose 100- >> > pin FX2 connector that don't come cheap from a hobby-side view, like >> > $25 for just a single connector if I remember correctly. ... >> >> <snip> >> >> I picked up a couple connectors from Digikey 1 year ago this Tuesday at >> $6.79 each. They still show up at the same price: >> >> http://search.digikey.com/scripts/DkSearch/dksus.dll?Detail?name=H432... >> >> The Hirose connector form factor may be "inconvenient" for perf-board >> hobbyists, but we're getting beyond the age of simple perf-board circuits. >> >> - John_H > >Why not get the FX2 expansion board from Digilent? > >http://www.digilentinc.com/Products/Detail.cfm?Prod=FX2WW&Nav1=Products&Nav2=Accessory > >It's got the Hirose connector, ground plane, 0.1" grid plated-thru >holes, supply lines and lots of I/O capability and only costs about >$20. I've been using one with my Spartan3E starter kit for a few >months now and it works quite nicely. > >EB it is a jewel! thanks :) JohnArticle: 124841
On Oct 5, 9:05 pm, Weng Tianxiang <wtx...@gmail.com> wrote: > Hi cms, > Good work ! > > If you have your VHDL code open, please give me a copy. > > Thank you. > > Weng Thank you for the high asset our efforts. We haven't made final decision about future of the project yet so I can't open sources now but I think it'll be possible soon. Digitally yours, MichaelArticle: 124842
Hi Michael, 1. What is your chip used? Why is it limited to 75 MHz? 2. I haven't read the specs of JPEG-98-LS (I will certainly later). What algorithm is used to beat arithmetic encoding? Can you give some tips? WengArticle: 124843
<pomerado@hotmail.com> wrote in message news:1191534471.228883.255710@r29g2000hsg.googlegroups.com... > I'm not even sure if this might be a stupid question. I have a Xilinx > app note on daisy-chaining FPGA configurations, but can Xilinx CPLDs > be placed on the chain as well? > Yes, you can chain as many JTAG-compliant devices as you like in a JTAG chain. For example, you could chain a CPLD, an FPGA and the configuration PROM for the FPGA. No problem.Article: 124844
"Andrew Holme" <andrew@nospam.com> wrote in message news:feak35$1v$1$8300dec7@news.demon.co.uk... > > <pomerado@hotmail.com> wrote in message > news:1191534471.228883.255710@r29g2000hsg.googlegroups.com... >> I'm not even sure if this might be a stupid question. I have a Xilinx >> app note on daisy-chaining FPGA configurations, but can Xilinx CPLDs >> be placed on the chain as well? >> > > Yes, you can chain as many JTAG-compliant devices as you like in a JTAG > chain. For example, you could chain a CPLD, an FPGA and the configuration > PROM for the FPGA. No problem. > From an electrical and JTAG spec perspective you are correct. But the software that you use must either directly supports all of the devices in the chain or allow for some form of bypassing 'foreign' devices in that chain. It's not really a 'JTAG issue' at that point, but more of a tool support issue. Consider a single JTAG chain consisting of devices from Actel, Altera, Lattice and Xilinx. JTAG download software from any of the vendors will only work if they allow those 'other' devices to be bypassed while you're working with one particular vendor's part. Whether that can happen or not simply needs to be investigated with the JTAG software tool. Alternatively, one could use JTAG software from a neutral party (such as Asset-Intertech and several others) to get at all of the parts. There are tradeoffs to that approach as well, but again something to investigate. There are also some devices that really want to be 'first' in the chain. So far I've only run into this as an issue with certain processors that use JTAG as the interface for software code debug but the problem is that the JTAG software assumed that the processor was the first and only device in the JTAG chain and flat out didn't work if it wasn't. It wasn't a JTAG hardware issue, it was the software that the vendor supplied but if you need to use the software to debug code (and yes you do) then you need to use that vendor's tool. Programming/verifying CPLDs is somewhat more amenable to other solutions but just another example of how the software that will be used is really the determining criteria for how you lay out the JTAG chain. KJArticle: 124845
On 7 , 14:11, Weng Tianxiang <wtx...@gmail.com> wrote: > Hi Michael, > 1. What is your chip used? Why is it limited to 75 MHz? We use Altera StratixII GX EP2SGX30DF780C3 (http://altera.com/products/ devices/stratix2gx/s2gx-index.jsp) Single-clock per pixel implementation results in a big combinational fragments that impact project speed. According to the base JPEG-LS standart we have to update four variables for each pixel during one clock cycle in the fact. The bad moment is that core speed significally degradates when pixel width ascending. > > 2. I haven't read the specs of JPEG-98-LS (I will certainly later). > What algorithm is used to beat arithmetic encoding? Can you give some > tips? The JPEG-LS algorithm includes two operation: context modeling and encoding prediction error by the Golomb-Ryce procedure. For natural images prediction error has a geometrical distribution therefore Golomb coding is optimal for. I have an idea about model enhancement and error encoding which makes implementation faster but in this case core will not be compatiable with ITU-T 87 standard. I think finally there are two branches of the core: slow, but fully- compatable with ITU-T 87 one and own high-performance compressor. Digitally yours, MichaelArticle: 124846
On Thu, 04 Oct 2007 15:47:51 -0700, pomerado@hotmail.com wrote: > I'm not even sure if this might be a stupid question. I have a Xilinx > app note on daisy-chaining FPGA configurations, but can Xilinx CPLDs be > placed on the chain as well? One little note: pay attention to differing JTAG voltage levels... Peter WallaceArticle: 124847
Hi, I am looking at various alternatives for interconnect testing, especially for prototype boards that have BGAs. I am very interested to know what other people are using for JTAG interconnect testing, and what your debugging experiences are? I have Scanseer, and I like it very much. I can do some interconnect testing and real-time monitoring with Scanseer. Another one out there is JSCAN from Macraigor Systems. I have not used JSCAN. The test script recorder stores in SVF looks like it could be good. Does anyone do prototype interconnect testing with: * Amontec JTAGkey? * the Lattice tools - ispVM? Any other suggestions or experiences with interconnect testing (besides X-ray:) )? Thanks & cheers, Tony BurchArticle: 124848
On Oct 7, 5:43 pm, "Tony Burch" <t...@burched.com.au> wrote: > Hi, > I am looking at various alternatives for interconnect testing, especially > for prototype boards that have BGAs. I am very interested to know what other > people are using for JTAG interconnect testing, and what your debugging > experiences are? > > I have Scanseer, and I like it very much. I can do some interconnect testing > and real-time monitoring with Scanseer. Another one out there is JSCAN from > Macraigor Systems. I have not used JSCAN. The test script recorder stores in > SVF looks like it could be good. > > Does anyone do prototype interconnect testing with: > * Amontec JTAGkey? > * the Lattice tools - ispVM? > > Any other suggestions or experiences with interconnect testing (besides > X-ray:) )? > > Thanks & cheers, > Tony Burch Hey Tony, The biggest issue with interconnect issues is developing the vectors. Getting the vectors to the JTAG controller is small by comparison. Just about any JTAG device -should- work just fine. I've bit-banged JTAG, and used high-end dedicated controllers. The Amontec could be a good choice. It runs at 12Mbps max, which should be OK for most applications. It uses a real common chip; the value add is the support, which seems to be much better than average. Near as I can tell, all the high-end JTAG systems add are the ability to import scan files, and nifty GUIs. Just my opinions, G.Article: 124849
"Tony Burch" <tony@burched.com.au> wrote in message news:47097d29$0$18984$afc38c87@news.optusnet.com.au... > Hi, > I am looking at various alternatives for interconnect testing, especially > for prototype boards that have BGAs. I am very interested to know what > other people are using for JTAG interconnect testing, and what your > debugging experiences are? > > I have Scanseer, and I like it very much. I can do some interconnect > testing and real-time monitoring with Scanseer. Another one out there is > JSCAN from Macraigor Systems. I have not used JSCAN. The test script > recorder stores in SVF looks like it could be good. > > Does anyone do prototype interconnect testing with: > * Amontec JTAGkey? > * the Lattice tools - ispVM? > > Any other suggestions or experiences with interconnect testing (besides > X-ray:) )? > > Thanks & cheers, > Tony Burch > > Tony, I've used Corelis for many years. Their latest toolset works really well in providing coverage and fault analysis. Their support is very good, too. They also have standard test suites for RAMs that are hooked up to FPGAs, but be sure you drive the clock from the FPGA if you want this feature to work. Their latest stuff works for ac couple paths as long as the boundary scan cell supports this feature. Talk to Karla May. She knows her stuff. Bob
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