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Hi All,
I am designing my first real clock domain crossing circuit. My
problem is a high speed wrapper for a low speed device. What is the
general approch to be followed. I will tell you my approch and please
correct me if needed.
The high speed wrapper will write to its registers at 100MHz. First i
am converting this registers to 1MHz domain, using two flops both
using a 1MHz clock. Now the data is safe in the 1MHz domain(And then i
will run some 1MHz state machine using this data). But the problem is
with the write at the first domain. We can have upto 50 writes (a
write wil lhappen only in two cycles) in the wrapper registers. For
this we can take the latest value to the 1MHz domain. But we must
indicate to the 1MHz domain that there was a write in the wrapper in
any of these possible 50 cycles. If any cycle was a write then in the
1MHz domain we must restart the state machine. How this is possible. I
hope i have made myself clear. I cant describe the correct usage since
it is company related things.
__ __ __ __ __ __ __ __ __ __
__ __ __
_| |__| |__| |__| |__| |__| |__| |__| |__| |__| |
__| |__| |__| |__
<w1><r1 ><w2> <w3> <r2 >
________ ________
________ ________
| |_________| |_________| |
_________| |_________
________
________ ________
__________________| |_________| |
_________| |_________
<fsm strd wth w2 data>
<fsm shd restrt wth w3 data
regards
Sumesh V S
Article: 121476subint wrote: > On Jul 4, 9:03 pm, John_H <newsgr...@johnhandwork.com> wrote: >> subint wrote: >>> Hi all, >>> I wrote a generate loop to generate a switching logic. I am getting >>> the expected circuit from the synthesizer(synplify). But it's not >>> working in the simulator ( Modelsim ). >>> The code is like this >>> genvar i; >>> generate >>> for(i=0;i<elements;i=i+1) begin:A1 >>> assign source_out[i*8+:8] = (enable[i])?result[address[i*6+:6]*8+: >>> 8]:source_in[i*8+:8]; >>> end >>> endgenerate >>> The requirement is, i have two bus(64 bytes each) and each byte of the >>> output of the block can be from the corresponding position from the >>> source or from anywhere (according to the address) from the result bus. >> In what way is it not working? Is the source_out always one of the two >> results? Are you certain the enable isn't an "x" value? > > Hai thanks for the reply > I dont know how the simulator is behaving. The inputs are correct,no x > driving. > when i enabled the the first element and given zero as the address it > was reading from the result bus > but when i changed the address of second element to 1, the element is > taken from the source_in even though > the enable is high. > When i tried to change the coding style > by (i*8+:8 to i*8+7:i*8 ) the simulator saying the range specified > cannot be a variable > what is simple to method of coding this logic so that it work in the > simulator Your code looks valid for what you want to achieve. I'd suggest using a simulator for what a simulator does best: when you change your input values, print a big list of the input vectors, the enables, and the result for your various indicies. You *shouldn't* have a problem. If the simulator has invalid inputs, it can give invalid results which is why I was asking about the x values. If you print out your data and sift through it, you might be surprised about why it comes out bad. I'd suggest that for each i, you display enable[i], address[1*6+:6], result[address[i*6+:6]*8+:8], source_in[i*8+:8], and source_out[i*8+:8]. This should tell you either what input value isn't behaving as you expect or it will tell you explicitly how the simulator is failing you. Break it down. This is debug.Article: 121477
azzhang2007@hotmail.com wrote: > I use synplify 8.8 to synthesis my design. And my design contain > xilinx ip core (generated by core generator). My design can be > synthesis with XST. But when I use synplify 8.8, synthesis cannot be > done successfully. It seems that synplify does recognise xilinx ip > core.Do i need to set some option? > > Thanks for your help! In what way does Synplify not recognize the core that you added to your Synplify project? Is it a Black Box wrapper that you added to the project? Or is the core supplied as a Verilog or VHDL file rather than a black box wrapper for a pre-synthesized core that gets brought together in the back-end tool?Article: 121478
On Jul 5, 8:10 am, vssumesh <vssumesh_a...@yahoo.com> wrote: > Hi All, > I am designing my first real clock domain crossing circuit. My > problem is a high speed wrapper for a low speed device. What is the > general approch to be followed. I will tell you my approch and please > correct me if needed. > The high speed wrapper will write to its registers at 100MHz. First i > am converting this registers to 1MHz domain, using two flops both > using a 1MHz clock. Now the data is safe in the 1MHz domain(And then i > will run some 1MHz state machine using this data). But the problem is > with the write at the first domain. We can have upto 50 writes (a > write wil lhappen only in two cycles) in the wrapper registers. For > this we can take the latest value to the 1MHz domain. But we must > indicate to the 1MHz domain that there was a write in the wrapper in > any of these possible 50 cycles. If any cycle was a write then in the > 1MHz domain we must restart the state machine. How this is possible. I > hope i have made myself clear. I cant describe the correct usage since > it is company related things. > __ __ __ __ __ __ __ __ __ __ > __ __ __ > _| |__| |__| |__| |__| |__| |__| |__| |__| |__| | > __| |__| |__| |__ > > <w1><r1 ><w2> <w3> <r2 > > ________ ________ > ________ ________ > | |_________| |_________| | > _________| |_________ > ________ > ________ ________ > __________________| |_________| | > _________| |_________ > > <fsm strd wth w2 data> > > <fsm shd restrt wth w3 data > > regards > Sumesh V S I can't really see your diagram, but there are a couple of points I can make. 1) Is your 1 MHz domain synchronous to the 100 MHz domain - i.e. do you just divide 100 MHz clock by 100 to make 1 MHz clock? If not and your domains are truly asynchronous you need to be sure your sampling of registers is coherent when you change clock domains. For example if you are looking at 8 bits of data written synchronously to 100 MHz and just put all 8 bits through 2 flip- flops on the 1 MHz clock, you can sometimes get some bits from before and other bits from after a write event. Since your clocks have a very large difference in frequency, it may make sense to sample the 1 MHz clock in the 100 MHz domain and make a clock enable after the rising edge of 1MHz clock that lasts one cycle of the 100MHz clock. Use this clock enable and the 100 MHz clock as the first stage of your synchronizer to ensure data coherency. 2) Generally when you need to indicate an update to an asynchronous process you need handshakes. You can have a register that is set when any of the data registers are written in the 100 MHz domain, and cleared when the 1 MHz domain acknowledges the change. This can have a race condition if changes happen frequently since the reset signal could come just as another update happens. Another approach is similar to a FIFO controller where you count up with one counter on any 1 MHz clock period where an update has occured, and count up with another counter when the 1 MHz logic recognizes the change. HTH, GaborArticle: 121479
Jesper.Kristensen@tellabs.com wrote: > Hello Group. > > Having a home-made PCB board which can adopt to both Spartan-3A > XC3S200A and XC3S400A FPGAs in the same FBGA320 footprint, we are > having great troubles getting the 400A image of the logic to work > stable, while the 200A image seems to work perfectly with the same > logic. > The symptoms are that various bits or groups of bits seem to "hang" > whenever we try to get them on the uController Bus for reading etc.. > > We have tried using both Xilinx ISE 8.2 and 9.1 as Fitter, but with > the same non-stable, although *different* result in respect of which > bits cannot be reached. > > The 3 I/Os being the difference between the two Spartan-3A variants > are *not* connected in the PCB. > Voltages are correct, and the timing should absolutely be no problem > in the design (Fmax 4 times over). > We have no troubles loading the FPGA devices in two different > configurations. > The problems seems consistent among boards with the same FPGA - 200A > or 400A. > > - Have you heard of such problems...? > > - Or do you just have some type of clue...? > > Thanks in advance, > > Jesper. The kind of problem you mention is often an issue of poor timing where asynchronous boundaries are crossed improperly and the unconstrained timing path is simply different between the two place & routes, not so much 200A vs 400A. Your timing report can generate more than a constrained-path timing report which must show proper compliance to your needs; you can generate a list of unconstrained paths as well. Maybe something important was forgotten in the timing constraints you did intend to specify and you'll discover what that was when you generate the unconstrained paths.Article: 121480
On Jul 3, 2:43 pm, Patrick Dubois <prdub...@gmail.com> wrote:
> On 19 juin, 09:23, "Jeremie" <nos...@here.com> wrote:
>
>
>
> > Hi everyone,
>
> > Could someone with experience or simulation tools provide information on the
> > hardware requirements to interconnect Virtex2pro and Virtex4 with rocketio
> > at 2.5Gb/s.
> > The simpler the better, DC if possible and if not AC. I'd like to know the
> > termination voltages and anything needed on the lines.
> > v2pro<=>v2pro and V4<=>V4 works.
> > I can't get the proper setup to run aberttest V4 to v2pro (v2pro to V4 is
> > easier) so if you have a working setup I'd be glad if you could describe it.
>
> > Thanks,
>
> > Best regards,
>
> > Jeremie
>
> > PS: If someone feels like describing his V5 setup I'm sure that will be
> > useful for many people.
>
> A little late response but I'd be interested to know if you have made
> progress on this issue. I unfortunately cannot provide help yet but we
> will soon (in 2 weeks) have to connect a V4 to a V2Pro through
> RocketIO (Aurora) in the lab.
>
> Regarding the BERT core from the Chipscope serial IO toolkit, I read
> the manual but I don't see how I could use this to test a V4-V2Pro
> connection unfortunately. Actually, it seems limited to a single FPGA.
> I don't see how to control two FPGAs from one Chipscope interface...
>
> Patrick
Hi Patrick,
As far as I know, you need to use two PC's or else you
need a PC with a parallel port cable and a USB cable and open up two
Chipscope Analyzers on the same PC. Good luck..
-- parag
Article: 121481Hello all, I am trying to generate several MAC FIR Filter cores for the same project. The filters range in length from 32 to 63 taps. I do not have any problem generating the core, but have noticed that the core generates a MIF file with a default name of "DATA_COEF_BUFFER.mif". For example, if I generate a filter with the name my_fir, all the files, including an additional MIF file are generated with the name my_fir.*. However, the MIF file pointed to in the my_fir.vhd file is DATA_COEF_BUFFER.mif. This is not too much of a problem if you have one such core. However, I would like to have several. So for my case: my_fir_1.vhd my_fir_2.vhd each generate DATA_COEF_BUFFER.mif (the second core generated overwrites the first file). In order to simulate the cores, Modelsim wants the DATA_COEF_BUFFER.mif for each of the cores in the simulation directory. I tried changing the vhd file to point at the my_fir.mif, but the simulation does not work. I am hoping that this is just a simulation problem, and that synthesis will look at he my_fir.mif instead of DATA_COEF_BUFFER.mif, but I would like a simulation of this model before moving to hardware. Any ideas? Thanks!Article: 121482
Andreas, I suspect that the ICAP core must wait until the configuration logic is completely finished, and idle. There is no means for resolving access to the configuration logic (that is on the list for 45nm). If there is a contention for access, there is no defined "winner" and both applications requesting access will lose. I will ask to see what the sequence might be, and why it appears you have to wait as long as you do. AustinArticle: 121483
water9580@yahoo.com wrote: > V4 FPGA has independently RXSIGDET port signal,but V5 not. > > how to detect the signal on V5 GTP? > Page 155 http://direct.xilinx.com/bvdocs/userguides/ug196.pdf You need to configure the "loss of Sync (LOS) state machine for the standard you wish to use. AustinArticle: 121484
On Jul 3, 3:46 pm, austin <aus...@xilinx.com> wrote: > page 234, > > http://www.xilinx.com/bvdocs/userguides/ug332.pdf Thank you! This is what I was looking for. > details the start up sequence. If you use the default, and you must not > wait for DCM to LOCK (as they won't), then you need to know the CCLK This I understand. I do NOT have STARTUP_WAIT set on any of the DCMs. > rate, and you will see the delay from GTS. Table 12-7. The state > machine for the start up progresses as shown. Using bitgen options, you > may re-arrange the start up sequence, if for some reason you wish one > even to happen before another (should have a really good reason, > however, as the default sequence is the easiest to debug and understand > because it is the default). And looking at Figure 12-12, it makes sense that even 1 CCLK would be adequate. Since GWE is released after GTS, the reset SRL16 won't even begin clocking until 1 CCLK after GTS is released. Thus it allows for the feedback clock to stabilize. Thank you very much for your help! That is the exact information I was looking for. PeteArticle: 121485
PlayDough, No problem. Sorry it took so long to find what you needed. AustinArticle: 121486
PretzelX, Xilinx recognizes the investment made when choosing a processor/architecture/language; and has made every effort to follow the "golden rule": Never obsolete your processor. And, so far, we have never given any customer cause to worry. There are no plans to (ever) change this policy. Our track record also speaks to keeping this commitment. The same can not be said for our competitors. AustinArticle: 121487
austin wrote: > PretzelX, > > Xilinx recognizes the investment made when choosing a > processor/architecture/language; and has made every effort to follow the > "golden rule": Never obsolete your processor. How is it possible to obsolete a soft core? -- Mike TreselerArticle: 121488
I have figured it out. (well part of it) I finally tried it with a Platform USB cable belonging to my Avnet FAE, and it WORKED! I had been using a Parallel Cable III (I guess I left that out). I was certain that this would have no effect. I still can't explain why JTAG partially works, but won't read device id. I would love for someone to confirm this or explain it. My guess would be some sort of voltage incompatibility (But I was *sure* changing the cable would have no effect, so how good are my guesses?) Thank you to everyone for your suggestions. Alan Nishioka On Jul 3, 11:06 am, Alan Nishioka <a...@nishioka.com> wrote: > I am trying to get an xc3s250e-4tq144c to configure using JTAG. > > 1. impact reads 0x00000000 as idcode > This causes impact to error out during identify with a strange > error about missing bsdl's > 2. JTAG works using impact debug mode. I can put it in bypass and > also see the length of the instruction register. I can see data > shifting in and out so I know JTAG works. > 3. Part markings are: > XC3250E > TQ144AGQ0601 > D1392255A0 > 4C > so it is a step 0 part. > 4. I have tried impact 8.1.3 and 9.1 > 5. I get identical results with two pc boards. > 6. Same software / computer / cable setup works fine with a virtex2p > design. > 7. All power supplies look good. (1.2Vint, 2.5Vaux, 3.3Vio) > 8. spartan-3e is the only part in the JTAG chain. > > I have tried removing all the parts except the spartan and power to > make sure nothing else was interfering with it. > > I have not made any progress with my Avnet FAE and Xilinx webcase so I > thought to try here. > > I have run out of things to try. Does this look familiar to anyone? > Any ideas to try? > > Alan Nishioka > a...@nishioka.comArticle: 121489
On Jul 5, 1:19 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > How is it possible to obsolete a soft core? By offering it in the form of device-specific macros or semi-compiled descriptions. Only if the processor core is true "source code" written in terms of generic or practically duplicatable library objects do you have immunity from obsolecence. Otherwise, you are dependent on the targeted devices continuing to be available, or whoever has the true source code offering you new versions that work on newer devices, or some third partner creating a workalike.Article: 121490
Mike, Easy. Just introduce a "new and improved" incompatible version, and remove support for the old one. Another way of saying "the original soft processor was so bad, that we redesigned it..." Thankfully, MicroBlaze(tm) soft processors followed the Harvard RISC architecture, and we got it right the first time. But, enough of this venture into the dark and murky realm of choice of microprocessor architectures and language. The biggest, and most important reason to choose a processor is what you already have written: can it be targeted at your choices? AustinArticle: 121491
Alan, I did bring up the 2.5 volt issue, but I guess you were chasing some other issue. Virtex 4, Spartan 3 (basically, everything since the first 90nm products) did change from 3.3 volts to 2.5 volts (3.3V compatible...) on the JTAG. It is the "compatible" that is not so easy: older programming cables, aren't. Sorry you got bit by this. Glad to hear you did not have a toasted chip. AustinArticle: 121492
On Jul 5, 10:41 am, vt2001cpe <vt2001...@gmail.com> wrote: > Hello all, > > I am trying to generate several MAC FIR Filter cores for the same > project. The filters range in length from 32 to 63 taps. I do not have > any problem generating the core, but have noticed that the core > generates a MIF file with a default name of "DATA_COEF_BUFFER.mif". > > For example, if I generate a filter with the name my_fir, all the > files, including an additional MIF file are generated with the name > my_fir.*. However, the MIF file pointed to in the my_fir.vhd file is > DATA_COEF_BUFFER.mif. > > This is not too much of a problem if you have one such core. However, > I would like to have several. So for my case: > > my_fir_1.vhd > my_fir_2.vhd > > each generate DATA_COEF_BUFFER.mif (the second core generated > overwrites the first file). In order to simulate the cores, Modelsim > wants the DATA_COEF_BUFFER.mif for each of the cores in the simulation > directory. I tried changing the vhd file to point at the my_fir.mif, > but the simulation does not work. > > I am hoping that this is just a simulation problem, and that synthesis > will look at he my_fir.mif instead of DATA_COEF_BUFFER.mif, but I > would like a simulation of this model before moving to hardware. > > Any ideas? Thanks! Additionally, I have noticed that the my_fir.mif contains a correct hex copy of the coefficients. However, the DATA_COEF_BUFFER.mif has incorrect values. Regenerating the core does not correct the discrepancies in the mif files.Article: 121493
On Jul 5, 9:21 am, John_H <newsgr...@johnhandwork.com> wrote: > Jesper.Kristen...@tellabs.com wrote: > > Hello Group. > > > Having a home-made PCB board which can adopt to both Spartan-3A > > XC3S200A and XC3S400A FPGAs in the same FBGA320 footprint, we are > > having great troubles getting the 400A image of the logic to work > > stable, while the 200A image seems to work perfectly with the same > > logic. > > The symptoms are that various bits or groups of bits seem to "hang" > > whenever we try to get them on the uController Bus for reading etc.. > > > We have tried using both Xilinx ISE 8.2 and 9.1 as Fitter, but with > > the same non-stable, although *different* result in respect of which > > bits cannot be reached. > > > The 3 I/Os being the difference between the two Spartan-3A variants > > are *not* connected in the PCB. > > Voltages are correct, and the timing should absolutely be no problem > > in the design (Fmax 4 times over). > > We have no troubles loading the FPGA devices in two different > > configurations. > > The problems seems consistent among boards with the same FPGA - 200A > > or 400A. > > > - Have you heard of such problems...? > > > - Or do you just have some type of clue...? > > > Thanks in advance, > > > Jesper. > > The kind of problem you mention is often an issue of poor timing where > asynchronous boundaries are crossed improperly and the unconstrained > timing path is simply different between the two place & routes, not so > much 200A vs 400A. Your timing report can generate more than a > constrained-path timing report which must show proper compliance to your > needs; you can generate a list of unconstrained paths as well. > > Maybe something important was forgotten in the timing constraints you > did intend to specify and you'll discover what that was when you > generate the unconstrained paths. Also take a look at the Vccint supply to make sure you're not getting supply droop. With the same design loaded, the dynamic power will be about the same for the 400A as the 200A, but the static power will be higher in the 400A, perhaps enough to make a voltage difference. Also note that in a larger part it is easier to get large routing delays on unconstrained paths. Another headache with larger parts in the same package is that pin to pin delays can vary significantly because the larger part will not necessarily place adjacent IOB's where there were adjacent IOB's in the smaller part. Usually once the IOB's in the silicon exceed the bonding for the package you start to see large groups of unbonded IOB's between adjacent bonded IOB's in the middle of a bank. Good Luck, GaborArticle: 121494
cs_posting@hotmail.com wrote: > Only if the processor core is true "source code" written in terms of > generic or practically duplicatable library objects do you have > immunity from obsolecence. Otherwise, you are dependent on the > targeted devices continuing to be available, Yes. The device can become obsolete, but if I have the netlist and the device, the "processor" usage of the device cannot be obsoleted. -- Mike TreselerArticle: 121495
On Jul 5, 4:44 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > Yes. The device can become obsolete, > but if I have the netlist and the device, > the "processor" usage of the device cannot > be obsoleted. Only so long as you can buy the devices. Obsolecence doesn't usually imply that the devices in your company stock room / desk drawer stop working, it implies that there aren't and aren't going to be any more in your distributor's stock room for you to buy. Or it may imply that you are locked into using old technology devices and unable to take advantage of newer ones which may badly needed advantages / ability to keep up with your market. At that point, the netlist is only going to help you if you have alternate-device versions of all of the components that it instantiates.Article: 121496
Sylvain Munaut wrote: >> Come on Xilinx. **PLEASE** release some signed hardware drivers!! >> Ditto Altera....... > > Come on Microsoft, let the user do what they want with their _own_ > hardware. Unlikely to happen, since Microsoft is trying to be Hollywood's best friend in the lets-screw-the-user game. -hpaArticle: 121497
Thanks Gabor for these valuable replys. First of all, how can i draw waveform diagrams in this group? I have seen lot of sessions with neat diagarm, my diagarm was also good when i draw it on the tesxt window but when in converted to the html page it somehow got distotred. How can i share my diagrams with you? Comming to your second suggestion, that ack from the 100MHz domain to the 1MHz domain is exactly what i want, but how we can do that? The flag which indicates that is set on 100MHz clock and rest on 1MHz clock. Is that possible to use two clocks in a single FF? I am thinking of another process similar to your suggestion that the flag will be set at 100Mhz, but will also be reset at 100MHz when an edge happend at the 1MHz signal. But these information that an edge happend at the 1MHz location is also needed to be synchronised to the 100MHz domain. That will delay it by two more cycles in the 100MHz domain. Your first suggestion i could not understand fully. What will happen if i use only two flops operting at 1MHz clock. Please explian me why some bits will be differnt from other bits. My two clocks are fully asynchronus.Article: 121498
vssumesh wrote: > Thanks Gabor for these valuable replys. First of all, how can i draw > waveform diagrams in this group? I have seen lot of sessions with neat > diagarm, my diagarm was also good when i draw it on the tesxt window > but when in converted to the html page it somehow got distotred. How > can i share my diagrams with you? 1) Use a fixed size font when drawing it. 2) Make sure your client does cut the line automatically at a certain number of character. And in any case try to keep all the line quite short (likee ~75 char)Article: 121499
hi all experts could you recommend good USB analyzer for me i am an new USB driver developer and my boss wanted me to investigate which one is the best choice 1.support 1.1/ 2.0 / OTG specification 2.can analyze RNDIS/MassStorage/Serial pactet 3.record potential and current 4.FPGA 5.have source code to provide correctness
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