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> And, the MicroBlaze(tm) uP soft core use agreement stipulates that it is > to be used on Xilinx FPGAs, only. We have no incentive to allow its use > in an ASIC. You certainly used to have the option. I was even quoted a price. Cheers, JonArticle: 121676
Antti, In the user guide I pointed to, there is no reference to any agreement. Your link points to the use agreement. It is not specific to anything. It has to be specifically stated in each and every document that the use agreement applies, and how it applies. I did find one reference to "use within a Xilinx FPGA" in one of the .pdf marketing documents, but that reference did not provide any details, nor any restrictions. I suspect that one .pdf document is not considered binding, or legal, as it does not refer to any "real" agreement (like the link you provide). One sentence like "use within a Xilinx FPGA" is more of a desire to keep the PicoBlaze 'in the family....' than any kind of binding legal use agreement. I will go ahead and ask, Austin Antti wrote: > On Jul 11, 3:25 pm, austin <aus...@xilinx.com> wrote: >> X-User, >> >> PicoBlaze is offered "as - is", and subsequently has no restrictions on >> its use. >> >> It is in the 'spirit' of an open core, as in, we really do not mind >> where and how it may be used. >> >> It is also "unsupported" by the Xilinx Support system. If we find >> something that is a bug, we will fix it, but we do not offer any >> guarantees about its use, or performance like we do for the >> MicroBlaze(tm) or PowerPC(tm) processors. >> >> http://www.xilinx.com/bvdocs/userguides/ug129.pdf >> >> Austin > > Austin, > > it looks like you dont know what you are talking about: > > ASFAIK PicoBlaze is under XDL License - > http://www.xilinx.com/bvdocs/appnotes/Design_License.pdf > > those it is resctricted for the use in Xilinx devices only. > => this is not OPEN SOURCE and FREE FOR ANY USE ! > > so if you dont care in what silicon it is used thats fine, > but officially Xilinx lawers could prevent ASICs with PicoBlaze > inside from being used. > > or is there any other way to understand the XDL terms? > > Antti > > > > > > > > > > > > > > > >Article: 121677
Jon, If you ask, we reserve the right to change anything and everything, for a price. It is called "being in business." AustinArticle: 121678
On Jul 11, 4:02 pm, Jon Beniston <j...@beniston.com> wrote: > > And, the MicroBlaze(tm) uP soft core use agreement stipulates that it is > > to be used on Xilinx FPGAs, only. We have no incentive to allow its use > > in an ASIC. > > You certainly used to have the option. I was even quoted a price. > > Cheers, > Jon MB VHDL license was some 19KUSD as much as i recall.. AnttiArticle: 121679
http://www.xilinx.com/ipcenter/doc/microblaze_click_core_source_license.pdf Is the MicroBlaze source code license. AustinArticle: 121680
<miche> wrote in message news:4694e4c9$1_3@mk-nntp-2.news.uk.tiscali.com... >I have received the following error warning: > > > Cpld:828 - Signal 'done.RSTF' has been minimized to 'GND'. > > > Waiting with antissipation, > Thanks Waiting might not do anything for you. Do you want help? There's a chance that your logic is not doing what you expect. Have you run this through simulation software? My guess - if you do - is that the signal will always be ground because the logic reduces to always-zero output.Article: 121681
Antti, You are right, I am wrong. To get the source code, you have to agree to a license, which states that the code is only to be used in a Xilinx device. I suppose that the only reason why we have this restriction is to "protect" designs in FPGAs from migrating to ASICs. AustinArticle: 121682
Hi, I am trying to use a Memory Interface generated by MiG (Memory Interface Generator 1.72) as a symbol in a schematic based project. CORE Generator doesn't allow me to select schematic based as a design entry when I use the Memory Interface Generator. How can I integrate the memory interface in a schematic based design so I can used the memory for my applications? It is for the 2 x 32 Megabytes MT46V16M16-6T:F chips on the ML402 board.Article: 121683
austin <austin@xilinx.com> wrote: >All, > >And, the MicroBlaze(tm) uP soft core use agreement stipulates that it is >to be used on Xilinx FPGAs, only. We have no incentive to allow its use >in an ASIC. > >I think for ASIC development, the issue is all risk: as in, there must >not be any risk at all. Thus, you see ARM uP's in most low power/low >cost ASICs. The 'guarantee' allows one to get real support (which is >sadly lacking in open cores). Higher end/higher performance ASICs use >MIPs, or the PowerPC. > >Recently opencores.org put itself up for sale, and is (effectively) out >of business. This is exactly why using open cores represents a huge >risk. Since no one has figured out how to make money off open cores, >there is no incentive at all to give your hard work away for free. Thats just as stupid as saying no profit is being made with Linux. Stop yelling 'Xilinx is the best' at all cost and try again Austin -this time without making a fool out of yourself- :-) * A lot of stuff on Opencores is either GPL licensed which basically means you'll have to pay for commercial use or are stripped down versions of real products. In both cases you'll get support if you pay for the product. And if things really get nasty, you can always modify the source code if necessary. Thats the beauty of open source. If you have the source code, you are not locked in by the manufacturer for support. *please note the smiley! -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 121684
On Jul 11, 5:06 pm, ML402 <> wrote: > Hi, I am trying to use a Memory Interface generated by MiG (Memory Interface Generator 1.72) as a symbol in a schematic based project. > > CORE Generator doesn't allow me to select schematic based as a design entry when I use the Memory Interface Generator. > > How can I integrate the memory interface in a schematic based design so I can used the memory for my applications? > > It is for the 2 x 32 Megabytes MT46V16M16-6T:F chips on the ML402 board. Hi, Generate the Memory Interface using Coregen. The easiest way will be to launch Coregen stand-alone (Start -> Run -> coregen). Create a coregen project in a new directory and generate the core. The memory interface HDL will be placed in the rtl directory. Add these files to your ISE project (make sure the files are moved to the project directory), right click the top level of the memory interface (normally tx_mem_interface_top) and select "Set as top module". After this under Design Utilities you will find Create Schematic Symbol. Set your own top level again as the top level of the project and you will find the generated schematic under Symbols -> Your project category. Cheers JacoArticle: 121685
On 11 Jul, 17:22, n...@puntnl.niks (Nico Coesel) wrote: > austin <aus...@xilinx.com> wrote: > >All, > > >And, the MicroBlaze(tm) uP soft core use agreement stipulates that it is > >to be used on Xilinx FPGAs, only. We have no incentive to allow its use > >in an ASIC. > > >I think for ASIC development, the issue is all risk: as in, there must > >not be any risk at all. Thus, you see ARM uP's in most low power/low > >cost ASICs. The 'guarantee' allows one to get real support (which is > >sadly lacking in open cores). Higher end/higher performance ASICs use > >MIPs, or the PowerPC. > > >Recently opencores.org put itself up for sale, and is (effectively) out > >of business. This is exactly why using open cores represents a huge > >risk. Since no one has figured out how to make money off open cores, > >there is no incentive at all to give your hard work away for free. > > Thats just as stupid as saying no profit is being made with Linux. > Stop yelling 'Xilinx is the best' at all cost and try again Austin > -this time without making a fool out of yourself- :-) * > > A lot of stuff on Opencores is either GPL licensed which basically > means you'll have to pay for commercial use or are stripped down > versions of real products. In both cases you'll get support if you pay > for the product. And if things really get nasty, you can always modify > the source code if necessary. Thats the beauty of open source. If you > have the source code, you are not locked in by the manufacturer for > support. > > *please note the smiley! > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nl indi.microfpga.com is bsd open source (acknowledge of copyright but free to develop) but not developed to full extent of utility yet, i need a good protocol reference for IDE LBA access so i can develop a hard disk boot system (cheaper than flash, and would give many <=64MB bootable images on multi GB disks). as soon as i have the disk access protocols written as code then the vhdl can be completed (currently a 16 cycle template for cheap 8 bit memory). personally as a developer of open source processor, i have found that obtaining development kit and access to stable housing are the biggest challenges, as no profit will be seen until i have a saleable development 19in 1U rack based arround altera kit, with enough of a software base. cheersArticle: 121686
On Jul 11, 5:34 pm, Jaco Naude <naude.j...@gmail.com> wrote: > On Jul 11, 5:06 pm, ML402 <> wrote: > > > Hi, I am trying to use a Memory Interface generated by MiG (Memory Interface Generator 1.72) as a symbol in a schematic based project. > > > CORE Generator doesn't allow me to select schematic based as a design entry when I use the Memory Interface Generator. > > > How can I integrate the memory interface in a schematic based design so I can used the memory for my applications? > > > It is for the 2 x 32 Megabytes MT46V16M16-6T:F chips on the ML402 board. > > Hi, > > Generate the Memory Interface using Coregen. The easiest way will be > to launch Coregen stand-alone (Start -> Run -> coregen). Create a > coregen project in a new directory and generate the core. The memory > interface HDL will be placed in the rtl directory. Add these files to > your ISE project (make sure the files are moved to the project > directory), right click the top level of the memory interface > (normally tx_mem_interface_top) and select "Set as top module". After > this under Design Utilities you will find Create Schematic Symbol. Set > your own top level again as the top level of the project and you will > find the generated schematic under Symbols -> Your project category. > > Cheers > Jaco I might have to add: This will only create a schematic symbol for the controller. You would need to do the same for your memory model. CheersArticle: 121687
Nico, I don't make things up. I just read about it in eetimes. opencores is up for sale, and there is no one who cares to "take it." What does that say? AustinArticle: 121688
On 11 Jul, 16:10, austin <aus...@xilinx.com> wrote: > Jon, > > If you ask, we reserve the right to change anything and everything, for > a price. > > It is called "being in business." > > Austin Ok, sure. But at one point you was offering a ASIC license for $150k. Cheers, JonArticle: 121689
Hello, Here is my program, if you want to compile it and see for yourself, it would be wonderful. Waiting with antissipation, Thanks. module vv(clk1, clk2, reset1,reset2, addr1); input clk1; input clk2; input reset1; input reset2; output [4:0] addr1; wire [4:0] addr1; wire int_mux_clk; wire int_done; mmux mymux(.a(clk1),.b(clk2),.sel(int_done),.y(int_mux_clk)); mcounter mycounter(.clk(int_mux_clk),.rs(reset1),.ad(addr1)); mdetect mydetect(.a(addr1[4]),.rs(reset2),.y(int_done)); endmodule module mmux(a,b,sel,y); input a, b, sel; output y; reg y; always @ (a or b) begin if (sel==0) y=a; else y=b; end endmodule module mcounter (clk,rs,ad); input clk,rs; output [4:0] ad; reg [4:0] ad; always @ (posedge clk or posedge rs) begin if(rs) ad=0; else ad=ad+1; end endmodule module mdetect(a,rs,y); input a; input rs; output y; reg y; always @(a or rs) begin if (a) y=1; else if(rs) y=0; else y=y; end endmoduleArticle: 121690
Wow, thanks for the quick replies. Yes that is the problem, I only created a symbol for the top module, mem_interface_top_main_O, so the synthesis suceeed, but errors are declared by NgdBuild since he can't find specific internal nets.Article: 121691
Austin, From their web page, it looks as though they are in the market for a corporate partner (someone to pay the bandwidth bills) not for a total buyout. I think many people/companies would love to have opencores but the problem is how to monatize it. Bandwidth isn't free you know. ---Matthew Hicks > Nico, > > I don't make things up. I just read about it in eetimes. > > opencores is up for sale, and there is no one who cares to "take it." > > What does that say? > > Austin >Article: 121692
I am starting with the easiest way to test according to ug086.pdf, I chose the DDR SDRAM design with DCM and testbench. So I'll check the ERROR and init_done signals via a LED. Do I need to interconnect 3 symbols, interface, testbench and controller? Or are there more? I thought that making a symbol out of the top VHDL module was sufficient. Thanks.Article: 121693
Since you have no signal or module named "done" and I wouldn't expect the tools to rename your int_done wire, are you sure this code generated the "error warning" (please specify if it's an error or a warning) that done.RSTF was minimized to ground? Also, the word is "anticipation" just for your information, no offense. <miche> wrote in message news:46951a71$1_4@mk-nntp-2.news.uk.tiscali.com... > Hello, > Here is my program, if you want to compile it and see > for yourself, it would be wonderful. > Waiting with antissipation, > Thanks. > > > module vv(clk1, clk2, reset1,reset2, addr1); > input clk1; > input clk2; > input reset1; > input reset2; > output [4:0] addr1; > wire [4:0] addr1; > wire int_mux_clk; > wire int_done; > mmux mymux(.a(clk1),.b(clk2),.sel(int_done),.y(int_mux_clk)); > mcounter mycounter(.clk(int_mux_clk),.rs(reset1),.ad(addr1)); > mdetect mydetect(.a(addr1[4]),.rs(reset2),.y(int_done)); > endmodule > > > module mmux(a,b,sel,y); > input a, b, sel; > output y; > reg y; > always @ (a or b) > begin > if (sel==0) y=a; > else y=b; > end > endmodule > > > module mcounter (clk,rs,ad); > input clk,rs; > output [4:0] ad; > reg [4:0] ad; > always @ (posedge clk or posedge rs) > begin > if(rs) > ad=0; > else > ad=ad+1; > end > endmodule > > module mdetect(a,rs,y); > input a; > input rs; > output y; > reg y; > always @(a or rs) > begin > if (a) y=1; > else if(rs) y=0; > else y=y; > end > endmodule > > >Article: 121694
On Jul 5, 11:50 am, austin <aus...@xilinx.com> wrote: > PretzelX, > > Xilinx recognizes the investment made when choosing a > processor/architecture/language; and has made every effort to follow the > "golden rule": Never obsolete your processor. > > And, so far, we have never given any customer cause to worry. > > There are no plans to (ever) change this policy. > > Our track record also speaks to keeping this commitment. > > The same can not be said for our competitors. > > Austin Let's see, just where has Xilinx violated your rule? Complete abandonment of XC4000 sortware support when Xilinx switched to XST? I certainly got stuck with a few hundred new XC4K parts and a Xilinx ISE 4.1 synthesis license that expired and you would not issue. You claim is outright hot air, an unfailrly damming your competitor with false assertions.Article: 121695
There is a simple answer: Click on http://www.xilinx.com/ise/logic_design_prod/classics.htm and get all the old software for FREE. Sorry to rain on your parade, but you asked for it. Peter Alfke On Jul 11, 1:08 pm, Totally_Lost <air_b...@yahoo.com> wrote: > On Jul 5, 11:50 am, austin <aus...@xilinx.com> wrote: > > > PretzelX, > > > Xilinx recognizes the investment made when choosing a > > processor/architecture/language; and has made every effort to follow the > > "golden rule": Never obsolete your processor. > > > And, so far, we have never given any customer cause to worry. > > > There are no plans to (ever) change this policy. > > > Our track record also speaks to keeping this commitment. > > > The same can not be said for our competitors. > > > Austin > > Let's see, just where has Xilinx violated your rule? Complete > abandonment of XC4000 sortware support when Xilinx switched to XST? > > I certainly got stuck with a few hundred new XC4K parts and a Xilinx > ISE 4.1 synthesis license that expired and you would not issue. > > You claim is outright hot air, an unfailrly damming your competitor > with false assertions.Article: 121696
On 11 Jul, 21:50, Peter Alfke <p...@xilinx.com> wrote: > There is a simple answer: > Click onhttp://www.xilinx.com/ise/logic_design_prod/classics.htm > and get all the old software for FREE. > Sorry to rain on your parade, but you asked for it. Is there also a simple answer as to get parts you announced two years ago but which still haven't materialised? ;-) Are you ever going to make the XC4VFX40? JonArticle: 121697
Uncle Noah wrote: > On Jul 11, 4:56 pm, "Xilinx User" <anonym...@net.com> wrote: > >>Thanks everyone, for the replies. My question was vague and poorly >>worded because I don't have a good grasp on what constitutes a >>"FPGA CPU-core"and an "ASIC CPU-core." Microblaze and Nios-II >>obviously are architected around the unique device-features of their >>respective vendors. But when it comes to the Opensource offerrings, >>I didn't see the same trend (maybe I didn't look close enough?) >> >>Picoblaze -- is that safe for ASIC-use? I was under the impression >>Xilinx's license-agreement limits it to Xilinx devices only. > > > I'm not sure about the Picoblaze licensing. > Actually, there are at least 2 distinct version of Picoblaze available > from Xilinx site. There is a Virtex-2/Spartan-3 optimized version > (KCPSM3) that involves Xilinx-specific components (buffers, registers > etc), and another version with some differences in the architecture > (slightly older instruction set, 8 registers instead of 16) originally > devised for CPLDs. > However this description is completely portable across different FPGA > vendors. For example i have ported this one to XC3S200 with good > results (around 170 slices, maybe less i don't recall the exact > results). > > It would be meaningful for Xilinx to license this more obsolete > version in GPL or LGPL sense. Anyone aware of the exact licensing > issues with the two different PicoBlaze versions, please jump in. Since there seems to be some confusion on the PicoBlaze license, the btter choices might be PacoBlaze, or the quite similar LatticeMico8 ? -jgArticle: 121698
Berk Birand wrote: > Hi, > > For our VHDL design, we are using an evaluation board that has a Xilinx > Virtex-II Pro chip on it. The design calls for sampling of a digital > signal at 100MHZ. The problem is that the signal contains very short > pulses, given at random intervals. Can you be more exact on what 'very short pulses' actually means ? If "very short' means 2ns, then you have bigger problems than Tsu. Th :) You can design pulse capture latches, that will signal the presence of a shorter pulse than your sample rate, but you just know 'it happened in this window', not how narrow it actually was. The actual FF-Sample-aperture in a modern FF, is well under 1ns, but the actual alignment of that varies with process, routing etc -jgArticle: 121699
On Jul 11, 2:50 pm, Peter Alfke <p...@xilinx.com> wrote: > There is a simple answer: > Click onhttp://www.xilinx.com/ise/logic_design_prod/classics.htm > and get all the old software for FREE. > Sorry to rain on your parade, but you asked for it. > Peter Alfke Peter, show me where the VHDL and Verilog are in that release, exactly the items that were in what Xilinx sold in ISE 4.x and refused to provide me keys for.
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