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On Jul 7, 9:36 am, rajiv <kahn...@gmail.com> wrote: > int *mem; .... > mem= (int*)0x10000032; .... > The address of the bram controller is from 10000000 to 10001fff but > this c code is not calling the verilog code written for the controller > so please suggest possible changes to achieve it. You could try declaring "mem" as volatile; volatile int *mem; mem= (volatile int*)0x10000032; Cheers, AndyArticle: 121551
Hi, all. Can anyone tell me what "Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC..." means, and what platgen actually does to the .tcl files? I'm wondering if this could be the cause of an issue I'm having with BRAM instances. Before, I could run a Base System with 1 or more MicroBlazes with any available size Local Memory each, and no other extra peripherals or software (merely for testing purposes), and it would build the bitstream just fine. Now, XPS generates this error with the same Base System straight from the Wizard (ML310 board v2p30ff896-6, MicroBlaze, 100MHz, no debug, any size Local Memory, no cache, no FPU, no extra peripherals, no extra software beyond the bootloop): "Mapping design into LUTs... ERROR:MapLib:482 - Blockram ramb16_s9_s9_0 is a memory mapped blockram generated for the Microprocessor. However it is not connected properly, causing it to be trimmed. Please connect up all memory mapped blockram properly and re-run Ngdbuild. etc." I'm baffled, as all the system files are the same (MHS, MSS, UCF, XMP, BMM, etc.) between when my previous working XPS would build a bitstream and my current broken version of XPS. Thanks to anyone willing to help me out. ----JD----Article: 121552
Jeremie wrote: > Hi everyone, > > Could someone with experience or simulation tools provide information on the > hardware requirements to interconnect Virtex2pro and Virtex4 with rocketio > at 2.5Gb/s. > The simpler the better, DC if possible and if not AC. I'd like to know the > termination voltages and anything needed on the lines. > v2pro<=>v2pro and V4<=>V4 works. No reason it shouldn't work. Just make sure the voltage swing and impedance is compatible (via measurement - your actual levels can vary quite a lot from the datasheet numbers depending on your layout). I suggest series caps for an AC coupling. It'll eliminate the need to make DC offset compatible. You can pick a physical layer standard to model - e.g. Infiniband or Fibre Channel - to make it easier to derive parameters. For example the V4 wizard has an entry for Fibre Channel, so if you pick that and test to those levels (with a 50-ohm impedance) you'll be in good shape. Be sure to test each separately to a dummy load (e.g. 50-ohm resistors to ground); that will let you look at each transmitter waveform so you can verify they look good (if your layout person is ambitious you can lay out the resistors perpendicular to the series caps and share a pad; then you can populate the resistors, do your initial tests, remove the resistors and populate the caps for real operation - save a layout spin). Note: if you haven't worked with the V4 transceivers before, you're in for a fun ride... kenArticle: 121553
Hi,
I've been working on a simulink model built using the Xilinx Blockset to
try to verify the function of an interplation filter made from the MacFir
Core. The full working VHDL version of the complete data path where the
input data goes into a fifo and is read out to the filter as it is ready for
data. The filter does a simple up by 2 interpolation and the output data is
written to another fifo for eventual output. This filter actually handles 64
channels. The input rate for the data is 100KHz and the Output rate is to be
200KHz.
In my simulink model I read the data for a input signal consisting of 2
sine waves, one well within the filters passband and one in the stop band,
from the MATLAB workspace. I then multiplex that same data to 28 channels
and feed the filter which is intantiated in the Simulink model as a black
box as per Matlab's help file for inserting a Xilinx core into a model.
I've had a lot of confusion about sample rates and how to deal with them
in Simulink, but I think I'm finally getting the hang of them. The output
rate is 2x the input rate for the complete system - fifo in to fifo out but
the filter runs very fast compared to the actual data rate in and out.
The Modelsim simulation of the whole VHDL coded system seems to be
working- I get 2 samples out for every one in on all the channels and the
data is written to the output fifos ok. Since the data is fixed point I
wanted to verify my output values with what I get in the Simulink model
which uses the fixed point blockset etc. The biggest issue I have is that
the Modelsim simulation goes very fast and outputs data from the filter
every usec or less while the Simulink model using the Modelsim output block
takes milliseconds to produce an output data. It does give me 2 values for
every one in and the filter model appears to be working ok, but the clocking
of the whole model is running at a sample rate of 100KHz. . I use modelsim
under the control of Simulink to run the simulation and the fastest clock in
the simulation is 200KHz. The system clock in the "real" VHDL system is
80MHz. When I try to increase the system clock in the SystemGenerator block
to anything faster than 1MHz I get some error about an unresolved Boolean
value and the simulation doesn't run.
Has anyone matched what an actual synthesizable system to a Simulink
model at the actual clock rates used in the VHDL simulation? When I look at
all the example files for simulink it seems they always use sample rates of
1sec which seems ridiculous when trying to match clock rates in an FPGA
system. Am I really off the mark here or to I just have to run my Simulink
model for 45 minutes to match what the VHDL model gives me in 2 seconds?
Totally dazed and confused,
CTW
Article: 121554On Jul 6, 3:45 pm, "MM" <m...@yahoo.com> wrote: > You might want to try using FIR compiler core instead of the MAC FIR. I > believe it has less bugs, although I am not sure. > > Keep us informed about what you find! > > /Mikhail I think you are right. However, the FIR compiler does not allow you to use 18-bit coefficients along with 18-bit data.Article: 121555
I use Xilinx PCSPMA GTP IP core to connect ML555 SFP interface. But how to connect the signal_detect signal of PCSPMA GTP core to indicate presence of optical input?Article: 121556
On 7 8 , 12 49 , "water9...@yahoo.com" <water9...@yahoo.com> wrote:
> I use Xilinx PCSPMA GTP IP core to connect ML555 SFP interface. But
> how to connect the signal_detect signal of PCSPMA GTP core to indicate
> presence of optical input?
SFP{1/2}_LOS is connected LED of ML555,no FPGA Pin.
how to connect the signal_detect signal of PCSPMA GTP core ?
Article: 121557
Hi all,
This is the verilog code which i have written to read and write
from bram block but when i am reading from it i get only zero and
nothing else.So can anyone please suggest changes.I have given c code
also for your refrence.
module user_logic
(
// -- ADD USER PORTS BELOW THIS LINE ---------------
// --USER ports added here
IP2Bus_Clk, // IP to Bus clock
Bus2IP_Clk, // Bus to IP clock
Bus2IP_Reset, // Bus to IP reset
IP2Bus_IntrEvent, // IP to Bus interrupt event
Bus2IP_Addr, // Bus to IP address bus
Bus2IP_Data, // Bus to IP data bus for user logic
Bus2IP_BE, // Bus to IP byte enables for user
logic
Bus2IP_Burst, // Bus to IP burst-mode qualifier
Bus2IP_RNW, // Bus to IP read/not write
Bus2IP_RdCE, // Bus to IP read chip enable for
user logic
Bus2IP_WrCE, // Bus to IP write chip enable for
user logic
Bus2IP_RdReq, // Bus to IP read request
Bus2IP_WrReq, // Bus to IP write request
IP2Bus_Data, // IP to Bus data bus for user logic
IP2Bus_Retry, // IP to Bus retry response
IP2Bus_Error, // IP to Bus error response
IP2Bus_ToutSup, // IP to Bus timeout suppress
IP2Bus_RdAck, // IP to Bus read transfer
acknowledgement
IP2Bus_WrAck, // IP to Bus write transfer
acknowledgement
Bus2IP_MstError, // Bus to IP master error
Bus2IP_MstLastAck, // Bus to IP master last acknowledge
Bus2IP_MstRdAck, // Bus to IP master read acknowledge
Bus2IP_MstWrAck, // Bus to IP master write
acknowledge
Bus2IP_MstRetry, // Bus to IP master retry
Bus2IP_MstTimeOut, // Bus to IP mster timeout
IP2Bus_Addr, // IP to Bus address for the master
transaction
IP2Bus_MstBE, // IP to Bus byte-enables qualifiers
IP2Bus_MstBurst, // IP to Bus burst qualifier
IP2Bus_MstBusLock, // IP to Bus bus-lock qualifier
IP2Bus_MstRdReq, // IP to Bus master read request
IP2Bus_MstWrReq, // IP to Bus master write request
IP2IP_Addr // IP to IP local device address for
the master transaction
); // user_logic
// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_AWIDTH = 32;
parameter C_DWIDTH = 32;
parameter C_NUM_CE = 6;
parameter C_IP_INTR_NUM = 1;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
// -- ADD USER PORTS BELOW THIS LINE -----------------
// --USER ports added here
// -- ADD USER PORTS ABOVE THIS LINE -----------------
output IP2Bus_Clk;
input Bus2IP_Clk;
input Bus2IP_Reset;
output [0 : C_IP_INTR_NUM-1] IP2Bus_IntrEvent;
input [0 : C_AWIDTH-1] Bus2IP_Addr;
input [0 : C_DWIDTH-1] Bus2IP_Data;
input [0 : C_DWIDTH/8-1] Bus2IP_BE;
input Bus2IP_Burst;
input Bus2IP_RNW;
input [0 : C_NUM_CE-1] Bus2IP_RdCE;
input [0 : C_NUM_CE-1] Bus2IP_WrCE;
input Bus2IP_RdReq;
input Bus2IP_WrReq;
output [0 : C_DWIDTH-1] IP2Bus_Data;
output IP2Bus_Retry;
output IP2Bus_Error;
output IP2Bus_ToutSup;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
input Bus2IP_MstError;
input Bus2IP_MstLastAck;
input Bus2IP_MstRdAck;
input Bus2IP_MstWrAck;
input Bus2IP_MstRetry;
input Bus2IP_MstTimeOut;
output [0 : C_AWIDTH-1] IP2Bus_Addr;
output [0 : C_DWIDTH/8-1] IP2Bus_MstBE;
output IP2Bus_MstBurst;
output IP2Bus_MstBusLock;
output IP2Bus_MstRdReq;
output IP2Bus_MstWrReq;
output [0 : C_AWIDTH-1] IP2IP_Addr;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------
// --USER nets declarations added here, as needed for user logic
// Nets for user logic slave model s/w accessible register example
reg [0 : C_DWIDTH-1] slv_reg0;
reg [0 : C_DWIDTH-1] slv_reg1;
reg state,nextstate;
wire [0 : 1] slv_reg_write_select;
wire [0 : 1] slv_reg_read_select;
reg [0 : C_DWIDTH-1] slv_ip2bus_data;
wire slv_read_ack;
wire slv_write_ack;
integer byte_index, bit_index;
wire [0:31] DOA_BRAM;
wire [0:3] DOPA_BRAM;
reg [0:14] ADDRA_BRAM;
reg [0:31] DIA_BRAM;
reg [0:3] DIPA_BRAM;
reg [0:3] WEA_BRAM;
wire [0:31] DOB_BRAM;
wire [0:3] DOPB_BRAM;
reg [0:14] ADDRB_BRAM;
reg [0:31] DIB_BRAM;
reg [0:3] DIPB_BRAM;
reg [0:3] WEB_BRAM;
`define ENA_BRAM=1'b1;
`define ENB_BRAM=1'b0;
initial state=1'b0;
// --USER logic implementation added here
// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible
registers
//
// Note:
// The example code presented here is to show you one way of reading/
writing
// software accessible registers implemented in the user logic slave
model.
// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
correspond
// to one software accessible register by the top level template.
For example,
// if you have four 32 bit software accessible registers in the user
logic, you
// are basically operating on the following memory mapped registers:
//
// Bus2IP_WrCE or Memory Mapped
// Bus2IP_RdCE Register
// "1000" C_BASEADDR + 0x0
// "0100" C_BASEADDR + 0x4
// "0010" C_BASEADDR + 0x8
// "0001" C_BASEADDR + 0xC
//
// ------------------------------------------------------
assign
slv_reg_write_select = Bus2IP_WrCE[0:1],
slv_reg_read_select = Bus2IP_RdCE[0:1],
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1];
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin
state=nextstate;
end
always @(posedge Bus2IP_Clk)
begin: SLAVE_REG_WRITE_PROC
if ( Bus2IP_Reset == 1 )
begin
slv_reg0 <= 0;
end
else
begin
case (state )
1'b0 : // for getting address
begin
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index =
byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7;
bit_index = bit_index+1 )
slv_reg0[bit_index] <= Bus2IP_Addr[bit_index];
if(slv_reg0 <= 32'h10001fff && slv_reg0 >= 32'h10000000)
ADDRA_BRAM = slv_reg0 & 32'h300007ff;
if( slv_reg_write_select==1'b1)
nextstate=1'b1; // in case of write
else
WEA_BRAM =4'b0000; // in case of read
end
1'b1 : // for getting data
begin
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index =
byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7;
bit_index = bit_index+1 )
slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
DIA_BRAM = slv_reg1;
WEA_BRAM = 4'b1111;
nextstate= 1'b0;
end
default : ;
endcase
end
end
// SLAVE_REG_READ_PROC
// ------------------------------------------------------------
// Example code to drive IP to Bus signals
// ------------------------------------------------------------
RAMB16_S36_S36 BRAM (.DOA (DOA_BRAM),
.DOB (DOB_BRAM),
.DOPA (DOPA_BRAM),
.DOPB (DOPB_BRAM),
.ADDRA (ADDRA_BRAM),
.ADDRB (ADDRB_BRAM),
.CLKA (Bus2IP_Clk),
.CLKB (Bus2IP_Clk),
.DIA (DIA_BRAM),
.DIB (DIB_BRAM),
.DIPA (DIPA_BRAM),
.DIPB (DIPB_BRAM),
.ENA (ENA_BRAM),
.ENB (ENB_BRAM),
.SSRA (1'b0),
.SSRB (1'b0),
.WEA (WEA_BRAM),
.WEB (WEB_BRAM));
defparam BRAM.INIT_00 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_01 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_02 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_03 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_04 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_05 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_06 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_07 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_08 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_09 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_0A =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_0B =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_0C =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_0D =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_0E =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_0F =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_10 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_11 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_12 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_13 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_14 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_15 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_16 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_17 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_18 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_19 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_1A =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_1B =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_1C =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_1D =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_1E =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_1F =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_20 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_21 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_22 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_23 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_24 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_25 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_26 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_27 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_28 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_29 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_2A =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_2B =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_2C =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_2D =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_2E =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_2F =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_30 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_31 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_32 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_33 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_34 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_35 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_36 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_37 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_38 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_39 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_3A =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_3B =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_3C =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_3D =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_3E =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INIT_3F =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INITP_00 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INITP_01 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INITP_02 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INITP_03 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INITP_04 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INITP_05 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INITP_06 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.INITP_07 =
256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam BRAM.WRITE_MODE_A = "WRITE_FIRST";
assign IP2Bus_Data = DOA_BRAM;
assign IP2Bus_Retry = 0;
assign IP2Bus_ToutSup = 0;
endmodule
here is the c code:
#include "stdio.h"
#include "xparameters.h"
#include "xuartlite_l.h"
#include "mb_interface.h"
int main(void)
{
int i,j,k;
volatile int*mem;
int fill_value = 0x10000001;
//basic uart test
print ("hello world\r\n");
for (k=0;k<1;k++){
//fill in values at consecutive addresses
mem= (volatile int*)0x10000032;
for (i=0;i<50;i++)
{
*mem = i;
xil_printf("%x\t%d\n\r",mem,*mem);
mem++;
}
//read back these values
mem = ( int*)0x10000032;
for (i=0;i<55;i++)
{
print("ADDRESS=");
xil_printf("%x",mem);
print("\tfill_value=");
xil_printf("%d",i);
print("\tread=");
xil_printf("%d",*mem);
print("\r\n");
mem++;
}
print("\n\r done OK!");
}
print("\n\rdone!");
for (;;);
}
Article: 121558Again, if you must use the OPB why not use the Xilinx provided opb_bram_if_cntlr? It should save you the hassle of debugging your Verilog. There is no reason to re-invent the wheel. I still recommend using the lmb_bram_if_cntrl if it's an option.Article: 121559
I use ise9.1 and synplify8.4.2,I use the core generator to generate a fifo,the parameters as follow,different clock and different data bus widths,write 16 bits and read 128 bits,now I want to use the fifo data counts to control my logic,the fifo depths is 256 for read,and I don't use the all fifo,if the fifo data conter reach 200,the logic must stop writing,the logic can't write one more or less,so i need the accurate fifo data conter,but from the datasheet I know that near empty and full the fifo counter will be not accurate but I dno't know if the fifo counts is accurate near 200(write and read will be not at the same time near 200),also under reset or power on,the fifo counts is 2(but now there are no datas in fifo,I don't know why?)Article: 121560
<bjzhangwn@gmail.com> wrote in message news:1183906196.799048.35950@z28g2000prd.googlegroups.com... >I use ise9.1 and synplify8.4.2,I use the core generator to generate a > fifo,the parameters as follow,different clock and different data bus > widths,write 16 bits and read 128 bits,now I want to use the fifo data > counts to control my logic,the fifo depths is 256 for read,and I don't > use the all fifo,if the fifo data conter reach 200,the logic must stop > writing,the logic can't write one more or less,so i need the accurate > fifo data conter,but from the datasheet I know that near empty and > full the fifo counter will be not accurate but I dno't know if the > fifo counts is accurate near 200(write and read will be not at the > same time near 200),also under reset or power on,the fifo counts is > 2(but now there are no datas in fifo,I don't know why?) > Dear Unsigned Poster, I think you may have set a new CAF record. One hundred and fifty two words without a single full stop. Remarkable, especially considering your use of apostrophes, plurals and capital letters is pretty good. ;-) Anyway, that's all well and good, but your post is, unfortunately, as good as incomprehensible. I'd guess your first language isn't English, however I'd respectfully suggest you try and reformat it, and I expect you'll get a lot more responses. I noticed, a few days ago, a post which was perfectly crafted to elict maximum response. You might like to check it out, the subject line was "Hobbyist trying to decide which device to start with...". The guy firstly gave a brief background to his position. Then he explained his problem. Next, he posed some questions. Finally, he pointed out that he had found some solutions for himself, but wanted further suggestions. He did this in four easy-to-read paragraphs, which showed respect and consideration for the reader. He realised that any response he gets on this newsgroup is free, and requires the responder to take the effort to understand his post. He made the post easy to comprehend. Anyway, I hope this reply doesn't sound too patronising, I really do want to help you get your questions answered. So, good luck and HTH, Syms. p.s. For further study:- http://www.catb.org/~esr/faqs/smart-questions.html#translationsArticle: 121561
On 6 Jul., 07:31, hobin0...@gmail.com wrote: > hi all experts > could you recommend good USB analyzer for me > i am an new USB driver developer and my boss wanted me to investigate > which one is the best choice > 1.support 1.1/ 2.0 / OTG specification > 2.can analyze RNDIS/MassStorage/Serial pactet > 3.record potential and current > 4.FPGA > 5.have source code to provide correctness diy there is nothing to your spec anttiArticle: 121562
On 29 juin, 12:16, "RedskullDC" <r...@oz.org> wrote: > Hi Christophe, > > Been using ISE9.1 with Vista Ultimate x64 for the last few months. > Compiles my projects without any problem. > > Only problem I've had is the non-signed parallel/usb drivers from Xilinx > won't install > with the final release versions of Vista X64, since you can no longer > disable > the driver-signing checks as you could with the pre-release versions of > Vista(AFAIK). > > Programming files are saved to a network shared directory, and another > machine > running XPhome is used to actually program the hardware. > Cumbersome, but the machine running vista is considerably higher spec, and > compiles > projects in a third of the time as the old XP box. > > Come on Xilinx. **PLEASE** release some signed hardware drivers!! > Ditto Altera....... > > Red > > "christophe ALEXANDRE" <christophe.alexan...@gmail.com> wrote in message > > news:1183055040.264539.195390@w5g2000hsg.googlegroups.com... > > > > > hi Xilinx, > > > i had a look at ISE 9.2 today. > > It's supporting Vista 32 bits. > > > When should we have a Vista 64 bits support ? > > > regards- Masquer le texte des messages pr=E9c=E9dents - > > - Afficher le texte des messages pr=E9c=E9dents - Thanks for your answer, i take note that 32 bits ISE runs under vista 64 bits. But my original question was of course a 64 bits ISE version running on Vista 64 bits. The goal is to break the 3 GB memory limit.Article: 121563
bjzhangwn@gmail.com wrote: > I use ise9.1 and synplify8.4.2,I use the core generator to generate a > fifo,the parameters as follow,different clock and different data bus > widths,write 16 bits and read 128 bits,now I want to use the fifo data > counts to control my logic,the fifo depths is 256 for read,and I don't > use the all fifo,if the fifo data conter reach 200,the logic must stop > writing,the logic can't write one more or less,so i need the accurate > fifo data conter,but from the datasheet I know that near empty and > full the fifo counter will be not accurate but I dno't know if the > fifo counts is accurate near 200(write and read will be not at the > same time near 200),also under reset or power on,the fifo counts is > 2(but now there are no datas in fifo,I don't know why?) In addition to making your statement/query/issue/rambling readable, please let those who can help know if you're dealing with a synchronous - FIFO where the input and output clocks are the same clock - or an asynchronous FIFO where the input and output clocks are different clocks. If you have the synchronous FIFO case, my suggestion would be: build your own! Synchronous FIFOs are easy to produce and can give you the full access and control you're looking for. If you want more than the core will give you, making your own is often the quickest route.Article: 121564
Greetings, First off, let me share with you that I'm a complete newb when it comes to FPGA/ISE/VHDL. I'm using the "free" version of ISE and my end device is a V2P-7 672 pin FPGA with the pins already locked and unchangable on a custom board. I'm using VHDL. The issue I'm trying to deal with is deserializing an 8 bit serial line from a clock rate of 1MHz upto 40MHz (bit rate of 8MHz to 320MHz) with the ability to switch which incoming clocks to use as the master deserializer clock. The deserializer I'm using is a portion of XAPP265 from XILINX, mainly just the flipflop section (not the block ram or DCM section). The first problem is the wide range of clock rates I need to program for. The 2nd issue deals with the fact that the "SYNC" clock may be unstable depending on the DUT and I will want to switch to a secondary SYNC clock if that's the case. The 2nd problem is how to implement the DCMs using as few of them as possible. The following is a description of the FPGA inputs: These 2 signals come directly from the DUT SYNC - The 1MHz to 40MHz clock from the device under test (DUT) which can sometimes be unstable INPUT - The 8MHz to 320MHz data word which I want to deserialize These 2 signals come from a clock generator which can be used in place of the SYNC if the SYNC clock is too unstable for deserializing PCLK - Optional 1MHz to 40MHz clock from external clock generator to be used instead of SYNC if necessary (on different pins from SYNC). CLK4x - Optional 4x of PCLK clock which is used as a DDR clock to deserialize data from INPUT if SYNC is too unstable Here is my current approach: If the DUT is operating at slow speeds (SYNC < 24MHz), I use the CLK4x input as my DDR clock because the DCM can't generate the 4x clock from the SYNC clock. I may optionally switch out the SYNC clock for the PCLK if the SYNC clock is too unstable. This is currently one build of the FPGA code and it appears to work fine. No DCMs are used in this build. My next approach is to figure out how to combine the slow and high speed options but am not sure the best way to approach this. I want to have a command protocol between my computer and the FPGA to be able to tell the FPGA if the DUT will be operating in SLOW or HIGHSPEED mode and command which clock, SYNC or PCLK to use.. HIGHSPEED mode will first try to use the SYNC clock and generate a 4xSYNC clock to use as the DDR clock, but if that fails due to SYNC instability, use the PCLK in place of the SYNC. I'm thinking I need at least 2 DCMs to do this. One to phase shift the SYNC/PCLK signal since I can't get the PCLK to have 0 phase relation with the SYNC clock externally and another DCM to generate a phase shiftable 4x clock from the SYNC/PCLK clock. I'm thinking of using a mux to switch between PCLK and the SYNC clock to the input of the both DCMs and a mux to switch in either the external CLK4x or the DCM generated CLK4x to operate as the DDR clock. Will this approach work? Is there a better way to do this? How can I tell the DCM which frequency it'll be operating at (the DCM pixel period generic) and is that generic really necessary? Thanks, JasonArticle: 121565
i am wondering how we can process it if both the frequencies were of 100 MHz and fully asynchronus. with all the possibility that one may be 100.1MHz and the other 99.9 MHz. And if i want send in a register from one to another how we can do that.Article: 121566
Hi, Does anyone have experience with Altium LiveDesign (Xilinx Spartan-3 XC3S1000) ? How does it perform with ISE WebPack, are there any odd issues with it? Any comment will be appreciated. I would like to use it for my CPU project. Size of FPGA is more than I need currently but I don't mind getting bigger device :)Article: 121567
On Jul 6, 11:49 pm, vasile <picli...@gmail.com> wrote: > On Jul 2, 2:05 pm, "jjlind...@hotmail.com" <jjlind...@hotmail.com> > wrote: > > > Hello, I'm trying to decide to use an EPC16 or EPCS64 to program the > > Stratix II EP2S601020C3 on my board. Can any comment which method is > > better/faster? Altera's development kits are using the EPCS64 so I > > leaning that direction. > > > Thanks, > > joe > > The better methode looks M25P64 without any compressed code inside and > fastest serial solution. > Using another microcontroller just for configuration (and not other > purposes) > seems to me a weird option even if harware cost less than $2 and > programming/debugging/PCB design another $20. > > Vasile No more weird than using a dedicated CPLD, which is a popular option for configuring an FPGA from parallel NOR flash memory. There is no way to directly configure an Altera FPGA from an M25P64 (unlike some Xilinx FPGAs), so I assume that the proposed solution assumes a microprocessor with a spare SPI port, or having the microprocessor bit bang the flash SPI port. SteveArticle: 121568
Jason Whitwam wrote: > The issue I'm trying to deal with is deserializing an 8 bit serial line from > a clock rate of 1MHz upto 40MHz (bit rate of 8MHz to 320MHz) with the > ability to switch which incoming clocks to use as the master deserializer > clock. The deserializer I'm using is a portion of XAPP265 from XILINX, > mainly just the flipflop section (not the block ram or DCM section). With such a wide range of clock rates, a DCM-based solution does sound a little awkward. If possible, you might want to consider using a single high-frequency clock on the FPGA (say around 400 MHz) to sample both data and incoming clock. A state machine (effectively a PLL) could then watch for edges on the incoming clock to know which samples of the data signal to pay attention to. Probably you'll want two or four phases of the FPGA clock to get enough timing resolution for good sampling of the incoming signals; a DCM would be convenient to generate those phases. An MGT would also make a good sampler/deserializer at some fixed high rate, but since you say your pinout is fixed, it's probably not an option for you. Cheers, Peter MontaArticle: 121569
That's what asynchronous FIFOs do for a living. But note that a consistent difference in input and output frequencies will inevitably cause the FIFO to go either full or empty. But they signal that to you, even with a warning: almost full, or almost empty. Asynchronous circuit design is tricky, but it can be (and is being) done. Peter Alfke, Xilinx (from home) On Jul 8, 11:30 am, vssumesh <vssumesh_a...@yahoo.com> wrote: > i am wondering how we can process it if both the frequencies were of > 100 MHz and fully asynchronus. with all the possibility that one may > be 100.1MHz and the other 99.9 MHz. And if i want send in a register > from one to another how we can do that.Article: 121570
On Sun, 08 Jul 2007 11:30:55 -0700, vssumesh <vssumesh_asic@yahoo.com> wrote: >i am wondering how we can process it if both the frequencies were of >100 MHz and fully asynchronus. with all the possibility that one may >be 100.1MHz and the other 99.9 MHz. And if i want send in a register >from one to another how we can do that. When you are transferring data from one clock domain to another with roughly the same clock rate, it is often best to use a FIFO. I know that's not really an answer to your question, because the design of the FIFO itself must deal with all the problems that you have been considering; but it's well-established stuff, there are plenty of reliable ready-to-use solutions out there, and it meets the majority of requirements very well. Obviously, if you are sending data from a 100.1MHz clock domain to a 99.9MHz clock domain, it's not possible to send one data value per clock - otherwise the amount of data stored in the FIFO will increase without limit. Again, there are various well-known tricks for working around that: - Batch-up the source data, perhaps in pairs, so that the average data rate is one double-word per two clock cycles. You can easily deal with this on the slightly slower side. - Ensure that all data streams have some "padding" so that you can drop a data value occasionally, and have just a little less padding on the slow-clock side. And, of course, many data sources are bursty so that there are significant dead times in which the receiving side can drain the FIFO. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 121571
Jason Whitwam wrote: > Greetings, > > First off, let me share with you that I'm a complete newb when it comes to > FPGA/ISE/VHDL. I'm using the "free" version of ISE and my end device is a > V2P-7 672 pin FPGA with the pins already locked and unchangable on a custom > board. I'm using VHDL. > > The issue I'm trying to deal with is deserializing an 8 bit serial line from > a clock rate of 1MHz upto 40MHz (bit rate of 8MHz to 320MHz) with the > ability to switch which incoming clocks to use as the master deserializer > clock. The deserializer I'm using is a portion of XAPP265 from XILINX, > mainly just the flipflop section (not the block ram or DCM section). > > The first problem is the wide range of clock rates I need to program for. > The 2nd issue deals with the fact that the "SYNC" clock may be unstable > depending on the DUT and I will want to switch to a secondary SYNC clock if > that's the case. The 2nd problem is how to implement the DCMs using as few > of them as possible. <snip> If your sync becomes unstable, what do you expect for the behavior of your circuit to be before and into the switchover to a stable clock? Is the determination of sync stability an issue only when communication is first established? If the sync is occasionally unstable and you must design for the unstable case, is there a reason to include the sync in the circuit design? Only question at this point so that answers may come more readily.Article: 121572
"Peter Monta" <pmonta@pmonta.com> wrote in message news:zPaki.4087$rL1.3394@newssvr19.news.prodigy.net... > Jason Whitwam wrote: > > >> The issue I'm trying to deal with is deserializing an 8 bit serial line >> from a clock rate of 1MHz upto 40MHz (bit rate of 8MHz to 320MHz) with >> the ability to switch which incoming clocks to use as the master >> deserializer clock. The deserializer I'm using is a portion of XAPP265 >> from XILINX, mainly just the flipflop section (not the block ram or DCM >> section). > > With such a wide range of clock rates, a DCM-based solution does > sound a little awkward. If possible, you might want to consider > using a single high-frequency clock on the FPGA (say around > 400 MHz) to sample both data and incoming clock. A state machine > (effectively a PLL) could then watch for edges on the incoming > clock to know which samples of the data signal to pay attention > to. Probably you'll want two or four phases of the FPGA clock > to get enough timing resolution for good sampling of the incoming > signals; a DCM would be convenient to generate those phases. > > An MGT would also make a good sampler/deserializer at some > fixed high rate, but since you say your pinout is fixed, it's > probably not an option for you. > > Cheers, > Peter Monta Hi Peter, Thanks for the advice. One question I have about this approach is how do I determine which sampled data is bit1, bit2, etc? Thanks, JasonArticle: 121573
"John_H" <newsgroup@johnhandwork.com> wrote in message news:dZbki.674$mS3.660@trnddc03... > Jason Whitwam wrote: >> Greetings, >> >> First off, let me share with you that I'm a complete newb when it comes >> to FPGA/ISE/VHDL. I'm using the "free" version of ISE and my end device >> is a V2P-7 672 pin FPGA with the pins already locked and unchangable on a >> custom board. I'm using VHDL. >> >> The issue I'm trying to deal with is deserializing an 8 bit serial line >> from a clock rate of 1MHz upto 40MHz (bit rate of 8MHz to 320MHz) with >> the ability to switch which incoming clocks to use as the master >> deserializer clock. The deserializer I'm using is a portion of XAPP265 >> from XILINX, mainly just the flipflop section (not the block ram or DCM >> section). >> >> The first problem is the wide range of clock rates I need to program for. >> The 2nd issue deals with the fact that the "SYNC" clock may be unstable >> depending on the DUT and I will want to switch to a secondary SYNC clock >> if that's the case. The 2nd problem is how to implement the DCMs using >> as few of them as possible. > <snip> > > If your sync becomes unstable, what do you expect for the behavior of your > circuit to be before and into the switchover to a stable clock? > > Is the determination of sync stability an issue only when communication is > first established? > > If the sync is occasionally unstable and you must design for the unstable > case, is there a reason to include the sync in the circuit design? > > Only question at this point so that answers may come more readily. Hi John, If a DUTs SYNC clock is unstable then the tester will send a command to the FPGA to switch to the stable clock and this clock will be used always for this particular DUT. I'm not planning any logic to automatically switch between the two. The test engineer will determine if the SYNC clock is unstable, not the FPGA. The reason why I want to try to use the SYNC clock rather than always use the "always" stable clock is: - I want to find DUTs which are working fine, meaning a stable SYNC clock because that's the clock which will be used in the final system. - If the SYNC clock is unstable, I still wish to be able to test the DUTs other functions to find any other issues and to gather reliability data to help improve the design of future ASICs. I hope that helps. Thanks, JasonArticle: 121574
Jason Whitwam wrote: > One question I have about this approach is how do I > determine which sampled data is bit1, bit2, etc? Bit order and link protocol are design decisions. The data packets must be delineated somehow. HDLC requires bit stuffing to eliminate flag patterns in the data. Start-bit / stop-bit is simpler, but requires a fixed packet width. See the reference design here http://home.comcast.net/~mike_treseler/ for a start-bit protocol example. -- Mike Treseler
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