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John_H, Using the DCM output (CLK0, CLK2X, or CLKFX) is certainly not recommended for use with the MGT, as it is not the best clock source. That said, it will work, and on short links with little losses, it will work error free. The PLL in the MGT actually attenuates much of the jitter produced by the DCM (much of the jitter is at very high frequencies in the jitter power vs. jitter frequency spectrum and is effectively removed by the MGT PLL). Again, not the best clock source, but perfectly usable. If you are attempting to meet a particular serial standard, then you should follow the respective characterization report implementation. If you deviate from the recommendation, you may still meet or exceed all the requirements, but we will be unable to say anything about the implementation. AustinArticle: 121451
Markus Fras wrote: > Hello everybody, > > do You know how to change the program of an existing PicoBlaze > implementation on a Xilinx Spartan 3E development board? The board uses > an USB cable to download the bitstream to the FPGA. > > I have an existing design including a PicoBlaze processor and would like > to change its ROM code without recompiling the complete project. The > JTAG loader software only seems to work with the parallel port cable, at > least it tells me so. > > Thanks for Your advice, > > Markus Fras Read your Spartan-3E Development Board User Manual. It explicitly covers reconfiguring the PicoBlaze code *without* performing another place & route, though that's an option as well. The tools are available from the Spartan-3E development board web page (or perhaps with the PicoBlaze suite) to give you the reprogramming capability for a live board. All the info you need is there.Article: 121452
Hi all, I've just read something about LVDS via emulation, in the datasheet of the FPGA its specified that some banks natively support LVDS while some other banks are specified to support LVDS in emulation only, does this mean that to support LVDS an external resistor is needed? Thanks, NetoArticle: 121453
Netoko Young isinulat: > Hi all, > I've just read something about LVDS via emulation, in the datasheet > of the FPGA its specified that some banks natively support LVDS while > some other banks are specified to support LVDS in emulation only, does > this mean that to support LVDS an external resistor is needed? > > > Thanks, > Neto Hi, BTW, here's the link to the datasheet: http://www.latticesemi.com/documents/tn1088.pdf?jsessionid=ba30dd372aa4$2137$E1 ps. its on page 13 and for correction its 'Differential output support via emulation'Article: 121454
darrick wrote: > I tried the unbuffered jtag programmer, it is partly working. > It allows me to go into the device with impact and select > various command. For exmaple I can get the device id > or checksum, but when I try to erase or program I > receive fail. Any ideas? If there are short relections on SCK caused by the cable, the JTAG engine will go astray. Schmitt trigger Buffer suppress those reflections very good, less hysteresis in the buffers will make the suppresion worse. But the external buffers also are kind of slow versus the spped of some JTAG input buffers > Second point, why is the buffered device use tri state buffers > and not just normal buffers without tristate. It's a way so detect presense of the Adapter and the device. > Third point, is impact able to know when the programmer > is buffered or not since it seems the buffered one requires > more inputs from lpt? Don't kno, but also don't think so. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 121455
Hello, I am trying to use the ICAP module of a Virtex-4 FX20. I built a project with EDK8.1 using the OPB-ICAP module from EDK 9.1.2. My configuration is a basic microblaze system with the usual debug/timer/lmb-bram/uart-modules clocked at 50 MHz. When executing the example applications from Xilinx on the system, the ICAP seems to work only after at least one system reset. Writing to the BRAM buffer of the ICAP-module works but if I try to execute a Read Device ID command, no device id gets written to the BRAM buffer therefore the high level Xilinx supplied ICAP functions like XHwIcap_Initialize() will also fail. The hardware and software part of the system builds without warning. How do I correctly initialize the ICAP without applying an other reset after configuration? Best regards, AndreasArticle: 121456
Has anyone been able to get the Actel Linux tools to run? I wasn't able to install them on CentOS5 so booted into Scientific Linux 4.4 (a RHEL 4.4 clone). Installation went fine in 4.4 but I haven't been able to run the tools. I'm getting, /usr/local/tools/Actel/LiberoLU80_Lin/Libero/bin/windu_scm: relocation error: /usr/local/tools/Actel/LiberoLU80_Lin/Libero/lib/libwinsock50.so: symbol h_errno, version GLIBC_2.0 not defined in file libc.so.6 with link time referenceArticle: 121457
> Hi all,
> i am designing a system in which we have a bram block,microblaze
> processor and other essential component.
> i have written a verilog code for bram controller (successfully
> compiled)to interface bram block to opb bus.now i have to write a c
> code to perform read write operation in bram block.i have written
> following code
>
> #include <stdio.h>
> #include <mb_interface.h>
> #include <xutil.h>
> int main(){
> printf("Hello this is the start, printing using print\n");
> volatile char *pointer = ( volatile char *) 0x10013405;
You shouldn't need a cast here and both volatile keywords add nothing additional
in this context and could hide errors.
You should also look into xil_printf()'s.
> *pointer = 'c';
> char temp = *pointer;
> printf("%c %c\n",temp , *pointer);
> return 0 ;
> }
> which is not working
But, you never said what the output of the printf() actually was.
> so regarding this i have following question
> 1-in c ,is it possible to assign address to a pointer according to
> us ????
Yes, it's valid but not because of C, but because you are using a flat non-managed
memory model. Try this kind of shenanigans in Windows and you most likely
will get a SEG Fault.
> 2-is it necessary to use gpio function to read write operation in a
> peripheral ??
You could write your own.
> if you find some conceptual mistake in code then please reply
>
> with regards
> Ajay
Article: 121458
On Jul 4, 12:23 pm, rajiv...@gmail.com wrote:
> Hi all,
> i am designing a system in which we have a bram block,microblaze
> processor and other essential component.
> i have written a verilog code for bram controller (successfully
> compiled)to interface bram block to opb bus.now i have to write a c
> code to perform read write operation in bram block.i have written
> following code
>
> #include <stdio.h>
> #include <mb_interface.h>
> #include <xutil.h>
> int main(){
> printf("Hello this is the start, printing using print\n");
> volatile char *pointer = ( volatile char *) 0x10013405;
> *pointer = 'c';
> char temp = *pointer;
> printf("%c %c\n",temp , *pointer);
> return 0 ;
>
> }
>
> which is not working
> so regarding this i have following question
> 1-in c ,is it possible to assign address to a pointer according to
> us ????
> 2-is it necessary to use gpio function to read write operation in a
> peripheral ??
>
> if you find some conceptual mistake in code then please reply
>
> with regards
> Ajay
Could it be the IP core you wrote? Why write custom BRAM interface
controller when one already comes with EDK (opb_bram_if_cntlr)?
Alternatively, if you have no other masters that need access to the
BRAM other than the Microblaze, you might want to consider interfacing
via the LMB through the lmb_bram_if_cntlr. This approach has better
performance since the single-master nature of the LMB requires no
arbitration.
Article: 121459On Jul 3, 2:03 pm, austin <aus...@xilinx.com> wrote: > INIT is not the signal that holds the JTAG block in reset, it is the > PROG signal, or the power ON reset. > > So, if the core voltage AND the Vccaux AND the IO bank which has the > config pins on it are all powered ON, AND if the PROG_b is not being > intentionally held low, THEN the JTAG state machine should be released, > and should operate. Basically, when INIT goes high, the mode pins are > sampled, and then based on the mode pins, the configuration state > machine goes to whatever mode is specified, and proceeds with configuration. > > If JTAG is specified by the mode pins, then the part waits to be > configured through the JTAG port. > > JTAG device ID can be read out prior to configuring (by any mode). > > Amazing what digging through the schematics reveals. > > Austin I tried tying PROG_B to gnd on my working virtex-2p board, and identify works fine (JTAG reads device id okay). Is there any reason to expect spartan-3e to behave differently from virtex-2p in this respect? I also tried using a bench power supply for vint (in case my on board supply was bad), but this made no difference. My next thought is I fried the chip in some weird way and I will try replacing it. Alan NishiokaArticle: 121460
Alan, Holding PROG_b low should hold the JTAG state machine in reset. I did not check the V2P schematics, so maybe they did something different. AustinArticle: 121461
Andreas, This may not be your problem, but if I read from the ICAP first thing after programming I have had it routinely fail. I've chalked this up to the device coming alive before the final dummy configuration frame contained in the bitstream has finished writing to the device (may not be the true cause). Thus my ICAP read conflicts with the device programming. If I delay the read to the ICAP it behaves perfectly. Stephen On Jul 4, 3:28 pm, Andreas Hofmann <ahn...@gmx.de> wrote: > Hello, > > I am trying to use the ICAP module of a Virtex-4 FX20. I built a > project with EDK8.1 using the OPB-ICAP module from EDK 9.1.2. > > My configuration is a basic microblaze system with the usual > debug/timer/lmb-bram/uart-modules clocked at 50 MHz. When executing the > example applications from Xilinx on the system, the ICAP seems to work > only after at least one system reset. > > Writing to the BRAM buffer of the ICAP-module works but if I try to > execute a Read Device ID command, no device id gets written to the BRAM > buffer therefore the high level Xilinx supplied ICAP functions like > XHwIcap_Initialize() will also fail. > > The hardware and software part of the system builds without warning. > > How do I correctly initialize the ICAP without applying an other reset > after configuration? > > Best regards, > > AndreasArticle: 121462
V4 FPGA has independently RXSIGDET port signal,but V5 not. how to detect the signal on V5 GTP?Article: 121463
Recently, I download a reference design from Xilinx. Then implementate
in EDK9.1.02i, while checking the timing report,I find some fails,such
as:
------------------------------------------------------------------------------------
Constraint|Check| Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors
| Score
------------------------------------------------------------------------------------
* TS_dc | SET | -0.598ns | 6.196ns | 300 | 59028
m_1_dcm | UP |
_1_CLK0 |
_BUF = |
PERIOD | HOLD| 0.410ns | | 0
| 0
TIMEGRP|
"dcm_1_ |
dcm_1_CL|
K0_BUF" |
TS_dcm |
_0_dcm_0 |
_CLK2X_B|
UF HIGH |
50% |
/////////////////////////////////////////////////////////////////////////////////////////////////////
* TS_dcm |SET | -0.197ns | 5.262ns | 6 | 848
_1_dcm_ |UP |
1_CLK90_ |
BUF = P |
ERIOD |HOLD| 0.446ns | | 0
| 0
TIMEGRP |
"dcm_1 |
_dcm_1_ |
CLK90_B |
UF" |
TS_dcm |
_0_dcm_ |
0_CLK2X |
_BUF P |
HASE |
1.25 ns |
HIGH |
50% |
/////////////////////////////////////////////////////////////////////////////////////////////////////
during this report the best case has enough slack,but the worst case
fail the constraints.Has anybody encounter this case,and how to solve
it,any advices are welcome,thanks.
Article: 121464Hi everyone, No doubt this subject has been discussed on numerous occasions: http://www.embeddedrelated.com/groups/fpga-cpu/show/2182.php http://www.edaboard.com/ftopic74807.html http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/d5df4786b2340f21/4502e4fb620f5157?lnk=st&q=microblaze+vs+nios&rnum=2#4502e4fb620f5157 http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/e629302f416e08cd/6916d47ebb3868b1?lnk=st&q=microblaze+vs+nios&rnum=3#6916d47ebb3868b1 However it seems that it has been a while since the subject has been visited, and since it has been a while, I'm wondering if opinions have changed. I went to a Xilinx sponsored seminar and was impressed by the capabilities of the tools, product and the knowledge of the local FAE's. I've since purchased a Spartan 3E Starter Kit to investigate the feasibility of using Soft processors to consolidate 4 or so processor boards in one of our products. (couldn't find an Altera Dev kit - not saying that one doesn't exist, just could find one - with similar features [Ethernet/RS232] in the same price range) However, I would also like to not exclude Altera/NIOS II from consideration based on the fact that I went to a Xilinx seminar and found a cheap & cool Development kit! My main concern isn't the architecture of either core. More important to me are the following factors: 1) Good integration of soft processor with IDE/Tools - intuitive tools 2) Ability to guarantee supply of pin/function compatible parts for long term. 3) Abundance of IP bundled with tools (or open source) [eg. I2C, SPI, UART, Eth MACS, USB MACS, etc] 4) Cheaper IDE/Tools (I understand Quartus & ISE webpacks are free, but neither EDK or Nios II Embedded Design Suite are) 5) Ability to upgrade (Pin/Function compatible) parts with higher/lower density parts. (I know for example Spartan 3's are interchangeable within each family; Could someone please confirm if Altera's FPGAs have this ability) 6) Availability of RTOS/eOS ports to soft processor 7) Abundance of tutorials/how-to's/examples 8) Good community support My take from what I've read so far is that both Xilinx and Altera are good. Some have said that Quartus is a a little slicker and easier to use than ISE - if you've had the opportunity to play with both recently, do you still think that is true? Any insight into the Altera(Nios) vs Xilinx(Microblaze) comparison would be greatly appreciated. Thanks very much for your opinions and insight. PretzelX.Article: 121465
On 3 Jul., 14:07, hofmann.juer...@pc-future.de wrote: > Hi all, > > I'm developing a multicore system with up to four Microblaze cores. > Now I'm searching for a solution to inform the cores about e.g. > messages with a software interrupt. That means, one core writes a > message in the shared memory and after that it informs the other cores > to read the message. > My first idea was to use a GPIO element with interrupts switched on. I > tried to write to the element when the message was posted . But there > is the problem, that the interrupt is only activated when the data > will be changed from outside the microblaze core. > So my new idea is to use two GPIO elements and link them together. But > it doesn't run and I think, that the problem is the linking of the > ports. > Has anybody an idea, which ports I have to link (GPIO_d_out or GPIO_IO > with GPIO_in or something else) or an idea how to implement software > interrupts in such a combination? > > I've got a Xilinx ML410 evaluation board. > > Thank you for your help. I solved my Problem with the two GPIOs. You have to design the interrupt GPIO as an input only element an link the GPIO_in port with the GPIO_d_out port of the other GPIO core. If the global interrupt register and the IP-Interrupt register is set correctly, every transition in the second GPIO data register activate an interrupt. Thanks to Zara and morphiend for their ideas!Article: 121466
On Jul 5, 12:26 am, Alan Nishioka <a...@nishioka.com> wrote: > On Jul 3, 2:03 pm, austin <aus...@xilinx.com> wrote: > > My next thought is I fried the chip in some weird way and I will try > replacing it. > > Alan Nishioka- Hide quoted text - > > - Show quoted text - its another try, sure. I happen to own 3 dead FPGA boards with XC3S100E-TQ144 on them.. they are those "sample pack boards", think there is something badly wrong with power supply on that board so I managed to get all 3 boards to fry.. at least one of them was damaged in a way that FPGA was half dead, eg can configure ok, but not all LUTS work AnttiArticle: 121467
Stephen, thanks for the quick reply. I've tested delaying the first access to the ICAP and now reading the device ID works perfectly. Using the Xilinx microkernel I have to wait about 30 ms after the start of the kernel to successfully talk to the ICAP. I've searched the Virtex-4 configuration guide (ug071) and the Xilinx website but found no information about this topic. Best regards, Andreas stephen.craven@gmail.com schrieb: > Andreas, > > This may not be your problem, but if I read from the ICAP first thing > after programming I have had it routinely fail. I've chalked this up > to the device coming alive before the final dummy configuration frame > contained in the bitstream has finished writing to the device (may not > be the true cause). Thus my ICAP read conflicts with the device > programming. > > If I delay the read to the ICAP it behaves perfectly. > > StephenArticle: 121468
I use synplify 8.8 to synthesis my design. And my design contain xilinx ip core (generated by core generator). My design can be synthesis with XST. But when I use synplify 8.8, synthesis cannot be done successfully. It seems that synplify does recognise xilinx ip core.Do i need to set some option? Thanks for your help!Article: 121469
Hello Group. Having a home-made PCB board which can adopt to both Spartan-3A XC3S200A and XC3S400A FPGAs in the same FBGA320 footprint, we are having great troubles getting the 400A image of the logic to work stable, while the 200A image seems to work perfectly with the same logic. The symptoms are that various bits or groups of bits seem to "hang" whenever we try to get them on the uController Bus for reading etc.. We have tried using both Xilinx ISE 8.2 and 9.1 as Fitter, but with the same non-stable, although *different* result in respect of which bits cannot be reached. The 3 I/Os being the difference between the two Spartan-3A variants are *not* connected in the PCB. Voltages are correct, and the timing should absolutely be no problem in the design (Fmax 4 times over). We have no troubles loading the FPGA devices in two different configurations. The problems seems consistent among boards with the same FPGA - 200A or 400A. - Have you heard of such problems...? - Or do you just have some type of clue...? Thanks in advance, Jesper.Article: 121470
> 1) Good integration of soft processor with IDE/Tools - intuitive tools They're both effectively the the same. > 4) Cheaper IDE/Tools (I understand Quartus & ISE webpacks are free, but > neither EDK or Nios II Embedded Design Suite are) If you want a free CPU and cross Vendor compatibility, try the LatticeMico32. http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/index.cfm > My take from what I've read so far is that both Xilinx and Altera are > good. Some have said that Quartus is a a little slicker and easier to > use than ISE - if you've had the opportunity to play with both recently, > do you still think that is true? There's not much in it. All the vendors tools can do the job (most of the time ;) ). Cheers, JonArticle: 121471
On Jul 4, 9:03 pm, John_H <newsgr...@johnhandwork.com> wrote: > subint wrote: > > Hi all, > > > I wrote a generate loop to generate a switching logic. I am getting > > the expected circuit from the synthesizer(synplify). But it's not > > working in the simulator ( Modelsim ). > > The code is like this > > > genvar i; > > generate > > for(i=0;i<elements;i=i+1) begin:A1 > > assign source_out[i*8+:8] = (enable[i])?result[address[i*6+:6]*8+: > > 8]:source_in[i*8+:8]; > > end > > endgenerate > > > The requirement is, i have two bus(64 bytes each) and each byte of the > > output of the block can be from the corresponding position from the > > source or from anywhere (according to the address) from the result bus. > > In what way is it not working? Is the source_out always one of the two > results? Are you certain the enable isn't an "x" value? Hai thanks for the reply I dont know how the simulator is behaving. The inputs are correct,no x driving. when i enabled the the first element and given zero as the address it was reading from the result bus but when i changed the address of second element to 1, the element is taken from the source_in even though the enable is high. When i tried to change the coding style by (i*8+:8 to i*8+7:i*8 ) the simulator saying the range specified cannot be a variable what is simple to method of coding this logic so that it work in the simulatorArticle: 121472
On Jul 4, 11:13 am, Pablo <pbantu...@gmail.com> wrote: > Hi everyone. > > I have a core to control a I/O peripheral. This core is based on a > FIFO to get words from a I/O bus (32 bits). But now, I want to read > from the FIFO and copy the words to the BRAM. I know this core runs ok > but I need to map the packets from FIFO to the memory so I could > access whenever I want. > > I have though in DMA to implement it. But at the moment I am not > sure if this solution is the best. I am using "Create and Import > Peripheral Wizard" from Xilinx to add this funtionality to the PowerPC > proccessor and access the words by a pointer. Another solution is to > implement the DMA manually but I am not any idea. > > Any suggestion. > > Regards Pablo Pablo, You probably want to make a PLB master/slave peripheral with SGDMA capability. Try with the wizard you mentioned, run the demo test_peripheral.c code. Take a look at created hw peripheral repository and inspect all VHDL files for included libraries versions. The next step is to read all the datasheets related to this peripheral (particulary SGDMA which is located under %EDK%\hw\XilinxProcessorIPLib \pcores\dma_sg_vX_XX_X\doc ). When you get the idea what it is all about try experimenting with a SW for a start by putting DMA engine to work. Then mess up with user_logic.vhd - the konwledge of VHDL is essential. When you get this far, you will start asking serious questions. Cheers, GuruArticle: 121473
On 5 jul, 11:36, Guru <ales.gor...@email.si> wrote: > On Jul 4, 11:13 am, Pablo <pbantu...@gmail.com> wrote: > > > > > Hi everyone. > > > I have a core to control a I/O peripheral. This core is based on a > > FIFO to get words from a I/O bus (32 bits). But now, I want to read > > from the FIFO and copy the words to the BRAM. I know this core runs ok > > but I need to map the packets from FIFO to the memory so I could > > access whenever I want. > > > I have though in DMA to implement it. But at the moment I am not > > sure if this solution is the best. I am using "Create and Import > > Peripheral Wizard" from Xilinx to add this funtionality to the PowerPC > > proccessor and access the words by a pointer. Another solution is to > > implement the DMA manually but I am not any idea. > > > Any suggestion. > > > Regards Pablo > > Pablo, > > You probably want to make a PLB master/slave peripheral with SGDMA > capability. Try with the wizard you mentioned, run the demo > test_peripheral.c code. Take a look at created hw peripheral > repository and inspect all VHDL files for included libraries versions. > The next step is to read all the datasheets related to this peripheral > (particulary SGDMA which is located under %EDK%\hw\XilinxProcessorIPLib > \pcores\dma_sg_vX_XX_X\doc ). When you get the idea what it is all > about try experimenting with a SW for a start by putting DMA engine to > work. Then mess up with user_logic.vhd - the konwledge of VHDL is > essential. When you get this far, you will start asking serious > questions. > > Cheers, > > Guru Thanks. What's mean SG?Article: 121474
This is not an answer, but try to do the same in an always block using 'if'. Also separtely create the source_out and then combine it.
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