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"Jim Granville" <no.spam@designtools.maps.co.nz> schrieb im Newsbeitrag news:457711fc$1@clear.net.nz... > Antti wrote: > <snip> >> here is utilization report targetting S3-50A 2KB LMB >> RAM (must use Byte write enables!) and OPB UART >> >> >> Total Number 4 input LUTs: 1,195 out of 1,408 84% >> Number used as logic: 848 >> Number used as a route-thru: 5 >> Number used for Dual Port RAMs: 256 >> (Two LUTs used per Dual Port RAM) >> Number used as Shift registers: 86 >> Number of bonded IOBs: 4 out of 108 3% >> IOB Flip Flops: 2 >> Number of GCLKs: 1 out of 24 4% >> Number of DCMs: 1 out of 2 50% >> Number of RAMB16BWEs: 1 out of 3 33% >> >> the LUT utilization is is 84% not 75% Xilinx claims, but maybe MB ver >> 6.0 brings some more size reduction, this report is with MB v 4.00.b > > Or maybe they omit the uart ? > > What do the speeds look like ? > Can you eaily try MB 5? > > -jg > when OPB bus and UART are dropped then the LUT utilization is 75% dont think it makes sense to check with MB 5.00.c, v6 will be more optimized on size, so I guess for now v4 or v3 are less resources than v5 AnttiArticle: 113126
How do I make sense out of the list of boards in the FAQ, other then going through them one at a time. It would help if I could sort them by price and interface. I want something cheap (under $500), with PCI or PCIe. It needs to include the interface to the PCI/PCIe. A $500 board is useless if it requires spending $2500 for IP to communicate with the PCI/PCIe. It also needs to include device drivers for Windows. I want to use it as a co-processor, for experimenting with Genetic Algorithms, Neural Networks, cellular automata, etc, using open source or free development tools. The code I develop will be posted on my website or sourceforge. Many boards I have come across include stuff for getting video or other data in and out of the board. I don't need this stuff. I just want 1 or more FPGAs and a reasonable way to communicate with the code running on the computer. Embedded processors are not required, they would just be wasted space in the FPGA. thanks BillArticle: 113127
Hi,
I'm working on a partial reconfiguration design and need to validate
an assumption.
This question isn't directly releated to partial reconfigration, so
don't let that scare you away.
I have a MicroBlaze created in EDK 8.2 that I must be integrate into a
top level design created in ISE 8.2. I'm using the Virtex II-Pro.
The methodology is to take the system.vhd generated by EDK during
netlist generation and add these component declarations and
instantiations to the top level design. In a partial reconfiguration
design clock primitive must be in the top level design. However, the
system.vhd file uses wrappers for DCMs. Here's my question...am I
removing the DCM wrapper correctly?
I remove the wrapper component declarations by commenting them out (I
only show one here):
-- component dcm_0_wrapper is
-- port (
-- RST : in std_logic;
-- CLKIN : in std_logic;
-- CLKFB : in std_logic;
-- PSEN : in std_logic;
-- PSINCDEC : in std_logic;
-- PSCLK : in std_logic;
-- DSSEN : in std_logic;
-- CLK0 : out std_logic;
-- CLK90 : out std_logic;
-- CLK180 : out std_logic;
-- CLK270 : out std_logic;
-- CLKDV : out std_logic;
-- CLK2X : out std_logic;
-- CLK2X180 : out std_logic;
-- CLKFX : out std_logic;
-- CLKFX180 : out std_logic;
-- STATUS : out std_logic_vector(7 downto 0);
-- LOCKED : out std_logic;
-- PSDONE : out std_logic
-- );
-- end component;
--
-- attribute box_type of dcm_0_wrapper: component is "black_box";
--
Then I change the dcm instantiations only change the component name
from "dcm_0_wrapper" and "dcm_1_wrapper" to dcm.
dcm_0 : dcm -- changed from dcm_0_wrapper
port map (
RST => net_gnd0,
CLKIN => dcm_clk_s,
CLKFB => sys_clk_s(0),
PSEN => net_gnd0,
PSINCDEC => net_gnd0,
PSCLK => net_gnd0,
DSSEN => net_gnd0,
CLK0 => sys_clk_s(0),
CLK90 => clk_90_s(0),
CLK180 => open,
CLK270 => open,
CLKDV => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
STATUS => open,
LOCKED => dcm_0_lock,
PSDONE => open
);
dcm_1 : dcm -- changed from dcm_1_wrapper
port map (
RST => dcm_0_lock,
CLKIN => ddr_feedback_s,
CLKFB => dcm_1_FB,
PSEN => net_gnd0,
PSINCDEC => net_gnd0,
PSCLK => net_gnd0,
DSSEN => net_gnd0,
CLK0 => dcm_1_FB,
CLK90 => ddr_clk_90_s(0),
CLK180 => open,
CLK270 => open,
CLKDV => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => open,
CLKFX180 => open,
STATUS => open,
LOCKED => open,
PSDONE => open
);
Do anyone know if this dcm will behave the same way as it would have
using the wrapper for the Virtex II Pro? I have memory problems that I
can't track down so I'm trying to make sure this changes doesn't effect
how the memory and microprocessor are clocked.
Thanks,
David
Article: 113128Hello, I have a 30-bit accumulator in which I use the last bit as my clock out to the design. In the following way: always @(posedge clk or negedge reset_n) begin if (!reset_n) nco_acc[29:0] <= 0; else nco_acc[29:0] <= nco_acc[29:0] + constant; end assign clk_out = nco_acc[29]; I notice that when the constant is 26-bit width the jitter on the clk_out is acceptable however when the constant is 27 bit wide the jitter on the clk_out is not acceptable. How can I reduce the amount of jitter on the clk_out. (I can't use clkdll all are used already in the design) Thank you,Article: 113129
I have a test bench in which the input stimulus file length is unknown.
I would like to read the file in to my test bench and loop through
each element of the stimulus every clock. The only problem is the the
upper limit of the loop is unknown. I created the following to find
the file length (number of elements) and use that length as the upper
limit of a loop used to read the file into an array which is based off
of that length. Here is the code I created (shortened for posting) but
it doesn't work in Model Sim:
.
.
.
signal ind : integer range 1 to 16777216;
--
***************************************************************************=
=AD*********
-- Determine length of input file
--
***************************************************************************=
=AD*********
filelength : process
variable index : integer :=3D 0;
variable linein : line;
variable test : integer;
file f2 : text open READ_MODE is "adc.txt";
begin
while not (endfile(f2)) loop
readline(f2,linein);
read(linein,test);
index :=3D index + 1;
end loop;
ind <=3D index;
wait;
end process;
--
***************************************************************************=
=AD*********
-- stimuli process
--
***************************************************************************=
=AD*********
stim_proc : process
file f2 : text open READ_MODE is "adc.txt";
type arradc is array(0 to ind) of integer;
variable lineout2 : line;
variable adc : arradc;
variable pixel : integer :=3D 0;
variable lower : integer :=3D 0;
variable upper : integer :=3D 3430;
variable linein2 : line;
begin
start_read <=3D '0';
--
***************************************************************************=
=AD*******
-- read data file
--
***************************************************************************=
=AD*******
i :=3D adc'high;
for i in 0 to adc'high loop
readline(f2,linein2);
read(linein2,adc(i));
end loop;
.
.
.
.
.
I thought it would be pretty straight forward to use the signal "ind"
to set the size of the array type, arradc, and create a variable, adc,
to read the file elements into of type arradc. I keep getting the
following message ...
# ** Fatal: (vsim-3734) Index value 2 is out of range 0 to 1 (null
array).
Makes sense because that is the low limit of the range of the signal
ind.
Basically, what I want to do is determine how long the file is and use
that number to create a type that I can use to create a variable to
read the stimulus into...
Any ideas on how I can do this? Thanks.=20
Ted
Article: 113130
I have a test bench in which the input stimulus file length is unknown.
I would like to read the file in to my test bench and loop through
each element of the stimulus every clock. The only problem is the the
upper limit of the loop is unknown. I created the following to find
the file length (number of elements) and use that length as the upper
limit of a loop used to read the file into an array which is based off
of that length. Here is the code I created (shortened for posting) but
it doesn't work in Model Sim:
.
.
.
signal ind : integer range 1 to 16777216;
--
***************************************************************************=
=AD*********
-- Determine length of input file
--
***************************************************************************=
=AD*********
filelength : process
variable index : integer :=3D 0;
variable linein : line;
variable test : integer;
file f2 : text open READ_MODE is "adc.txt";
begin
while not (endfile(f2)) loop
readline(f2,linein);
read(linein,test);
index :=3D index + 1;
end loop;
ind <=3D index;
wait;
end process;
--
***************************************************************************=
=AD*********
-- stimuli process
--
***************************************************************************=
=AD*********
stim_proc : process
file f2 : text open READ_MODE is "adc.txt";
type arradc is array(0 to ind) of integer;
variable lineout2 : line;
variable adc : arradc;
variable pixel : integer :=3D 0;
variable lower : integer :=3D 0;
variable upper : integer :=3D 3430;
variable linein2 : line;
begin
start_read <=3D '0';
--
***************************************************************************=
=AD*******
-- read data file
--
***************************************************************************=
=AD*******
i :=3D adc'high;
for i in 0 to adc'high loop
readline(f2,linein2);
read(linein2,adc(i));
end loop;
.
.
.
.
.
I thought it would be pretty straight forward to use the signal "ind"
to set the size of the array type, arradc, and create a variable, adc,
to read the file elements into of type arradc. I keep getting the
following message ...
# ** Fatal: (vsim-3734) Index value 2 is out of range 0 to 1 (null
array).
Makes sense because that is the low limit of the range of the signal
ind.
Basically, what I want to do is determine how long the file is and use
that number to create a type that I can use to create a variable to
read the stimulus into...
Any ideas on how I can do this? Thanks.=20
Ted
Article: 113131ted a écrit : > > Basically, what I want to do is determine how long the file is and use > that number to create a type that I can use to create a variable to > read the stimulus into... > > Any ideas on how I can do this? Thanks. You can not do it that way. You will need to use dynamic allocation with pointers (access type) NicolasArticle: 113132
Several reasons I can think of to use BUFIO/BUFR: * BUFIO is faster (>700MHz) and the clock skew is smaller. * BUFIO/BUFR not only save global clock buffers, but also the global routing resources (in V4, each clock region can ONLY have max 8 global clocks. * The input clock can be easily divided with BUFR, which is very useful of serdes designs. Cheers, Jim http://home.comcast.net/~jimwu88/tools/ Brandon Jasionowski wrote: > Is there any advantage of using a BUFIO/BUFR's for driving IOB FF's > versus a BUFG? After looking through that section in the V4 user guide > I'm not sure I really see an advantage other than resource usage of the > global clock buffers. > > Normally I just use the typical IBUFG -> DCM -> BUFG setup and use the > output of the BUFG to drive everything... > > Thanks, > -BrandonArticle: 113133
> Is ISE smart about dealing with the BUFR's? What if you have too many > slices for a given BUFR region and they can't fit? Will it burp? You would just get an error saying the design is unroutable if that happens. > Is there anyway to improve timing with any of the Virtex 4 > capabilities? You can try to see if you can abosorb some of the registers into DSP48. If DSP48s are infereed, first thing to check if you have asynchrounous reset. Registers can not be pushed into DSP48 if you do. Cheers, Jim http://home.comcast.net/~jimwu88/tools/Article: 113134
On 2006-12-06, Bill Burris <wburris@ualberta.ca> wrote: > I want something cheap (under $500), with PCI or PCIe. It needs to > include the interface to the PCI/PCIe. A $500 board is useless if it > requires spending $2500 for IP to communicate with the PCI/PCIe. It > also needs to include device drivers for Windows. For PCI you have a variety of open source IP cores, most notably the PCI bridge on opencores. For PCIe I'm not aware of any free core. Perhaps Enterpoint's PCI board could be interesting for you? It seems to be very cheap and does not include any of the features you say that you don't need :) http://www.enterpoint.co.uk/moelbryn/raggedstone1.html Otherwise, if you really need PCIe, one of the cheaper solutions might be to buy a PCIe based board with an FPGA that includes a PCIe core in hardware. I'm not sure if you can get one of those for less than $500 though. As for windows device drivers, I can't say anything since I'm mostly a Linux user myself. /AndreasArticle: 113135
John, you ned to be more specific: Which device family? How long the delay? What accuracy? Do you have a clock, what frequency? Peter Alfke, Xilinx Applications ========= John wrote: > I have Xilinx FPGA and need to delay a signal to pad. It is not a clock. I would like to do this in the constraints file, any examples?Article: 113136
Georg Acher wrote: > "Peter Alfke" <peter@xilinx.com> writes: > >>Let me explain what I mean with n and n-1. >> >>If you want to reduce the number of pulses per unit time (that's what >>you are doing) you do that by eliminating pulses from the input stream. >>You can achieve ANY desired result by a pattern of eliminated pulses. >>I claim that this pattern can achieve the desired result best when the >>number of adjacently eliminated pulses never varies by more than one. >>If you must eliminate 4 adjacent pulses, then mix that with 3 adjacent >>pulses. Or for a lower "frequency" mix it with 5 adjacent pulses, but >>never with a mixture of 3, 4, and 5 adjacent pulses. There is no need >>for it mathematically. > > > Sounds to me like the good old SN7497 "binary rate multiplier". Yup. Rate multipliers also make good DACs, if you want DC from a RC integrator. Smaller to code than PWM, and higher frequency corner. -jgArticle: 113137
Hello, My application needs to write the on booard SRAM with the data and then read the data from the FPGA. I saw the application note "XSA Board SDRAM controller" on xess's website. It tells me that I need to have source files like "xsasdramcntl.vhd" etc to read the RAM. Would anybody please advice me that how to get these files and put them together with webpack8.1 and program the FPGA as the document is not in detail explain the matter. Thanks Regards johnArticle: 113138
Hi I want to connect an LVDS output from a Stratix II FPGA to a Camera Link frame grabber, but I can't figure out how I should configure the altlvds megafunction to the correct clock setting. Are they at all compatible? Thanks, AvishayArticle: 113139
Am wrote: > Hello, > > I have a 30-bit accumulator in which I use the last bit as my clock out to > the design. > > In the following way: > > > > always @(posedge clk or negedge reset_n) > > begin > > if (!reset_n) nco_acc[29:0] <= 0; > > else nco_acc[29:0] <= nco_acc[29:0] + constant; > > end > > > > assign clk_out = nco_acc[29]; > > > > I notice that when the constant is 26-bit width the jitter on the clk_out is > acceptable however when the constant is 27 bit wide the jitter on the > clk_out is not acceptable. > > How can I reduce the amount of jitter on the clk_out. > > (I can't use clkdll all are used already in the design) > > > > Thank you, What is "acceptable" jitter? If you want a clock with little jitter, you either need a subdivided clock frequency (50MHz/12587, for instance) where you code a simple counter or you use an external PLL. The "problem" with NCOs and jitter is that the clock edge will *always* be at your system clock edge. Sometimes it's before your "ideal" clock, sometimes it's after. If one of your clk_dll resources uses your system clock as input, the CLK0 output can be joined by the CLK90, CLK180, and CLK270 outputs and - with appropriate BUFGMUX or combinatorial logic, you can select which of 4 phases to use rather than toggling at the CLK0 edge only. If you can't even do that, all that's left is FPGA techniques that are beyond the scope of most engineering designs (and not very well characterized so the spec limits won't be easy to pin down). - John_H (who has contemplated a discrete DCM replacement)Article: 113140
The LatticeECP2M devices, being a low-cost SERDES solution, do not support Digitally Controled Impedance matching for the general purpose LVDS inputs. Only the SERDES receivers have the selectable termination as mentioned by JSalk. The LatticeSC devices are a full featured SERDES solution that include among other things, Programmable On-Die Termination (ODT). ODT allows the LatticeSC devices to provide the capibility of to implement many kinds of termination on-chip, minimizing stub lengths and hence improving performance. Gabor wrote: > JSalk wrote: > > Does anyone know if the LATTICE ECP2M FPGA's have on die Digitally > > Controlled Impedance (DCI) matching for input LVDS? I am designing a x4 > > lane PCIe digitiser card with the National 500MSPS ADC and the ECP2M > > FPGA. The ADC output 32 pair LVDS and I have read the FPGA datasheet > > but there is no mention of DCI?? > > > > Thanks > > slkjas > > I'm pretty sure that the general purpose I/O pins do not > have DCI, but the SERDES receivers have selectable > 50 Ohm or 2K ohm differential termination. Look for > ZRX-TERM in the data sheet.Article: 113141
Hi, I've been using X FPGA for years and I often use the following VHDL initial value assignment, especially for finite state machines, counters, etc : signal sCounter : std_logic_vector(7 downto 0) := x"1B"; Using "FPGA Editor", I'm able to validate that the synthesis tool has correctly interpreted the initial value by checking individual slice FF (INIT0, INIT1). Now, my problem. Not having much experience with A Stratix II FPGA, I'm a little confused about how the synthesis and fitter tools use the initial value assignment. Quartus has a synthesis option of "Power-up Don't Care" that can be turned off. Does that means that FF must be initialized using the Assignment Editor using "Power-Up Level" attribute? RTFM didn't help (Quartus II 6.1 Handbook, Stratix II Device Handbook). Also, I tried to check the result with "Chip Editor" but the FF power-up values are not indicated (or I simply don't know how to show them) so I can't validate power-up conditions. For the moment, I don't have access to the hardware (else I would have already made a simple test to check that issue). Anyone has a hint about how Quartus Synthesis handle initial values assignments? Thanks!Article: 113142
If you want nostaglia: I wrote this up in the 1972 Fairchild" TTL Applications Handbook" on page 4-12 as application for the 9318 Priority Encoder. As the French say: Plus ca change, plus c'est la meme chose (pardon the missing accents) Peter Alfke ================= Jim Granville wrote: > Georg Acher wrote: > > > "Peter Alfke" <peter@xilinx.com> writes: > > > >>Let me explain what I mean with n and n-1. > >> > >>If you want to reduce the number of pulses per unit time (that's what > >>you are doing) you do that by eliminating pulses from the input stream. > >>You can achieve ANY desired result by a pattern of eliminated pulses. > >>I claim that this pattern can achieve the desired result best when the > >>number of adjacently eliminated pulses never varies by more than one. > >>If you must eliminate 4 adjacent pulses, then mix that with 3 adjacent > >>pulses. Or for a lower "frequency" mix it with 5 adjacent pulses, but > >>never with a mixture of 3, 4, and 5 adjacent pulses. There is no need > >>for it mathematically. > > > > > > Sounds to me like the good old SN7497 "binary rate multiplier". > > Yup. > Rate multipliers also make good DACs, if you want DC from a > RC integrator. Smaller to code than PWM, and higher frequency corner. > -jgArticle: 113143
I'm trying to get the PAR tool to run using makefiles and it consistently crashes with the message: Starting Placer Phase 1.1 Phase 1.1 (Checksum:98ee53) REAL time: 32 secs Phase 2.7 Phase 2.7 (Checksum:1312cfe) REAL time: 32 secs Phase 3.31 Phase 3.31 (Checksum:1c9c37d) REAL time: 32 secs FATAL_ERROR:Place:PlXil_GClkDD.c:234:1.1.4.4 - in file "" Line 0, Column 0, Message: Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com If I run PAR from the command line, it runs OK. If I use nmake or wmake and my makefile, it crashes. I've opened a WebCase, but I've little hope that they will resolve anything. Has anyone else run across this? Thanks! John PArticle: 113144
Sorry for the hick-up. The jitter has little to do with the length of the accumulator, but rather with the nature of the accumulated number. A higher clock rate of the accumulator always helps. There are wasteful ways to reduce the jitter with multiple accumulators plus a fast Serializer. I am playing around with 16 accumulators plus an MGT, to reduce the jitter below 200 ps for any value of a 32-bit DDS circuit. But that's rather extreme... (Except when you have plenty of accumulators to spare ...) Peter Alfke On Dec 6, 4:57 pm, "Peter Alfke" <p...@xilinx.com> wrote: > On Dec 6, 2:50 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > > > Am wrote: > > > Hello, > > > > I have a 30-bit accumulator in which I use the last bit as my clock out to > > > the design. > > > > In the following way: > > > > always @(posedge clk or negedge reset_n) > > > > begin > > > > if (!reset_n) nco_acc[29:0] <= 0; > > > > else nco_acc[29:0] <= nco_acc[29:0] + constant; > > > > end > > > > assign clk_out = nco_acc[29]; > > > > I notice that when the constant is 26-bit width the jitter on the clk_out is > > > acceptable however when the constant is 27 bit wide the jitter on the > > > clk_out is not acceptable. > > > > How can I reduce the amount of jitter on the clk_out. > > > > (I can't use clkdll all are used already in the design) > > > > Thank you,What is "acceptable" jitter? > > > If you want a clock with little jitter, you either need a subdivided > > clock frequency (50MHz/12587, for instance) where you code a simple > > counter or you use an external PLL. > > > The "problem" with NCOs and jitter is that the clock edge will *always* > > be at your system clock edge. Sometimes it's before your "ideal" > > clock, sometimes it's after. > > > If one of your clk_dll resources uses your system clock as input, the > > CLK0 output can be joined by the CLK90, CLK180, and CLK270 outputs and > > - with appropriate BUFGMUX or combinatorial logic, you can select which > > of 4 phases to use rather than toggling at the CLK0 edge only. > > > If you can't even do that, all that's left is FPGA techniques that are > > beyond the scope of most engineering designs (and not very well > > characterized so the spec limits won't be easy to pin down). > > > - John_H > > (who has contemplated a discrete DCM replacement)Article: 113145
Avishay, Yes, they are compatible. I have done this in both the Cyclone and Stratix families, both using the MegaWizard and building my own interface. The MegaWizard is pretty straight forward. What difficulties are you experiencing? CamerLink is made up of 3 banks (base, medium, and full) of 4 lanes with a serialization factor of 7 for each lane. Each bank has an associated clock, which most newer grabbers can handle up tp 85MHz. All you have to do is tell the MegaWizard how many lanes, what the serialization factor is, and the speed of the data. The timing, when using the MegaWizard, is all done under the hood. Rob "avishay" <avishorp@yahoo.com> wrote in message news:1165444993.193814.114030@n67g2000cwd.googlegroups.com... > Hi > I want to connect an LVDS output from a Stratix II FPGA to a Camera > Link frame grabber, but I can't figure out how I should configure the > altlvds megafunction to the correct clock setting. Are they at all > compatible? > > Thanks, > Avishay >Article: 113146
Hello Francois, Please refer him to the Chapter 8, Page 46 of the Quartus II 6.1 Handbook. In short, Quartus will honor initial or default values in VHDL, except for state machines. For an FSM with an asynchronous reset, it will use the asynchronous reset state as the power-up state. In the absence of an asynchronous reset, we use the first state in the enumerated type, or the state that was assigned the encoding "000..0" with a syn_encoding attribute. You can verify power-up settings by looking for inverted registers in the report file It is in the Analysis and Synthesis section under Register Statistics. If a register must power-up to one, Quartus will use not-gate pushback to achieve the effect because all device registers in Stratix, Cyclone, Stratix II, etc power up to zero. http://www.altera.com/literature/hb/qts/qts_qii51008.pdf Hope this helps, Subroto Datta Altera Corp. On Dec 6, 4:44 pm, "Francois Choquette" <fchoque...@gmail.com> wrote: > Hi, > > I've been using X FPGA for years and I often use the following VHDL > initial value assignment, especially for finite state machines, > counters, etc : > > signal sCounter : std_logic_vector(7 downto 0) := x"1B"; > > Using "FPGA Editor", I'm able to validate that the synthesis tool has > correctly interpreted the initial value by checking individual slice FF > (INIT0, INIT1). > > Now, my problem. Not having much experience with A Stratix II FPGA, > I'm a little confused about how the synthesis and fitter tools use the > initial value assignment. Quartus has a synthesis option of "Power-up > Don't Care" that can be turned off. Does that means that FF must be > initialized using the Assignment Editor using "Power-Up Level" > attribute? RTFM didn't help (Quartus II 6.1 Handbook, Stratix II > Device Handbook). Also, I tried to check the result with "Chip Editor" > but the FF power-up values are not indicated (or I simply don't know > how to show them) so I can't validate power-up conditions. For the > moment, I don't have access to the hardware (else I would have already > made a simple test to check that issue). > > Anyone has a hint about how Quartus Synthesis handle initial values > assignments? > > Thanks!Article: 113147
> Otherwise, if you really need PCIe, one of the cheaper solutions might be > to buy a PCIe based board with an FPGA that includes a PCIe core in > hardware. I'm not sure if you can get one of those for less than $500 > though. Another option is the PEX 8311 from PLX Technology -- it's a single-chip PCI-E bridge that looks like it takes a lot of the pain involved in PCI away. Like you, I don't want to spend a lot of money on a core, and for my current project (which is GPL'd) I don't want to depend on any non-Free IP, even if it is zero cost. The chips from PLX are expensive -- in some cases they cost more than the FPGA that you'd want to hook up to them. My group has considered developing a logic-dense (think lots of spartan-3s) PCI-E board for experimenting with some of the various applications you've mentioned, but getting boards cut, populated, and debugged makes every project at least a $5k one -- so it's unlikely to be in your price range. Keep in mind too that, for the really "interesting" stuff, you don't generally need to physically touch hardware. We did all of our studies with wavelet compression in FPGAs without ever touching hardware. The synthesis and sim tools are all available cheap and run under windows, and generally let you learn far more about what your code is doing than the physical hardware would. ...EricArticle: 113148
Hi Peter, Peter Alfke wrote: > Ashish, everybody agrees that the DCM is the best solution, but you > never told us why you want to avoid it at any cost. I have a clock which will change in runtime(25 Mhz to 50 MHz to 100 MHz) and expect DCM to take time in locking the clock. I just wanted a straight 180 deg ph shift and dont wish to have any wait period for DCM to lock the o/p. Please correct me if my understanding is wrong. > Peter Alfke > Thank You Ashish > On Dec 6, 7:42 am, "Ashish" <ashish.shringarp...@gmail.com> wrote: > > Frank Buss wrote: > > > Alan Myler wrote: > > > > > > Use an inverter? > > > > > I don't think this will result in an exact 180 shifted signal at 100 MHz, > > > because of the delay of the inverter, so using a DCM is a good idea.DCM is a always the best option. > > I just wanted to avoid using this resource. Using inverter it might not > > be exact 180 deg phase shift considering 100 Mhz clock and inverter > > delay. > > > > > > > > > -- > > > Frank Buss, f...@frank-buss.de > > >http://www.frank-buss.de,http://www.it4-systems.deIs it still possible to use IDELAY component without having to loop > > back through IO pad? > > > > Thanks. > > > > AshishArticle: 113149
Hello Group. Not being that familiar with Altera's Quartus II, and it may be a beginners problem... Anyways... I'm compiling a VHDL-based design for the MAX-II EPM1270F256C5, which Ifinally managed to get error-free. When trying to back-annotate the Fitter's suggestion for the pin placing, the Pin Planner's list section actaully states two entries for the same physical pin and signal like this: mpifdX[7] PIN_J14 mpifdX[7]~0 PIN_J14 I have run the Remove Assignments before the Back-annotation The signals giving this problem are always and ONLY the bidir's. - Has anyone seen something similar and can give an explanation...? Thanks i advance. Jesper.
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