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On Aug 24, 8:16 am, "Symon" <symon_bre...@hotmail.com> wrote: > http://www.samtec.com/sudden_service/current_literature/powerposer.asp > > I saw this and thought of comp.arch.fpga . I'm not endorsing this, just a > 'FYI'. I wonder if any of you guys have used this yet? I see it uses the X2Y > caps we mentioned a few months back. > > Anyway, I hope it's interesting. > Cheers, Syms. That looks really interesting. It mentions Virtex 4, and I'm guessing there aren't too mane versions of the PowerPoser available yet. I read in the Virtex 5 literature that the new devices have some bypass caps built into the package. I wonder if the PowerPoser would have as dramatic an effect on V5 signal integrity? Regards, GaborArticle: 123351
On Aug 24, 6:42 am, "RCIngham" <robert.ing...@gmail.com> wrote: > >John_H <newsgr...@johnhandwork.com> wrote: > > >... > >> Here is a link: > > http://www.xilinx.com/publications/xcellonline/index.htm > > > > >But these are single article PDFs, not whole magazine PDFs, as far as I > can > >tell... > > From:http://www.xilinx.com/publications/xcellonline/xcell_60/index.htm > > "On this site, you can download individual articles for reading or > printing. Or if you like, you can read the magazine in its entirety by > registering for a FREE subscription immediately available in digital > format." > > Hope that helps! Of course "read the magazine in its entirety" means the on-line digital version, not a downloadable pdf. Your other possibility until the journals are archived, is to download all of the articles in pdf format and stick them together using a pdf merger. You may miss some of the excellent ads in the magazine this way, though. I wonder if Xilinx realized this when they published the articles individually? Regards, GaborArticle: 123352
On Aug 24, 6:09 am, "Rutger Stoots" <m...@home.it> wrote: > Hello out there, > > I don't know whether this is the right group to post this message. Still, > I'll try anyway. > Yeah, this is the place. > For a few weeks I'm using the Xilinx ISE 9.2i WEBPack. I wrote my code in > vhdl, simulated and post-simulated it until I was satisfied with the > results. So far so good. > Then I JTAGged it to the Spartan-3 Starter Board, which went fine in Xilinx > ISE 8.1, but to my amazement doesn't work in 9.2i. It just says "failed", > the "DONE" pin doesn't go up. I looked at the properties of the bit > generator, but I don't know if, nor what I'm doing wrong. > Does anyone of you know of this problem. Does anyone have a solution? I > can't find anything at Xilinx. > > Thanks > Rutger Are you saying you had a working project in 8.1 and the same project won't download in 9.2? Or is it a new project? If so, can you get anything (your old project or Xilinx sample code) to download successfully in 9.2? Have you installed the service pack 1 over 9.2? Regards, GaborArticle: 123353
"Gabor" <gabor@alacron.com> wrote in message news:1187959290.089887.19900@r23g2000prd.googlegroups.com... > On Aug 24, 6:09 am, "Rutger Stoots" <m...@home.it> wrote: >> Hello out there, >> >> I don't know whether this is the right group to post this message. Still, >> I'll try anyway. >> > > Yeah, this is the place. > >> For a few weeks I'm using the Xilinx ISE 9.2i WEBPack. I wrote my code in >> vhdl, simulated and post-simulated it until I was satisfied with the >> results. So far so good. >> Then I JTAGged it to the Spartan-3 Starter Board, which went fine in >> Xilinx >> ISE 8.1, but to my amazement doesn't work in 9.2i. It just says "failed", >> the "DONE" pin doesn't go up. I looked at the properties of the bit >> generator, but I don't know if, nor what I'm doing wrong. >> Does anyone of you know of this problem. Does anyone have a solution? I >> can't find anything at Xilinx. >> >> Thanks >> Rutger > > Are you saying you had a working project in 8.1 and the same project > won't > download in 9.2? Or is it a new project? If so, can you get anything > (your old project or Xilinx sample code) to download successfully in > 9.2? > Have you installed the service pack 1 over 9.2? > > Regards, > Gabor > I developped the project in 9.2, but the same source compiles in 8.1 as well. The problem is when I compile the source in a 9.2 project and generate a "bit"-file, I can't upload (JTAG) it to the board with Impact (yes, I do have the latest service packs). If I use the same source in a 8.1 project it compiles and uploads smoothly. Still, I want to use the latest software (e.g. there are better optimizations). I have the feeling that some obscure option of Impact or Bitgen is different from 9.2 compared to 8.1. RutgerArticle: 123354
Hi. I am using Xpower for estimating the total dynamic power consumption of my processor which is described in VHDL. I would be thankful if you could tell me how I can calculate this value using the data produced in Xpower report file. Thanks, MahshidArticle: 123355
Hey guys & gals,
I've been experiencing some difficulty using the opb_hwicap for EDK
9.1. I'm trying to use it for reading/writing BRAM data w/ it's new
32-bit, virtex4 support. Anyway, I cannot seem to be able to get it to
run. I've noticed - first off, that the def "XHI_FAR_BRAM_BLOCK" is set
to 1, which is correct for the V2 but not V4... So i've set the
block_type to 2 for read/write BRAMs. Anyway -- I've been using the
XHwIcap_DeviceReadFrameV4 & XHwIcap_DeviceWriteFrameV4 functions without
success. They do RETURN "XST_SUCCESS", but from what I'm seeing, it's
not correct. For example, if I write something to a location and then
read it, I always get 0's. I'm reading the attached BRAM and see some
starting packet stuff, and then zeros. Has anyone used the new 32-bit
hwicap w/ success for reading/writing BRAMS. If so, sample code perhaps
that I could test please? Oh, fyi - it seems to be able to read config
registers, and the BRAMs I'm reading/writing to are not being accessed
when the ICAP attempts read/write. I appreciate any help.
Kevin
Article: 123356Yes this was an undocumented constraint that was included in the 8.2 PR toolsArticle: 123357
Hi there, I have a more general question about processor design, hope that is alright ;) I am just implementing some kind of MIPS core, and I am about to integrate the memory hiarchy with instruction and data cache which is linked to a SRAM that contains the binary. So I was thinking of having one module for each the data and instruction cache which are both connected to the SRAM module. In this case I need two datawrite, dataread signals, one from each cache to the memory is that right? In addition, when a cache miss occurs I was thinking of stalling the pipeline for 2 clock cycles until the cache has been updated with the memory content. Is this a proper approach? Cheers, RomanArticle: 123358
> In this case I need two > datawrite, dataread signals, one from each cache to the memory is that > right? Can't see the need for the instruction cache to write to memory. > In addition, when a cache miss occurs I was thinking of stalling > the pipeline for 2 clock cycles until the cache has been updated with > the memory content. Is this a proper approach? How wide is each cache line? Often you want to make it multiple words. Other than that, it is normal to stall the pipeline while refilling the cache, although a goal is to try an minimize how often and for how long this occurs. Init funny that ARM/MIPS used to make millions selling something students/beginners now design. Cheers, JonArticle: 123359
> Can't see the need for the instruction cache to write to memory. Good point;) >> In addition, when a cache miss occurs I was thinking of stalling >> the pipeline for 2 clock cycles until the cache has been updated with >> the memory content. Is this a proper approach? > > How wide is each cache line? Often you want to make it multiple words. For a start I wanna simulate the basis behaviour, and as soon as this is running smoothly I will take the next step. Lets say the wide of the cache line is 8 words, in this case I need a sram to bus interface with 8*wordsize to transfer it in one clock cycle. Or does the cache fetch a line on a word by word basis? Cheers, RomanArticle: 123360
"Gabor" <gabor@alacron.com> wrote in message news:1187958800.714022.23500@z24g2000prh.googlegroups.com... > On Aug 24, 8:16 am, "Symon" <symon_bre...@hotmail.com> wrote: >> http://www.samtec.com/sudden_service/current_literature/powerposer.asp >> >> I saw this and thought of comp.arch.fpga . I'm not endorsing this, just a >> 'FYI'. I wonder if any of you guys have used this yet? I see it uses the >> X2Y >> caps we mentioned a few months back. >> >> Anyway, I hope it's interesting. >> Cheers, Syms. > > > That looks really interesting. It mentions Virtex 4, and I'm guessing > there > aren't too mane versions of the PowerPoser available yet. I read in > the > Virtex 5 literature that the new devices have some bypass caps built > into > the package. I wonder if the PowerPoser would have as dramatic an > effect on V5 signal integrity? > > Regards, > Gabor > Hi Gabor, Reading through the bumf on the Samtec site, it would seem that Virtex 4 onwards has built in "IC power rails with substantial in package and/or on-die storage". Check out page 22 of this:- http://www.samtec.com/sudden_service/current_literature/PowerPoser_Technical_043007.pdf I reckon it won't be long before the FPGA manufacturers will build the power poser stuff onto the part, but this looks like a good solution for now. Cheers, Syms.Article: 123361
"mahshid" <mahshid.sedghy@gmail.com> wrote in message news:1187962737.141952.255580@q5g2000prf.googlegroups.com... > Hi. > I am using Xpower for estimating the total dynamic power consumption > of my processor which is described in VHDL. I would be thankful if you > could tell me how I can calculate this value using the data produced > in Xpower report file. > > Thanks, > Mahshid > Have you tried reading the FFAQ? http://www.xilinx.com/products/design_tools/logic_design/verification/XpowerAnalyzerFAQ.pdf HTH., Syms.Article: 123362
"PeteS" <axkz70@dsl.pipex.com> wrote in message news:6sOdnVh67u2qjVLbnZ2dnUVZ8silnZ2d@pipex.net... > The only problem there is that it's difficult to get the capacitance > values necessary for proper decoupling inside the silicon, > Hi Pete, I agree. I believe the V4 on-package capacitance is mounted on the BGA 'circuit board'. Somewhere underneath that metal lid. Cheers, Syms.Article: 123363
Rutger Stoots wrote: > I developped the project in 9.2, but the same source compiles in 8.1 as > well. > > The problem is when I compile the source in a 9.2 project and generate a > "bit"-file, I can't upload (JTAG) it to the board with Impact (yes, I do > have the latest service packs). If I use the same source in a 8.1 project it > compiles and uploads smoothly. > > Still, I want to use the latest software (e.g. there are better > optimizations). I have the feeling that some obscure option of Impact or > Bitgen is different from 9.2 compared to 8.1. Can you grab a bit file from the 8.1 and try to load it with the 9.2 Impact? If that fails, it shows the problem is in 9.2's Impact loader. If it works, then try to load the 9.2 bit file with 8.1 If that fails, then it shows that the bit file is not created properly, and must be failing CRC checking on the FPGA. This should narrow the search for the problem quite a bit. JonArticle: 123364
> >> In addition, when a cache miss occurs I was thinking of stalling > >> the pipeline for 2 clock cycles until the cache has been updated with > >> the memory content. Is this a proper approach? > > > How wide is each cache line? Often you want to make it multiple words. > > For a start I wanna simulate the basis behaviour, and as soon as this is > running smoothly I will take the next step. Lets say the wide of the > cache line is 8 words, in this case I need a sram to bus interface with > 8*wordsize to transfer it in one clock cycle. Or does the cache fetch > a line on a word by word basis? Usually wordsize is 32-bits, so, if you want to implement this for real, most FPGA boards will have 32-bit SRAM, so you will need to do the transfer in several cycles. Nothing unusual about that. How are you going to perform uncached accesses to peripherals? I'd recommend having a bus between the cache and SRAM, although perhaps you want to keep it simple at this stage. If you want to look at some example source code, look at the Lattice Mico 32. Cheers, JonArticle: 123365
>There are 3 kinds of lies: lies, damn lies, and benchmarks. >;-) >For instance, in FFT benchmarks, the quoted speeds for DSPs are produced >from carefully-optimised Assembler sub-routines. ... What's wrong with that? Do you go hunt for some crappy code when you need a FFT routine? Do you avoid routines in the c library if they have been hand optomized? It helps if they say what code they are using and how to get it. It's even better if it's open source. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 123366
Here's one thing I'm trying to figure out. I'm using my same clocking module and building two chips, one with much more utilization than the other. The constraints are the same in both builds. The less utilized design shows only 4 clocks as expected when looking at the clock report section of the .par file. However, the more utilized design shows those 4 as well as several clocks showing up as "local." Can someone please explain what this means? I've copy-pasted both clock reports below. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------ +-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------ +-------------+ |DataConv1xClock40Out | | | | | | | | BUFGMUX5S| No | 16 | 0.287 | 2.406 | +---------------------+--------------+------+------+------------ +-------------+ |DataConv2xClock80Out | | | | | | | | BUFGMUX3S| No | 5 | 0.156 | 2.338 | +---------------------+--------------+------+------+------------ +-------------+ | PHYClock4xOut | BUFGMUX1S| No | 47 | 0.304 | 2.494 | +---------------------+--------------+------+------+------------ +-------------+ | PHYClock6xOut | BUFGMUX6P| No | 47 | 0.366 | 2.494 | +---------------------+--------------+------+------+------------ +-------------+ ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------ +-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------ +-------------+ |dcm_80_to_20_and_100 | | | | | | | _0_CLK0_OUT | BUFGMUX1P| No | 1644 | 0.784 | 2.696 | +---------------------+--------------+------+------+------------ +-------------+ |interFPGA_fixed_80MH | | | | | | | z_clk | BUFGMUX6P| No | 288 | 0.499 | 2.535 | +---------------------+--------------+------+------+------------ +-------------+ | clk_120_MHz | BUFGMUX4S| No | 1389 | 0.562 | 2.608 | +---------------------+--------------+------+------+------------ +-------------+ |filter_fixed_40MHz_c | | | | | | | lk | BUFGMUX7S| No | 1869 | 0.455 | 2.613 | +---------------------+--------------+------+------+------------ +-------------+ | clocks_1_clk1 | BUFGMUX5P| No | 6286 | 0.785 | 2.697 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_1 | Local| | 7419 | 6.832 | 8.947 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_11 | Local| | 250 | 1.244 | 7.358 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_10 | Local| | 254 | 2.044 | 7.111 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_2 | Local| | 289 | 2.028 | 7.566 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_14 | Local| | 246 | 5.646 | 8.785 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_13 | Local| | 251 | 1.938 | 8.431 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_6 | Local| | 257 | 2.709 | 7.238 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_9 | Local| | 254 | 1.280 | 6.727 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_3 | Local| | 248 | 2.161 | 4.204 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_7 | Local| | 246 | 1.016 | 6.781 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_5 | Local| | 252 | 1.316 | 5.791 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_8 | Local| | 237 | 1.117 | 7.405 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_12 | Local| | 239 | 2.247 | 7.950 | +---------------------+--------------+------+------+------------ +-------------+ |VariableBWClockGenVi | | | | | | | rtex2_inst_4 | Local| | 236 | 3.172 | 5.255 | +---------------------+--------------+------+------+------------ +-------------+ |phycore_with_mpi_ins | | | | | | |t/phycore/tx_top_ins | | | | | | |t/legacy_preamble_in | | | | | | | st.sym_count(2) | Local| | 10 | 0.007 | 1.496 | +---------------------+--------------+------+------+------------ +-------------+Article: 123367
Symon wrote: > "Gabor" <gabor@alacron.com> wrote in message > news:1187958800.714022.23500@z24g2000prh.googlegroups.com... >> On Aug 24, 8:16 am, "Symon" <symon_bre...@hotmail.com> wrote: >>> http://www.samtec.com/sudden_service/current_literature/powerposer.asp >>> >>> I saw this and thought of comp.arch.fpga . I'm not endorsing this, just a >>> 'FYI'. I wonder if any of you guys have used this yet? I see it uses the >>> X2Y >>> caps we mentioned a few months back. >>> >>> Anyway, I hope it's interesting. >>> Cheers, Syms. >> >> That looks really interesting. It mentions Virtex 4, and I'm guessing >> there >> aren't too mane versions of the PowerPoser available yet. I read in >> the >> Virtex 5 literature that the new devices have some bypass caps built >> into >> the package. I wonder if the PowerPoser would have as dramatic an >> effect on V5 signal integrity? >> >> Regards, >> Gabor >> > Hi Gabor, > Reading through the bumf on the Samtec site, it would seem that Virtex 4 > onwards has built in "IC power rails with substantial in package and/or > on-die storage". > > Check out page 22 of this:- > http://www.samtec.com/sudden_service/current_literature/PowerPoser_Technical_043007.pdf > > I reckon it won't be long before the FPGA manufacturers will build the power > poser stuff onto the part, but this looks like a good solution for now. > > Cheers, Syms. > > The only problem there is that it's difficult to get the capacitance values necessary for proper decoupling inside the silicon, but it's certainly going to significantly reduce ground/Vdd bounce simply because they [caps] are closer (in the inductive sense) to the load when within the package, and that's a limiting factor in many newer board designs. This will make the designer's life simpler, but I suspect the only real 'tuning' is optimal part placement on the powerposer of the decoupling components relative to the targeted part power / ground rails. Cheers PeteSArticle: 123368
On Aug 24, 8:12 pm, "Symon" <symon_bre...@hotmail.com> wrote: > "mahshid" <mahshid.sed...@gmail.com> wrote in message > > news:1187962737.141952.255580@q5g2000prf.googlegroups.com...> Hi. > > I am using Xpower for estimating the total dynamic power consumption > > of my processor which is described in VHDL. I would be thankful if you > > could tell me how I can calculate this value using the data produced > > in Xpower report file. > > > Thanks, > > Mahshid > > Have you tried reading the FFAQ?http://www.xilinx.com/products/design_tools/logic_design/verification... > > HTH., Syms. Thanks, but there's not relevant information in the PDF regarding calculation of Dynamic power.Article: 123369
"Jon Elson" <elson@wustl.edu> wrote in message news:46CF2C8E.20809@wustl.edu... > Can you grab a bit file from the 8.1 and try to load it with the 9.2 > Impact? If that fails, it shows the problem is in 9.2's Impact loader. > If it works, then try to load the 9.2 bit file with 8.1 If that fails, > then it shows that the bit file is not created properly, and must be > failing CRC checking on the FPGA. This should narrow the search for the > problem quite a bit. > > Jon > Good thinking, Jon. I'll try that, I'll be back after the weekend. RutgerArticle: 123370
Sylvain Munaut <SomeOne@SomeDomain.com> wrote: > Hi, > > I've been working on Virtex 4 with a DDR2 controller for about 1 year > now and it works fine. The controller is based on MiG generated > controller that we modified. The changes were some little bug fixes > and changes in the user interface. > This controller uses the ISERDES / OSERDES so that at the end, the > physical interface of DDR2 is 8 bits at 250 MHz and the user interface > internally is 32 bits at 125 MHz. Did you use the same speed in your previous design or ist it slower now than it was before? Or is the routing maybe different (shorter traces)? I have a DDR2-design on a Virtex4 as well, running at 125MHz, and the calibration doesn't work there because the maximum delay the IDELAY can do is 5ns. I don't remember the exact details, but I think during calibration they delay the DQS until they detect 2 edges to measure the cycle time and match it to the FPGA-internal clock, and then set the delay for the data pins accordingly, so there is a phase difference of 90 degrees. In my case the delaying for the strobes didn't work, the calibration would just never find the second edge because it could not delay by more than 5 ns. If you have very short traces between FPGA and DRAM giving you a delay of maybe 200ps, you have to delay the strobe for another 3.2ns just to find the first edge, and then another 4ns (if you're running at 125MHz) to find the second edge, which is a total of 7.2ns, which the IDLEAY can't give you. So in my case the calibration just would run to the maximum and then give up. I turned it off and fixed the delays manually to get ariound this. HTH, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 123371
So I don't want to appear to be the advocate of designs that rely on multicycle constraints, and therefore sprinke around like salt and pepper. However, there are occasions, mostly in core usage which do not run at full data rate clocks, where a designer runs into this problem. The point is that multicycle constraints are as powerful as a shotgun .... and possibly just as dangerous -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. email : jretta@rtc-inc.com web : www.rtc-inc.com "Andy" <jonesandy@comcast.net> wrote in message news:1187880844.530688.101600@x35g2000prf.googlegroups.com... > On Aug 21, 1:04 pm, Ray Andraka <r...@andraka.com> wrote: >> I avoid multi-cycle constraints like the plague as well. They bring in >> too many opportunities to make a mistake that will bite you later. > > Seems like a couple of years ago, there were some startups that were > trying to create tools that would automatically/formally identify and/ > or verify multi-cycle and false paths/constraints. Seemed like a > really great idea. Anyone know or try one of these? > > I'm with Mike and Ray, I avoid such constraints if at all possible. It > is just too hard to verify that you have them specified correctly, and > you are not accidentally relaxing a single clock path. They are an > absolute last resort for me. With enabled clock buffers, many circuits > can be converted to slower clocks and automatically verified in STA > with no special constraints (other than clock rates/relations). > > Andy >Article: 123372
John Retta wrote:
> So I don't want to appear to be the advocate of designs that
> rely on multicycle constraints, and therefore sprinkle around
> like salt and pepper.
I commend you for actually answering Eli's question
rather than just recoiling in horror as I did.
> However, there are occasions, mostly in core usage which
> do not run at full data rate clocks, where a designer runs into
> this problem.
Yes, if I didn't have source code for the core
or if I didn't know how to rewrite it or pipeline the problem
sections, I might be in the same boat.
> The point is that multicycle constraints are as powerful
> as a shotgun .... and possibly just as dangerous
And quite unnecessary for new fpga designs
where registers are free.
-- Mike Treseler
Article: 123373I've realised there are many things I don't know about the synthesis process under Xilinx XST. The top level of code is associated with a .ucf file, which defines pinout and timing constraints. There's a wizard for timing constraints. It writes into the .ucf file. What about sub-modules? The synthesis properties can be defined differently for each sub-module with an xcf file. You can opt to use .xcf files under synthesis/properties/use synthesis constraint file Is the timing constraint syntax the same in .xcf as in .ucf? ##### "Daddy, where do baby .xcf files come from?" ###### How do I enter a .xcf file? There's no obvious way to do it from the wizard; it writes .ucf files. As there seems to be no wizard, must I write constraints into .xcf files manually? Must I use a text editor and set the file type to .xcf? When I synthesise the top level, the sub-modules will be synthesised according to the constraints in their .xcf files. Is that correct? I've looked at the XST User guide, but I'm still puzzled. All comments gratefully received. -- Mit der Dummheit kämpfen Götter selbst vergebens.Article: 123374
On 23 Aug., 18:22, eli.billa...@gmail.com wrote: > Regardless, I got this error while synthesizing a Verilog project. The > problem was that I adopted a project from ISE 7.1.04. After starting a > fresh project on ISE 9.2, handpicking the HDL files and UCFs (and so > on) the synthesis went smoothly. I had the problem with a fresh 9.2 VHDL-only project. Which version of fixed_pkg did you use? The Xilinx-adapted from http://www.eda-stds.org/fphdl/vhdl.html, or the original package from the VHDL200x website? Thanks, Andreas
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