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quick survey... Would it be of value to provide cheap on-chip one time programmable memory in an FPGA like Cyclone II? Say 1-10Mbit depending on density. It would be field or user programmable either via a programmer (very fast) or by user logic. It would be very secure (anti-copy) for: secure s/w code with on-chip processor secure data storage configuration data(s) etc. Please share your thoughts on the value (I would pay X% premium) and the type of ways you would use it? Thanks in advance AtorisArticle: 73676
Guy wrote:
> quick survey...
>
> Would it be of value to provide cheap on-chip one time programmable
> memory in an FPGA like Cyclone II?
Yes.
> Say 1-10Mbit depending on density.
>
> It would be field or user programmable either via a programmer (very
> fast) or by user logic.
Can you clarify - would this need Supra Voltages/Currents, or
can the FPGA program itself, while running. ( eg could an
NV event log be created ? )
> It would be very secure (anti-copy) for:
> secure s/w code with on-chip processor
> secure data storage
> configuration data(s)
> etc.
>
> Please share your thoughts on the value (I would pay X% premium) and
> the type of ways you would use it?
First one is easy, X = 0 :)
>
> Thanks in advance
An interesting question.
From a wider industry perspective, there is a trend in the
Microcontroller sector, to offer MASK devices, where a couple of
years ago the party line was 'we will now only make FLASH'.
This must be driven by a number of factors, and clearly customer
demand, because of
** MASK is always going to be lower cost (fewer process steps, and testing)
** Zero risk of field bit erasure
** No programming needed at customer end.
** Some apps stipulate that high voltage must be needed for program,
so they want to _guarantee_ errant software cannot jump into the
FLASH loader Block erase routines, for example :)
Designers love Flash, because they can change it easily, but there
are many products that are code-stable, and the bean-counters prefer
the lowest cost options.
So, back to your Cheap OTP memory in FPGA question ?
First step would be to give every device a 128 bit unique ID, that
could be used for seed, and ID usage.
Users would access that 'for free' in their present flows.
Next step is more questions :
What is the yield of this memory ? All OTP memory has failures, so
what does the user do, if this occurs - remove the FPGA from a expensive
PCB ?
Speed and Width of the memory ?
Can it be easily swapped for (say) off chip NV memory, or on Chip RAM ?
Market Model here is then the same as for MASK uC.
Product development is using NV memory, and when proven stable,
the lower price option is chosen.
This applies to both CODE and FPGA CONFIG memory spaces.
For configuration data, I would guess the cost of this memory
would start to be significant, which would push up the device
variant price, and impact those users who never used this feature.
I would imagine, provided it was easy to develop with, that
OTP memory would expand the usage of the simplest soft processors,
for state engines, and stable-code layers.
Quite small OTP memory could be usefull here, << 1MBit, which
should have minimal impact on device cost ?
-jg
Article: 73677>It would be very secure (anti-copy) for: > secure s/w code with on-chip processor > secure data storage > configuration data(s) I'm missing something. How can data be both secure and useful? If I can read it back out to use it, clearly the bad guy can too. It might take him a while to write some code to get it. That doesn't seem like a big deal compared to the recent discusions on extracting the encryption key for the configuration bit stream. Same general idea for secure code. You might be able to make that secure if you had a dedicated memory that was only good for code. But that seems against the general idea of flexibility that makes FPGAs so interesting. Besides, it would probably be a pain to debug - or the debugging tools could be used to read the code memory. One time secure configuration data might be interesting. I'm not sure how much I would pay for it. Not much for anything I can think of right now. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 73678
Hi, The solution of ken doesn't work i still het the same error. Error Code <xcmap.c:3416 Invalid LUT instantiation. Have you included the virtex.v(hd) file, and an INIT value?> @E:Internal Error The lut has an init value. When i add the virtex2 library this is gone, but with vcomponents it is still there. Bram "Symon" <symon_brewer@hotmail.com> wrote in message news:2rqv0sF1bi104U1@uni-berlin.de... > ...or, if you're using ModelSIM (say), you can map the virtex2 library to > the UNISIM one. But Ken's solution is better... > Cheers, Syms. > "Ken McElvain" <ken@synplicity.com> wrote in message > news:GwV5d.11117$NC6.495@newsread1.mlpsca01.us.to.verio.net... > > Use the unisim library instead. > > > > library unisim; > > use unisim.vcomponents.all; > > > > the "virtex2.components" package is only > > there for compatability with old projects. > > > > - Ken > > > > > > van de Kerkhof wrote: > > > > > Hi, > > > > > > How do I get this library trough compilation. When I include this in my > vhdl > > > it gives an error with compilation. > > > If I leave it out synplify giveas an error with synthesis. And I don't > like > > > to manual add this to the vhdl every thime. > > > > > > Bram > > > > > > > > > >Article: 73679
Brad Smallridge a écrit: > In this case my situation is reversed. I have an out pin (it's the > Write*/Read SRAM line) and want to read it internally (one use would be to > control the tristate data outputs). As has already been told, if you use an inout port you will read the pad signal, thus adding output and input delays. You can use a buffer port instead of inout although this is quite a pain, or use an internal signal that you assign to your port: port ( ... sram_rw_b : out std_logic; -- the output port ... ); ... signal i_sram_rw_b : std_logic; -- the internal signal ... sram_rw_b <= i_sram_rw_b; -- the connection between the two of them ... -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 73680
>The limitation is if ... >* The VCCO supply ramps faster than the minimum data sheet specification >(Tcco) >and >* The VCCO supply does not have excess current capacity I'm missing something. How can it not have "excess current capacity" if it's ramping up too fast? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 73681
Hal Murray wrote: >>The limitation is if ... >>* The VCCO supply ramps faster than the minimum data sheet specification >>(Tcco) >>and >>* The VCCO supply does not have excess current capacity > > > I'm missing something. How can it not have "excess current > capacity" if it's ramping up too fast? I think he meant 'excess' as in 'spare' - sounds a great little problem they stumbled onto, where too fast a ramp triggers what seems close to a 'latch-up reflex' in the ESD regions. From Steve's description, if you have spare capacity, the chip will come up, but "but may still draw [extra?] current." -jgArticle: 73682
hengyew@gmail.com (david kong) wrote in message news:<f49c9766.0409271742.48293196@posting.google.com>... > I need help on Serpent implementation. It has a very large > transformation table which i need to optimize. could anyone help?? The > transformation table is basically a series of 3 input or 7 input > XOR...please help. There was a paper on this years FPL conference, session SPC8: "High Throughput Serpent Encryption Implementation" by Jesus Lazaro (University of the Basque Country), Armando Astarloa (University of the Basque Country), Jagoba Arias (University of the Basque Country), Unai Bidarte (University of the Basque Country), Carlos Cuadrado (University of the Basque Country) Kolja SulimmaArticle: 73683
Good morning every body, I'm working with an APEX 20K600E -2x and have a trouble with the embedded clocks PLLs, and I need help: With my 40 MHz system-clock I drive a Double Data Rate output, which is implemented by Synplify with a multiplexer, the clock beeing the selection pin: msb on the high level, lsb on the low level,. That is a usual, and works fine with an external global clock. In order to lower the tco time (horrible 9ns!), I tried to use the embedded PLLs to create an internal clock with an advanced phase, and then Quartus refuses to connect the Clock to the multiplexer selection pin: "Error: ClockLock pll ...... must drive only a pin or clock port." Is there any solution to implement a Double Data Rate output with a PLL generated clock?? Thank you in advance, Pierre-LouisArticle: 73684
Thanks for your help Matt.
I had tried using a char pointer as you suggested but the values I want
to write out are 32 bit integers, when I use a char pointer the correct
value is not written to SRAM. I have shown a section from the terminal
window below that shows this. Have I misinterpreted your suggestion for
using a char pointer or can you see a mistake I'm making.
>>
Mem[80F0007E]=126
Mem[80F0007F]=127
*** Error @ Mem[80F00080]=-128 Expected=128***
*** Error @ Mem[80F00081]=-127 Expected=129***
>>
If I use a pointer but set the addresses manually as below it works. I
set the value of i to a large integer value and then increment it for
each location but set the address directly in the code.
>>
i=268435456;
sram_addr_data=(int *) 0x80F00000;
*sram_addr_data = i;
i++;
sram_addr_data=(int *) 0x80F00001;
*sram_addr_data = i;
i++;
sram_addr_data=(int *) 0x80F00002;
*sram_addr_data = i;
i++;
sram_addr_data=(int *) 0x80F00003;
*sram_addr_data = i;
i++;
sram_addr_data=(int *) 0x80F00000;
mem_fill = *sram_addr_data;
xil_printf("\n\rMem[%x]=%d",(int *) sram_addr_data, mem_fill);
sram_addr_data=(int *) 0x80F00001;
mem_fill = *sram_addr_data;
xil_printf("\n\rMem[%x]=%d",(int *) sram_addr_data, mem_fill);
sram_addr_data=(int *) 0x80F00002;
mem_fill = *sram_addr_data;
xil_printf("\n\rMem[%x]=%d",(int *) sram_addr_data, mem_fill);
sram_addr_data=(int *) 0x80F00003;
mem_fill = *sram_addr_data;
xil_printf("\n\rMem[%x]=%d",(int *) sram_addr_data, mem_fill);
>>
This code results in the correct display in the terminal window but if I
try to put this in a loop to do it automatically how do I get the
pointer address to increment the way I need.
The SRAM device I am connecting to has a 19 bit address bus and a 32 bit
data bus. Am I right in thinking I should have 2^19 i.e. 524288
addresses each capable of holding 4 bytes therefore 2097152 bytes. This
corresponds to the documentation which says the device is 2M. Using the
code in my origibal post I am only getting access to a quarter of this.
Again thanks for your assitance, it is much appreciated.
Matthew Ouellette wrote:
> Ben,
>
> Since you are pointing to a 32-bit value (int), incrementing a pointer
> to this a value of this type will add the sizeof(int) to the address.
> Since MicroBlaze addresses are on byte boundaries, the address will be
> incremented by 4 (32 bits = 4 bytes).
>
> To increase your address by 1 byte, change the type of the variable you
> are pointing to to a char, which has sizeof(char) = 1 byte.
>
> Matt
>
Article: 73685
Hiya,
> I'm working on a quadrature decoder to interface with a rotation
> sensor. My thought was to have an asynchronous process that operates
> on the A and B signals, and then have the 'state' variable synchronous
> with the clock in a seperate process. The following vhdl works as
> expected in one simulation tool, but produces garbage when I use
> Quartus.
>
> begin
> process(A_in, B_in)
> begin
> state(3) <= state(1);
> state(2) <= state(0);
> state(1) <= A_in;
> state(0) <= B_in;
> end process;
> state_out <= state;
> direction <= ( (not state(3)) and (not state(0)) ) or ( state(3) and
> state(0)) ;
> end a;
>
> I expect that 'state' will always be of the form XXYY where XX is the
> old state, and YY is the current state of the inputs A and B (for
> example, 0001, 0111, 1110 etc). With one simulation tool I have, it
> works exactly as expected. With Quartus, the 'state' variable is
> always 0000, 0101, 1111, or 1010.
>
> Is there something wrong with the way I'm trying to implement this?
> Any suggestions on a better way?
The way you have written this code will make sure that Modelsim only
'schedules' the process if A_in or B_in changes. In a synthesized design, a
process is always dependant on all its inputs, so also its internal state -
er - register (which you don't have here).
If you synthesize this with Quartus (or any synthesis tool for that matter)
you will get warnings that state(1) and state(0) should also be on the
sensitivity list. The synthesis tool will subsequently simply generate a
wire between state(1) and state(3) and one between state(0) and state(2)
What you should do here is work synchronously, something like
process(clk)
signal tA, tB : std_logic;
begin
if rising_edge(clk) then
if (A_in /= tA) or (B_in /= tb) then
tA <= A_in;
tB <= B_in;
state(3) <= state(1);
state(2) <= state(0);
state(1) <= A_in;
state(0) <= B_in;
end if;
end if;
end process;
state_out <= state;
direction <= ( (not state(3)) and (not state(0)) ) or ( state(3) and
state(0)) ;
Even though I hate using the /= operator on a std_logic.
Best regards,
Ben
Article: 73686Hi Dominik, Dominik Gawlowski wrote: > HI > > I would like to confirm that my flow is correct. > I am checking the Power consumption of some final state machines. > The begining is the kiss file with the state machine, next I am encoding > and synthetizing it with SIS (berkeley university product) tool. After > that I am receiving the blif file. > Using our own tool I am converting this blif to edif which is full > yrecognizable by the ISE tool. > I am making mapping of this edif, generating testbench > simulating it with modelsim and when I hav .vcd file from model sim I am > using the xpower tool. > The results for this files are mostly resonable or inaccurate. > > When I checked the same flow with our own tool most of the results is > accurate and only some of them is inaccurate. > > Do you when can be the problem?? You will get a more accurate result if you run PAR on the design after MAP. Let me know if things improve when you do that. Regards, Brendan > > If my explanation is not full just let me know, then I will highlight > the points which are not clear. > > thank you in advance > > regrads > > Dominik Gawlowski > > Brendan Cullen wrote: > > Hi Mukesh, > > > > Mukesh wrote: > > > > > >>Before using xpower for my design, I decide to check for a simple > >>design of fibonacci series. I am facing following issues: > >> > >>I am running xpower with vcd generated with post par simulation and > >>during parsing I encounter the following warnings: > >> > >>WARNING:Power:91 - Can't change frequency of net CLK_BUFGP/IBUFG to > >>741.84Mhz. > >>WARNING:Power:91 - Can't change frequency of net CLK_BUFGP to > >>741.84Mhz. > >>WARNING:Power:91 - Can't change frequency of net CLK_BUFGP/IBUFG to > >>741.84Mhz. > >>WARNING:Power:91 - Can't change frequency of net CLK_BUFGP to > >>741.84Mhz. > >>... > >> > >>The frequency for signals in data view shows some values inthe range > >>of 2-9% in all cases except CLK_BUFGP/IBUFGP and CLK_BUFGP.. Any > >>attempts to change this value results in power:91 warnings as above. > >> > >>The confidence level shows Accurate. I am confused as the report shows > >>zero power for clock/ logic nets and still the confidence level is > >>accurate. > >>The report summary is : > >> > >>Total estimated power consumption: 439 > >>Peak Power consumption: 1081711 > >> --- > >> Vccint 1.50V: 65 98 > >> Vccaux 3.30V: 100 330 > >> Vcco33 3.30V: 3 11 > >> --- > >> Clocks: 0 0 > >> Inputs: 0 0 > >> Logic: 0 0 > >> Outputs: > >> Vcco33 2 8 > >> Signals: 0 0 > >> --- > >> Quiescent Vccint 1.50V: 65 98 > >> Quiescent Vccaux 3.30V: 100 330 > >> Quiescent Vcco33 3.30V: 1 3 > >> > >>Whats going wrong here? Anybody encountered similar problems? > >>Feedback/ help from Xilinx folks please. > >> > >>-- > >>Mukesh > > > > > > This does indeed look similar to another problem which we've been working > > on. We have a fix for that problem (the one we've been working on) and > > the fix will be available in the next service pack - 6.3.01i - which > > should be available to you next week. However, you might be experiencing > > a diferent symptiom. One option would be for you to zip up the NCD & VCD > > file and send them to us ? Or are they huge ? The other option is for > > you to try the service pack next week. Note - in order for you to use > > 6.3.01i you'll need to have the underlying 6.3i. (From your other e-mail > > to the newsgroup it appears you are using 6.2.03i.) > > > > Brendan > > > >Article: 73687
Hi thank you for your response I have a following flow in ISE software: ngdbuild -intstyle ise -dd _ngo -i -p xc2v1000-fg256-4 $EDF data.ngd netgen -intstyle ise -tb -rpw 100 -tpw 0 -ar Structure -ti UUT -xon true -w -ofmt vhdl -sim data.ngd data_translate.vhd map -intstyle ise -p xc2v1000-fg256-4 -cm area -pr b -u -k 4 -c 100 -tx off -o data_map.ncd data.ngd data.pcf par -w -intstyle ise -ol std -t 1 data_map.ncd data.ncd data.pcf trce -intstyle ise -e 3 -l 3 -xml data data.ncd -o data.twr data.pcf netgen -intstyle ise -s 4 -pcf data.pcf -ngm data_map.ngm -tb -rpw 100 -tpw 0 -ar Structure -ti UUT -xon true -w -ofmt vhdl -sim data.ncd data_timesim.vhd $EDF is a variable which is calling my edif file which is created from kiss. As you can see, the mapping is made before PAR, And the strangest think is that if I am using our tool to make blif and our tool to make edif, almost all results are accurate or reasonable. When I am using SIS (berkeley)tool to make blif and our tool to make edif, then most of the results are inaccurate or reasonable, which means that when I am trying to take values of the power I have always the same result. The second question I have is about the 1-hot binary gray and jedi encoding. I have tried to use xst tool to encode the FSM converted from Kiss format to verilog, but I was unsuccessful. Do you have any idea, how the flow should looks like?? Thank you in advance regards Dominik Brendan Cullen wrote: > Hi Dominik, > > Dominik Gawlowski wrote: > > >>HI >> >>I would like to confirm that my flow is correct. >>I am checking the Power consumption of some final state machines. >>The begining is the kiss file with the state machine, next I am encoding >>and synthetizing it with SIS (berkeley university product) tool. After >>that I am receiving the blif file. >>Using our own tool I am converting this blif to edif which is full >>yrecognizable by the ISE tool. >>I am making mapping of this edif, generating testbench >>simulating it with modelsim and when I hav .vcd file from model sim I am >> using the xpower tool. >>The results for this files are mostly resonable or inaccurate. >> >>When I checked the same flow with our own tool most of the results is >>accurate and only some of them is inaccurate. >> >>Do you when can be the problem?? > > > You will get a more accurate result if you run PAR on the design after MAP. > Let me know if things improve when you do that. > > Regards, > > Brendan > > >>If my explanation is not full just let me know, then I will highlight >>the points which are not clear. >> >>thank you in advance >> >>regrads >> >>Dominik Gawlowski >> >>Brendan Cullen wrote: >> >>>Hi Mukesh, >>> >>>Mukesh wrote: >>> >>> >>> >>>>Before using xpower for my design, I decide to check for a simple >>>>design of fibonacci series. I am facing following issues: >>>> >>>>I am running xpower with vcd generated with post par simulation and >>>>during parsing I encounter the following warnings: >>>> >>>>WARNING:Power:91 - Can't change frequency of net CLK_BUFGP/IBUFG to >>>>741.84Mhz. >>>>WARNING:Power:91 - Can't change frequency of net CLK_BUFGP to >>>>741.84Mhz. >>>>WARNING:Power:91 - Can't change frequency of net CLK_BUFGP/IBUFG to >>>>741.84Mhz. >>>>WARNING:Power:91 - Can't change frequency of net CLK_BUFGP to >>>>741.84Mhz. >>>>... >>>> >>>>The frequency for signals in data view shows some values inthe range >>>>of 2-9% in all cases except CLK_BUFGP/IBUFGP and CLK_BUFGP.. Any >>>>attempts to change this value results in power:91 warnings as above. >>>> >>>>The confidence level shows Accurate. I am confused as the report shows >>>>zero power for clock/ logic nets and still the confidence level is >>>>accurate. >>>>The report summary is : >>>> >>>>Total estimated power consumption: 439 >>>>Peak Power consumption: 1081711 >>>> --- >>>> Vccint 1.50V: 65 98 >>>> Vccaux 3.30V: 100 330 >>>> Vcco33 3.30V: 3 11 >>>> --- >>>> Clocks: 0 0 >>>> Inputs: 0 0 >>>> Logic: 0 0 >>>> Outputs: >>>> Vcco33 2 8 >>>> Signals: 0 0 >>>> --- >>>> Quiescent Vccint 1.50V: 65 98 >>>> Quiescent Vccaux 3.30V: 100 330 >>>> Quiescent Vcco33 3.30V: 1 3 >>>> >>>>Whats going wrong here? Anybody encountered similar problems? >>>>Feedback/ help from Xilinx folks please. >>>> >>>>-- >>>>Mukesh >>> >>> >>>This does indeed look similar to another problem which we've been working >>>on. We have a fix for that problem (the one we've been working on) and >>>the fix will be available in the next service pack - 6.3.01i - which >>>should be available to you next week. However, you might be experiencing >>>a diferent symptiom. One option would be for you to zip up the NCD & VCD >>>file and send them to us ? Or are they huge ? The other option is for >>>you to try the service pack next week. Note - in order for you to use >>>6.3.01i you'll need to have the underlying 6.3i. (From your other e-mail >>>to the newsgroup it appears you are using 6.2.03i.) >>> >>>Brendan >>> >>> > >Article: 73688
Steven Knapp wrote: > > The limitation is if ... > > * The VCCO supply ramps faster than the minimum > data sheet specification (Tcco) > One question: is this strictly a power-up issue, or can it be triggered during operation? In particular, since the ramp spec. is worse for the leaded packages, could a large transient on the VCCO supply cause the same problem? e.g., if you configure a PQ208 with many parallel DCI terminations, at the end of configuration the VCCO supply will jump instantly from quiescent to full power ( maybe ~3 amps max. for a PQ208, but by that point you'd have heatsinking problems ) BrianArticle: 73689
Hello I need information about creating a fast adder (n = n + 1) and a fast equal (a = b). (both 28 bit signals) I'm going to create a fast binary counter in a FPGA Spartan II Would it be faster to create several 4 bit LFSR and a converter to binary than a normal binary counter? I need the binary output because it's a timestamp I need to be able to reset the counter to zero when it reaches a certain number. (reset every second by a pulse per second signal or if the reference signal is missing when the counter is equal to the measured frequency of the clock) The goal is to use a clock frequency on 100MHz + 25% margin. Thanks RuneArticle: 73690
Rune Christensen wrote: > Hello > > I need information about creating a fast adder (n = n + 1) and a fast equal > (a = b). (both 28 bit signals) > > I'm going to create a fast binary counter in a FPGA Spartan II > > Would it be faster to create several 4 bit LFSR and a converter to binary > than a normal binary counter? > > I need the binary output because it's a timestamp > > I need to be able to reset the counter to zero when it reaches a certain > number. (reset every second by a pulse per second signal or if the reference > signal is missing when the counter is equal to the measured frequency of the > clock) > > The goal is to use a clock frequency on 100MHz + 25% margin. You can use a 28 bit binary up counter and comparator or also recommended is a 28 bit downcounter which issues a carry when it has reached zero. In this case the reset signal loads a preset value. The timestamp is a subtraction then, assumedly in software. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 73691
>
> I searched and searched AVNET for a AvBus cable, but
> couldn't find any. So how exactly are users supposed
> to use those expansion modules, if Avnet doesn't
> even provide a cable?!?
>
In normal use, you'd design your module with the mating
connectors to stack right on top of the evaluation board,
which is how the Avnet daughter cards work.
However, they do make two AVbus "breakout" boards, try an
Avnet parts search for:
ADS-AVBUS-DAU ( breakout board )
ADS-AVBUS-ADAPT ( adapter board, unpopulated )
177983-6 ( mating AMP connector, 8 mm stack height )
Or, from Avnet's website, on the "evaluation kits" page:
"
AvBus Adapter
This printed circuit board provides adaptability to both male and
female AvBus connectors for interface cable fabrication or vertical
height extension. The board is unpopulated.
AvBus Breakout Module
This daughtercard provides a convenient method of interfacing
external signals to standard AvBus connectors on development and
evaluation boards. The board features two male and two female AvBus
connectors which breakout to six MICTOR connectors and four 50-pin
(0.1") headers. Power indicator LEDs are provided for +5 and +3.3 VDC
"
Brian
Article: 73692Rune Christensen <rune.christensen@adslhome.dk> wrote: : Hello : I need information about creating a fast adder (n = n + 1) and a fast equal : (a = b). (both 28 bit signals) : I'm going to create a fast binary counter in a FPGA Spartan II : Would it be faster to create several 4 bit LFSR and a converter to binary : than a normal binary counter? : I need the binary output because it's a timestamp : I need to be able to reset the counter to zero when it reaches a certain : number. (reset every second by a pulse per second signal or if the reference : signal is missing when the counter is equal to the measured frequency of the : clock) : The goal is to use a clock frequency on 100MHz + 25% margin. It depends on the FPGA family and the toolchain you use and if "b" is a constant or a input. For most families, you requirements should be easily fullfilled. As first test, write some HDL code, synthesize and place the design eventually giving constraints describing your requirements and look at the reports. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 73693
Yes - use the locked signal as an asynchronous reset. That will keep your logic in a known state until the frequency is stable. Another thought is to latch the falling edge transitions in an error flag so that if your DCM goes unlocked when you don't expect it to, you can correct / cleanup with software. Chris "Dave" <gretzteam@hotmail.com> wrote in message news:<urSdnShroJyVN8XcRVn-hA@comcast.com>... > Hi, > I have a design (basically a FIR filter) that is clocked by the output of a > DCM. I understand that I should not do anything before the locked signal > goes high. However, what is the right way to do this? > > I also have a small state machine that resets the FIR filter, sets some > stuff, and then enable everything. The state machine is also clocked by the > output of the DCM (it is the only clock of the design). Should I use the > locked signal as an asynchronous reset of the state machine so that nothing > happens before locked goes high? I wonder if this is what people do, or if > there is an easier way. > Thanks, > DavidArticle: 73694
I agree with this response, but I think you missed a begin-end pair.
You only want to toggle the LED when the counter wraps. See below.
Cheers,
Chris
always @(posedge clk50) //Trigger on 50MHz clock
begin
if (c == 50000000) //Convert 50MHz Clock to 1Hz <= 0; led_o <= 1;
begin
c <= 0; // reset counter
led <= ~led; // toggle led (when ctr wraps)
end
else
c <= c + 1; //Step up c +1
end
ben@ben.com (Ben Jackson) wrote in message news:<3X%5d.270176$Fg5.97056@attbi_s53>...
> In article <ee89141.-1@webx.sUN8CHnE>, Weizbox <> wrote:
> >
> >module pulse(led_o, clk50);
> >
> >input clk50;
> >output led_o;
> > reg [15:0] c;
>
> make that big enough to hold 50000000, at least 26 bits.
>
> make an output register
>
> reg led;
> assign led_o = led;
>
> >always @(posedge clk50) //Trigger on 50MHz clock
> > begin
> > if (c == 50000000) //Convert 50MHz Clock to 1Hz <= 0; led_o <= 1;
> c <= 0; // reset counter
> led <= ~led; // toggle led
> >
> >else
> > c <= c + 1; //Step up c +1
> > end
> >
> >endmodule
>
> Offhand I think that will do what you want. With clock driven logic
> you can't just 'wait', you have to maintain some sort of state (in this
> case just whether the LED is off or on) and come back to it at a later
> clock edge, based on some counter or signal.
Article: 73695
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> skrev i en meddelelse
news:cjbm19$n8j$1@lnx107.hrz.tu-darmstadt.de...
> Rune Christensen <rune.christensen@adslhome.dk> wrote:
> : Hello
>
> : I need information about creating a fast adder (n = n + 1) and a fast
> equal
> : (a = b). (both 28 bit signals)
>
> : I'm going to create a fast binary counter in a FPGA Spartan II
>
> : Would it be faster to create several 4 bit LFSR and a converter to
> binary
> : than a normal binary counter?
>
> : I need the binary output because it's a timestamp
>
> : I need to be able to reset the counter to zero when it reaches a certain
> : number. (reset every second by a pulse per second signal or if the
> reference
> : signal is missing when the counter is equal to the measured frequency of
> the
> : clock)
>
> : The goal is to use a clock frequency on 100MHz + 25% margin.
>
> It depends on the FPGA family and the toolchain you use and if "b" is a
> constant or a input.
>
> For most families, you requirements should be easily fullfilled. As first
> test, write some HDL code, synthesize and place the design eventually
> giving
> constraints describing your requirements and look at the reports.
>
> Bye
>
> --
> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
I have already done that but my goal is 8 ns and a simple implementation
gives
Slack: -1.380ns (requirement - (data path - clock path skew
+ uncertainty))
Source: cnt_0 (FF)
Destination: cnt_3 (FF)
Requirement: 8.000ns
Data Path Delay: 9.373ns (Levels of Logic = 9)
Clock Path Skew: -0.007ns
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 8.000ns
Clock Uncertainty: 0.000ns
-- clock counter
counter : process(clk, cnt, freq_meas)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
cnt <= X"000_0000";
else
cnt <= cnt + 1;
end if;
end if;
-- local mode when reference is missing
if (cnt = freq_meas and localmode = '1') then
overflow <= '1';
else
overflow <= '0';
end if;
end process counter;
reset <= ref_edge or overflow;
The minimum slack I have had is aprox. -0.500 ns but no matter how I change
the circuit I can not get the wanted 8 ns
I'm using Xilinx Project Navigator and the FPGA is a SpartanII
XC2S200-5pq208
Cheers
Rune
Article: 73696Can you tell me which version of Synplify you are using? 7.7 is the current release. Make sure you are not including a unisim.vhd file from anywhere in your project. Synplify will automatically use a pre-compiled version with some mapping attributes. If you include the unisim simulation library, then those attributes will be missing. - Ken van de Kerkhof wrote: > Hi, > > The solution of ken doesn't work i still het the same error. > > Error Code <xcmap.c:3416 Invalid LUT instantiation. Have you included the > virtex.v(hd) file, and an INIT value?> > @E:Internal Error > > The lut has an init value. > > When i add the virtex2 library this is gone, but with vcomponents it is > still there. > > Bram > > > > "Symon" <symon_brewer@hotmail.com> wrote in message > news:2rqv0sF1bi104U1@uni-berlin.de... > >>...or, if you're using ModelSIM (say), you can map the virtex2 library to >>the UNISIM one. But Ken's solution is better... >>Cheers, Syms. >>"Ken McElvain" <ken@synplicity.com> wrote in message >>news:GwV5d.11117$NC6.495@newsread1.mlpsca01.us.to.verio.net... >> >>>Use the unisim library instead. >>> >>>library unisim; >>>use unisim.vcomponents.all; >>> >>>the "virtex2.components" package is only >>>there for compatability with old projects. >>> >>>- Ken >>> >>> >>>van de Kerkhof wrote: >>> >>> >>>>Hi, >>>> >>>>How do I get this library trough compilation. When I include this in > > my > >>vhdl >> >>>>it gives an error with compilation. >>>>If I leave it out synplify giveas an error with synthesis. And I don't >> >>like >> >>>>to manual add this to the vhdl every thime. >>>> >>>>Bram >>>> >>>> >>> >> > >Article: 73697
Hi And where can I find the download link for the Verilog model? Because I can nowhere on the project site of aeMB! cheers Roman "Antti Lukats" <antti@case2000.com> wrote in message news:cjbrus$csk$02$1@news.t-online.com... > Hi All > > finally today the project maintainer at opencores uploaded the verilog > design files for MicroBlaze compliant IP-Core. Download is available at > opencores.com - as project aeMB !! > > for PicoBlaze there are 2 different open source 3rd party implementations > known, i wonder when first NIOS-II open source IP-core will be available > :) > > > Antti > xilinx.openchip.org > > > >Article: 73698
"Rune Christensen" <rune.christensen@adslhome.dk> wrote in message news:41594f1e$0$238$edfadb0f@dread12.news.tele.dk... > Hello > > I need information about creating a fast adder (n = n + 1) and a fast equal > (a = b). (both 28 bit signals) > > I'm going to create a fast binary counter in a FPGA Spartan II > > Would it be faster to create several 4 bit LFSR and a converter to binary > than a normal binary counter? > > I need the binary output because it's a timestamp > > I need to be able to reset the counter to zero when it reaches a certain > number. (reset every second by a pulse per second signal or if the reference > signal is missing when the counter is equal to the measured frequency of the > clock) > > The goal is to use a clock frequency on 100MHz + 25% margin. > > Thanks > Rune If you don't like the idea of a down-counter where the carry out loads your count value... If you don't want to offset your counter by 2^n-MaxCount... If you want everything, consider pipelining. It uses the same number of resources as the "reset on equal" because the register packed with the equal signal would go unused: pipeline the terminal count. By determining the terminal count by registering the comparison to the terminal count minus 1, you get the zero-offset and much greater than 100MHz timing.Article: 73699
In article <f49c9766.0409271742.48293196@posting.google.com>, david kong <hengyew@gmail.com> wrote: >I need help on Serpent implementation. It has a very large >transformation table which i need to optimize. could anyone help?? The >transformation table is basically a series of 3 input or 7 input >XOR...please help. Serpent is a piece of cake. Implement 8 rounds with the 8 different S-boxes, with the s-boxes will be very 4-lut favorable. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.edu
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