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Roman Leitner <roman.leitner@cern.ch> writes: > Hello , > got a problem with the SOPC-Builder from Altera. > I made a new Project in Quartus2, and added a MEGAFUNCTION from SOPC. > > In the SOPC i added the NIOS2 Core, OnChip Memory, Jtag UART and > Serial UART. > When I try to generate the code, an error occurs. > here is the whole logfile: > > > Altera SOPC Builder Version 4.10 Build 208 > Copyright (c) 1999-2004 Altera Corporation. All rights reserved. > > # 2004.09.22 18:17:35 (*) mk_custom_sdk starting > # 2004.09.22 18:17:35 (*) Reading project > C:/test/NIOS/templates_microtronix/standard_32_nios/ref_32_system.ptf. > # 2004.09.22 18:17:35 (*) Finding all CPUs > # 2004.09.22 18:17:35 (*) Finding all available components > > no install.ptf file found at > c:/altera/quartus41/sopc_builder/bin/europa/europa_utils.pm line 1700. > Error in processing. System NOT successfully generated. Funny, I got the exact samme message, but running a Makefile which worked on a different machine. This is QuartusII 4.0 SP1 with NIOS 3.2. # 2004.09.24 02:05:58 (*) mk_custom_sdk starting # 2004.09.24 02:05:58 (*) Reading project ./nios32.ptf. # 2004.09.24 02:05:58 (*) Finding all CPUs # 2004.09.24 02:05:58 (*) Finding all available components no install.ptf file found at /usr/local/altera/quartus/sopc_builder/bin/europa/europa_utils.pm line 1700. make: *** [nios32.v] Error 2 Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 73601
Hi All, I am trying to use the SDR SDRAM controller that is comming with the NIOS II development package. In the simulation it looks like this core supports only 2 words bursts. I couldn't find anything in the documentations. Am I correct? If this core supports bigger bursts then 2 words, any ideas what am I doing wrong? Thank you all ZoharArticle: 73602
If you order the ML310 board, it comes with both Linux and Vxworks running. Works quite well. Just plug in and go. Boots up to rs232 console (hyperterm works) and then select among several boot options including Linux and Vxworks. Then you can telnet to the board through the Ethernet. -Tom "Jonas Floden" <jontef@home.se> wrote in message news:4153EE71.2090203@home.se... > Hi all, > > We are working with a Memec development board with a Xilinx Virtex-II > Pro FPGA. The idea was to run VxWorks on this board. But we seem to have > a bit of problems. And it seems very hard to find resources on the > internet that uses VxWorks with Xilinx FPGA's. > > So I was hoping that anyone here could suggest some places to look out. > > Also right now we do not have the com module, so no ethernet and no > flash. But we load the SDRAM with the vxworks executable and then jump > to that address. Is that a good way, or do you have to go through some > ROM-loader? > > All help would be greatly appreciated! > > With regards > Jonas Floden >Article: 73603
Weizbox, They seem to number the board connectors in a funny way. On their connectors, pin 1 of the male does not connect to their pin 1 of the female. Get the pinouts and schematics for both boards so you can tell what is really happening. Cheers, Jim -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > I looked at the sheet and now i belive it wants a signal.. i think. The confusing part is when I look at the datasheet for the AD7823 and the AIO1, the seem to do some weird things. The CONVST label on the ADC changes over to ADCLK when it gets to the pinout, as well SCLK on the ADC changes to CONVST? Not sure why.... may take a few trial and errors to figure out what pins do what unfortunetly, or mabye Im reading it wrong...Article: 73604
On Fri, 2004-09-24 at 13:43 -0700, Weizbox wrote: > Im reading up on some of it now and was getting confused.. does teh ADC output a clock or do you give it a clock to use? The clock is an input into the ADC. See page 9 of the Analog Devices data sheet. And to your earlier question to the type of serial... it is a synchronous serial protocol which means a separate clock. You often seen it called by the name SPI, Microwire, etc some of which are trademarked names from various companies but all do the same. As for a website to get you started, Xilinx has an application note of SPI protocol. I also like the website fpga4fun.com which is informative for learning but the code examples are not very complete. They do have a simple serial interface example though.Article: 73605
On Fri, 2004-09-24 at 14:33 -0700, Weizbox wrote: > I looked at the sheet and now i belive it wants a signal.. i think. The confusing part is when I look at the datasheet for the AD7823 and the AIO1, the seem to do some weird things. The CONVST label on the ADC changes over to ADCLK when it gets to the pinout, as well SCLK on the ADC changes to CONVST? Not sure why.... may take a few trial and errors to figure out what pins do what unfortunetly, or mabye Im reading it wrong... You may want to trace the pins with a multimeter. I had another Digilint board before and while they are affordable, the documentation is sometimes full of errors.Article: 73606
rickman <spamgoeshere4@yahoo.com> wrote in message news:<414F9E50.8B315F7B@yahoo.com>... > sebastian wrote: > > > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<41488BBA.4B570E72@yahoo.com>... > > > > > When it comes to memory, it can be hard to infer it in a way that is > > > compatible with multiple hardware platforms. > > > > well i hope some time soon they make it somehow "standard", cause > > right now altera just lost (again! cause it's the second time in few > > months i see it happening) against xilinx, cause the boss said it was > > already too much trouble having generates for ASIC and for FPGA, to > > have another one for another family we were just evaluating (we'd need > > to modify lots of files). > > There's your problem. Your designs should be done in a modular fashion > so that there are common files for memory componets. I have a single > file for memory blocks with the required code to infer or instantiate > the various memory styles. I select the chip family and select infer > vs. instantiate. When I need to add something, I only have one file to > modify. Further, additions should not affect any established code, so I > don't need to do regression tests. > well, i was talking about ROMs, and we've plenty of them holding microcode and LUTs, etc. The thing is that we had that for ROMs (a generic ROM), it is a vhdl file that according to a parameter file, will generate the ROM with a function. It's the same than a RAM but where a function loads the constants, something like: constant tRAM : MyROM := InitRAM(parameterfile); To infer ROMs in the way Altera we'd need to create a separate module for each instantiation of our generic ROM cause Altera uses a "case" statement to infer a ROM, and there's no way (well, maybe a generate?? but i just thought that while writing, i'd need to think thru) to make them "generic", we'd need a script to generate them. > > > And also because we werent seeing any gains > > in LUTs (the same design was using more LUT4 in altera than on > > xilinx), nor on speed, Quartus II 3.0 was a lot slower than ISE 5.2. > > Though Quartus was meeting timing with more slack, i guess ISE 6.3 and > > Quartus 4.0 are even better. > > I would not expect any gains in LUTs going from Xilinx to Altera. As > you found, often the Xilinx design can use less. But that itself is not > the issue since the cost per LUT is not the same. > > I am not sure what you mean about Quartus being slower. Are you > referring to the run time to compile a design? > yes, it is slower, though like i said it meets timing better, so the router must be better than ISE 5.2 > > > guys! it's time you start doing "standard" things so that code is > > portable *without* modifications (provided that FPGA families have the > > same functionality, dual ported RAM, etc. of course!) > > Many forms of RAM can port between FPGA families. I suggest that you > explore the common ground and try to use compatible memory styles. > Excluding a vendor based on your coding style keeps you from getting the > best price from the remaining vendor. > well, that wasnt my decision :) seems like my boss dont like "complicated" stuff, so if porting is not almost instantly, and requires scripts or things out of VHDL itself, he doesnt like it for example, ISE 5.2 cant create large ROMs from VHDL, so we need to use CoreGen...we already got ISE 6.something so we dont need it anymore. > The design I am working on now uses compatible memory even though the > Altera ACEX part is targeted. The only thing I can't do in a Xilinx > Spartan 3 is the async read of memory. In the Spartan 3 (and most of > their other chips) the read requires one clock cycle. That requires > changes in other parts of my architecture. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73607
On Wed, 22 Sep 2004 11:14:39 +0200, Leroy Tanner wrote: > For a while I have been confronted with the following task which I find > quite challenging but unfortuantely didn't manage to solve it, yet. > What I want to do is to use 2-4 FPGAs (Xilinx Virtex 2 Pro) together on one > printed circuit board (PCB). They are used to process a large amount of > incoming serial data (data rates of several GHz's). My idea is to handle > that data parallel by the 2-4 FPGAs. But now there arises the problem how to > adequately split the data and how to synchronize the FPGAs among one > another, in particular? There are two ways to approach this problem: (1) have each FPGA perform a part of the process on the entire data stream or (2) have each FPGA perform the entire process on part of the data stream. We once implemented (2) for a bandwidth expander where each chip did the complete process (one clock cycle Huffman decoding, translation of the code to a value, then arithmetic processing) for a portion of the incoming data stream. Each chip was provided a chunk of the incoming data (e.g., in a two-chip system, chip one processed chunks 1,3,5,... of the data and chip two was processed chunks 2,4,6,... of the data). We actually used two on the board because of I/O bandwidth limitations, but the chip was designed to allow for 1,2,4,or 8 chip operation. -=Dave=-Article: 73608
Have you looked at the development boards at www.digilent.com Xilinx only, but the lowest priced ones I've seen anywhere on the web...Article: 73609
k flash wrote: > I am looking for an LCD model which i can use as a test bench for my simulations. > Any ideas where i might be able to find one. You should have a look at the datasheet of the respective manufacturer. And be aware that the timing information may not be accurate. Meaning you should test it while developing an interface to it. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 73610
I' ve registered my account into xilinx form for downloading the spice models for rocket io etc etc that xilix give on the site. However these models are encrypted. How can i use them if they are encrypted. What else i need for using them? Can i use them in a spice3f5 or LTspice or Orcad environment? ThanksArticle: 73611
Hi, Its EDK 6.2.03i. I have only one .xmp file. I recreated the project ..and I guess that has fixed it ..not sure why. Regards, MadhuraArticle: 73612
Did you mean : http://www.digilentinc.com/ maxfoo wrote: > Have you looked at the development boards at www.digilent.com > > Xilinx only, but the lowest priced ones I've seen anywhere on the web... > > > > >Article: 73613
Hey all! I'me looking for a PCI card that would have an FPGA chip on it that i could re-program on the fly (without a power cycle). Nothing fancy, though it would be nice if i could program the FPGA and the board would handle all PCI, memory and other access for me. (meaning i only would have to program the FPGA). I want to be able from a custom software driver that i will make to re-program the fpga on the fly, and send data to be processed. Thanks a lot!Article: 73614
How do I take an exisiting FPGA design ( say a xilinx Spartan IIE or III, designed in vhdl, simulated in ModelSim and is presently running successfully in an FPGA ) and cost reduce it as an ASIC: 1. What type of quantities are needed to make ASIC viable 2. Please name a couple of ASIC houses that do this sort of think, especially for the entry level market 3, What will I need to do to the FPGA design to facilitate its conversion to ASIC? Thanks for bear with such a general question TLArticle: 73615
sebastian wrote: > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<414F9E50.8B315F7B@yahoo.com>... > > There's your problem. Your designs should be done in a modular fashion > > so that there are common files for memory componets. I have a single > > file for memory blocks with the required code to infer or instantiate > > the various memory styles. I select the chip family and select infer > > vs. instantiate. When I need to add something, I only have one file to > > modify. Further, additions should not affect any established code, so I > > don't need to do regression tests. > > > > well, i was talking about ROMs, and we've plenty of them holding > microcode and LUTs, etc. > The thing is that we had that for ROMs (a generic ROM), it is a vhdl > file that according to a parameter file, will generate the ROM with a > function. It's the same than a RAM but where a function loads the > constants, something like: > > constant tRAM : MyROM := InitRAM(parameterfile); > > To infer ROMs in the way Altera we'd need to create a separate module > for each instantiation of our generic ROM cause Altera uses a "case" > statement to infer a ROM, and there's no way (well, maybe a generate?? > but i just thought that while writing, i'd need to think thru) to make > them "generic", we'd need a script to generate them. I'm not sure I follow this, but in an FPGA a ROM is nothing but a RAM that is never written. You can infer them the same way as a RAM, just don't use a write signal and input data. They can be initialized in different ways. I find it most useful to init the data *after* compliation and routing of the design. Both Xilinx and Altera support this. > > I would not expect any gains in LUTs going from Xilinx to Altera. As > > you found, often the Xilinx design can use less. But that itself is not > > the issue since the cost per LUT is not the same. > > > > I am not sure what you mean about Quartus being slower. Are you > > referring to the run time to compile a design? > > > > yes, it is slower, though like i said it meets timing better, so the > router must be better than ISE 5.2 You have said the same thing as before. But I assume you mean it takes longer to run. Meeting timing is a function of the software as well as the chip. So it may be that your design fits an Altera part better. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73616
rickman wrote: (snip about ROMs in FPGA's) > I'm not sure I follow this, but in an FPGA a ROM is nothing but a RAM > that is never written. You can infer them the same way as a RAM, just > don't use a write signal and input data. They can be initialized in > different ways. I find it most useful to init the data *after* > compliation and routing of the design. Both Xilinx and Altera support > this. Quartus II for me, if I have a design with RAM in it, such as a FIFO has a warning that I haven't provided initialization data for the RAM. I believe it takes the old intel hex format, and maybe others. Are you using the BRAM's or LUT's for your ROM? -- glenArticle: 73617
Thank you for your reply. I read that the PROM used in my Spartan3 Board, a XCF02S is full 5V tolerant if supplied with 3.3V (as it is in the board). So in this case it's not strictly necessary to put the series resistors, is it? Another thing...can you tell me where can I found the schematic for the parallel cable III? Thanks a lot Guido news@sulimma.de (Kolja Sulimma) wrote in message news:<b890a7a.0409230701.11d30cf1@posting.google.com>... > This is easily possible. > There are schematics for the parallel cable III available on the net. > You should however additionally put resistors between the input and > output of each buffer to provide a hysteresis of a few hundred > millivolts. > Also, for spartan-3 you must make sure that your series resistors to > the fpga are large enough to limit the current to whatever it is the > datasheet says. > You can not simply supply the buffers with 2.5V because then you will > not be able to generate TTL levels for the PC. > > Because the original parallel cable III did only work with about 2/3 > of all PCs, > there are a couple of sites on the net that sell improved and less > expensive versions. > One that explicitely is Spartan-3 compatible is this one: > http://shop.trenz-electronic.de/catalog/product_info.php?products_id=46 > > Kolja SulimmaArticle: 73618
"Jon Beniston" <jon@beniston.com> wrote in message news:e87b9ce8.0409231030.326d0b2a@posting.google.com... > gvaglia@gmail.com (Guido) wrote in message > news:<44f5f440.0409230231.4e64da8c@posting.google.com>... >> Hi all! >> My Xilinx Parallel Cable IV was lost during a travel and it needs 5 >> weeks to receive another from Memec. > > You can order one from Xilinx's web site. They ship internationally. > They got me mine in a couple of days. > > Cheers, > JonB Xilinx's shipping is very good (who ever they use). Ordered on a tuesday night recieved the order on the thursday morning. Not bad from the US to Sydney, Australia. AlexArticle: 73619
"Ted Lechman" <eastwood132@yahoo.com> wrote in message news:<WZSdnQnBg8AjSsjcRVn-gQ@adelphia.com>... > How do I take an exisiting FPGA design ( say a xilinx Spartan IIE or III, > designed in vhdl, simulated in ModelSim and is presently running > successfully in an FPGA ) and cost reduce it as an ASIC: There are a couple of other options inbetween FPGA and standard-cell ASIC. Have a look at Altera's Hardcopy and Xilinx's EasyPath products. Then you have structured ASICs: http://www.chipx.com/ http://www.lightspeed.com/ http://www.amis.com/asics/structured_asics/ http://www.lsilogic.com/products/rapidchip_platform_asic/index.html > especially for the entry level market > 3, What will I need to do to the FPGA design to facilitate its conversion to > ASIC? It depends what FGPA specific features you use (special I/Os, DCMs, etc). The less the easier it will be. Cheers, JonArticle: 73620
"Ted Lechman" <eastwood132@yahoo.com> wrote in message news:<WZSdnQnBg8AjSsjcRVn-gQ@adelphia.com>... > How do I take an exisiting FPGA design ( say a xilinx Spartan IIE or III, > designed in vhdl, simulated in ModelSim and is presently running > successfully in an FPGA ) and cost reduce it as an ASIC: > 1. What type of quantities are needed to make ASIC viable > 2. Please name a couple of ASIC houses that do this sort of think, > especially for the entry level market > 3, What will I need to do to the FPGA design to facilitate its conversion to > ASIC? > > Thanks for bear with such a general question > TL Flextronics, AMI, google <fpga asic conversion> Better if project has been designed fior FPGA & ASIC in mind from start. FPGA to ASIC is easier as FPGAs are slower to start and may well pick up 2x or more speed in ASIC. ASIC to FPGA has only speed to lose. Also if you use any IP from FPGA such as BRAMs, multipliers, PLLs etc, the conversion will need all of these in equiv form as available IP. You can checkout foundries websites & download asic cell lib info to get an idea of whats available and see if you need to make your design comform some. regards johnjakson_usa_comArticle: 73621
Hi all, I am currently using the (gratis) Xilinx ISE 6.2i WebPack for Windows version for developing CPLD and FPGA designs for reasons that shall not be discussed right now ;) First thought was to play a little with the tools that come with it using some application notes code from Xilinx (namely from XAPP137). Well, that first attempt half-way failed due to the fact that I somehow seemed to be unable to restore the archived project that was contained in the xapp137.zip archive from within the Project Navigator. Is this functionality possibly only available in the paid-for version ? Thanks and regards, Christian BoehmeArticle: 73622
Antti Lukats <antti@case2000.com> wrote: : Quote from Xilinx Website (the best support web as many seem to claim!): : "Support for 3S1000 and 3S1500 devices is available in ISE WebPACK 6.3i only : when the product is downloaded and installed from the Web at : www.xilinx.com/ise/webpack6" : if you go to the link to download 6.3 you get what ? : guess: you land to 6.2 download pages!! : ISE 6.3 is available as ""free"" CD for 20 USD shipping, but as per quote : above if you dont download from the (dead) link you will not get 3S1000/1500 : support! So you have to pay 20 USD to get less than you could get for free : (if xilinx would fix the wrong link to the download) : So as the things stand today: since ISE 6.3 free webpack is no longer : available, not from web download not as CDROM (20USD shipping charges : apply). I dont mind the 20USD and I dont need the Webpack either, but I also : dont like people being fooled around with incorrect information. The 6.3 Webpack had problems and was withdrawn. Expect a corrected version soon. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 73623
Antti Lukats wrote: >>: So as the things stand today: since ISE 6.3 free webpack is no longer >>: available, not from web download not as CDROM (20USD shipping charges >>: apply). I dont mind the 20USD and I dont need the Webpack either, but I > > also > >>: dont like people being fooled around with incorrect information. >> >>The 6.3 Webpack had problems and was withdrawn. Expect a corrected version > > soon. > > thanks! > I wonder why that information is not available from Xilinx!! > Antti Because we would complain anyway ? ;-) But serious, it seems that they decided too late to put in the support for xc3s1000 & xc3s1500 into webpack, and if that is the case I can wait few days for this gift ;-)Article: 73624
I often get Xilinx error messages saying that I can't read a pin that is configured "out mode" (or something like that). Up to now, to get around the error, I have been mirroring such a pin with an internal register and reading the output of the register instead. Recently I find that making such a pin an inout instead of an out will also let it be read. That's reasonable but seems contrary to what I believe that an inout pin is a bidirectional pin. What is the best way to do this, as a matter of style? b r a d @ a i v i s i o n . c o m
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Compare FPGA features and resources
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