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Grzegorz Kasprowicz wrote: >>You have the required pullups and pulldowns ? >>1k up for TMS, TDI and TDO and 1k down for TCK. >>Plus there is whealth of pins that require a fixed connection. >>Documented in the *.RPT file as ASCII. >> >> > > Yes, i have all pullups and pulldowns, all signal except TDO look good, i > mean levels. > All grounds and supplies are also OK. > Anyway instead of solving problem, i will change logic family to MAX3000A, > which better suits my needs (3.3V) I also found in at least one case that re-soldering or re-heating the pins was of help in case of self soldered prototype. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 73326
Uwe Bonnes wrote: > Andre Bonin <Yoyoma_2@[at-]hotmail.com> wrote: > : Hello all, i'me doing a school project requiring Cyclone2 chips, but all > : the distributors I called (that allow single-order) have only the > : EP1C7's (Cyclone1's speed grade 7). And furthermore they sell it for > : around 300$ us (500 canadian). > > : Am i missing something? Altera says they cost under 3$ each. I concure > : that yes volume pricing etc, but from 3$ to 500$ seems a rather large > : increase. > > : I'me looking for the cheapest FPGA possible that will be easy to program > : on the fly and could multiply a 10x10 matrix. Our design does have some > : external ram and a PLD so System-On-Chip could be integrated into our > : pci board. > > Did you consider going with Spartan 3? At nuhorizons they start at 13$45 > with the XCF02 for 5$80. From what i hear, the xilinx devices are harder to integrate with the board. That's why w'ere gearing towards altera. Plus the school already has altera equipment. Unless xilinx wants to give me free spartans because i'me a starving student, then i'lle thank them in my term presentation :). > > Spartan 3 has embedded multipliers. > > ByeArticle: 73327
Andre Bonin <Yoyoma_2@[at-]hotmail.com> wrote: : Uwe Bonnes wrote: : > Andre Bonin <Yoyoma_2@[at-]hotmail.com> wrote: : > : Hello all, i'me doing a school project requiring Cyclone2 chips, but all : > : the distributors I called (that allow single-order) have only the : > : EP1C7's (Cyclone1's speed grade 7). And furthermore they sell it for : > : around 300$ us (500 canadian). : > : > : Am i missing something? Altera says they cost under 3$ each. I concure : > : that yes volume pricing etc, but from 3$ to 500$ seems a rather large : > : increase. : > : > : I'me looking for the cheapest FPGA possible that will be easy to program : > : on the fly and could multiply a 10x10 matrix. Our design does have some : > : external ram and a PLD so System-On-Chip could be integrated into our : > : pci board. : > : > Did you consider going with Spartan 3? At nuhorizons they start at 13$45 : > with the XCF02 for 5$80. : From what i hear, the xilinx devices are harder to integrate with the : board. That's why w'ere gearing towards altera. About what problems did you hear? I had no problems so long... : Plus the school already : has altera equipment. Unless xilinx wants to give me free spartans : because i'me a starving student, then i'lle thank them in my term : presentation :). -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 73328
"Jimmy zhang" <crackeur@comcast.net> wrote in message news:<yj22d.440209$%_6.55759@attbi_s01>... > Hi, All, > A 32 bit adder takes two 32 bit inputs. The propogation delay > can be significant. if one of those two 32 bit inputs is a constant > 1, can the add logic be optimized so that the delay for increment > (+1) is reduced? Not really. A straight forward 32-bit adder and subtractor both are approcimately the same size and delay in an FPGA. But depending on you application you might be able to do a pipelined adder or carry save adder. (Cut the carry chain in pieces by flip-flops) Or you can count the lower bits by ring counter and use adders only for the higher bits. > The ohter question is that for 32 bit add, can I achieve 100Mhz > on the latest FPGAs? IIRC about 500 Mhz in Virtex-4. Even in older low cost FPGAs like Spartan-2 some 32-Bit Processors run close to 100 MHz so getting the adder to work at that frequency should really be no problem. Kolja SulimmaArticle: 73329
> Hello all, i'me doing a school project requiring Cyclone2 chips, but all > the distributors I called (that allow single-order) have only the > EP1C7's (Cyclone1's speed grade 7). And furthermore they sell it for > around 300$ us (500 canadian). > > Am i missing something? Altera says they cost under 3$ each. I concure > that yes volume pricing etc, but from 3$ to 500$ seems a rather large > increase. I bought EP1C3CT144-8 for < 16EUR and EP1C6Q240 - 8 for < 30EUR in EBV when you buy 10000, you ca get them at Altera's prices. Cyclone II will appear in a few monthsArticle: 73330
did you try in EBV?Article: 73331
I admit I'm puzzled. Within a given 'package' form-factor, the Virtex-4 and Virtex2P parts are going to have nearly identical circuitry (since they come off the same lithographic manufacturing process.) If you developed a field-process to extract the config-bitstream of 1 loaded/configured FPGA, presumably you could do it to any other FPGA based on the same die. So does it really matter whether the 'secret key' was unique to each customer's bitstream? Adam Megacz wrote: > Austin Lesea <austin@xilinx.com> writes: > >>See my other posting today. > > > Okay, so, it appears that my argument became invalid about a week ago > when the Virtex4 shipped. My apologies for this. > > But at the same time, so did the argument "we can't document the > bitstream because it will compromise customer design security".... So, > what is the current reason for not publishing the bitstream format? > > >>And, you are correct, we have no NVRAM in our FPGA devices right > > > I was probably a bit too specific there; I meant any sort of > customer-writable memory that doesn't get cleared when you take away > the main power supply to the device. The battery-backed memory for > storing a customer-specific decryption key is close enough -- in fact, > this is what Dallas Semico uses (rather than flash or some other > zero-current storage). > > I'm quite happy to see this; unlike previous schemes, this is > something I would actually trust. A customer-specific (or > design-specific) key is definately the only way to go for any sort of > real security. > > - aArticle: 73332
> Hi all. I'm looking for FPGA for real-time video processing. > The requirements are not yet fixed, but I think something > like Xilinx Virtex-II Pro from XC2VP7 to XC2VP30 would be > a good choice. PCI interface would be nice so that I could > plug the card in and transfer uncompressed video frames into > the card and get compressed frames back. Something like, > say 100 Mbit/s Ethernet, might also work but then it would > use pretty much all of the bandwidth. AVNET sells a Spartan3 and Virtex2p development board. Both have PCI edge-connectors. The Spartan 3 board is ~$500 USD (XC3S1500). Unfortunately, it doesn't have any SDRAM (just 1MB of SRAM), so it's probably not suitable for video-processing. The Virtex2p board starts at $2500 (price depends on the size of the bundled V2P FPGA.) It has 32MB SDRAM and 2MB of SRAM, which hopefully is enough to get you started! The XC2VP30-6 version is $3700 USD. Take a lot at http://www.ads.avnet.com, for details on each kit. (Click on "Evaluation and Development Kits", then scroll down to the "Xilinx" section. Look for "Xilinx Spartan-3 Evaluation Kit" and "Xilinx Virtex2 Pro Development Board") Oh, don't forget you'll need to get Foundation ISE (another +$2400 ISE.) The free webpack software won't target these high-capacity FPGAs! If you can rig-up your own I/O interface (to transfer the video data), also take a look at http://www.insight-electronics.com I admit these are 'less likely' to fit your criteria, but you could build a system using multiple boards (1 from Avnet, another from Insight.) Insight has a few (non-PCI) FPGA-boards. Finally, both companies have rather long 'lead times' for ordering. If you placed an order tomorrow, you'd be lucky to your FPGA boards 2-3 weeks from now (4-6 weeks is more typical.) At least that was my experience with Avnet, 4 years ago. Tuukka Toivonen wrote: > Also, I want to do development on Linux (Debian) host, > so the tools should run on that. Running Linux on the > FPGA PowerPCs sounds like a nice idea too. > > My question is: what hardware and software do I need? > Looks like I need: > - The development board. Prospective candidates are > Alpha Data's ADM-XPL and Amirix boards. Something > from Avnet might also do, except that it appears > they don't support Linux. Not sure about Alpha Data > either. And then there's Xilinx's > ML310 which appears to be a complete computer with > PCI slots and Ethernet. But it might have some bandwidth > problems, unless I connect camera directly into the > PCI slots in the board. > - Hardware development tools. Are there other alternatives > than ISE Foundation/BaseX? And are there differences > between the two except that the latter supports > devices only up to XC2VP7? > - Software development tools. Should I get them from the > board vendor or is it possible to use them from third > party? I have found EDK from Xilinx and the TimeSys SDK. > What is the difference between the two? Other alternatives? > - Operating system for the PowerPC inside the FPGA. Does > this come with the development kits or would I need > to get one separately? > - Something else? > > I hope the questions were not too silly, but I haven't > done any work with FPGAs before.Article: 73333
I've been a hardware (ASIC) engineer for the last 4 years, so I know all the basics of Verilog RTL coding, simulation, synthesis constraints, and the synthesis (netlist generation) design-flow. I've used Xess's XSV-300 and XS40-010XL+ FPGA-boards to do simple prototyping. I know my way around C (not C++), and I can probably struggle through a *tiny* bit of assembly, but honestly, I am no software engineer. I do know the basics of computer architecture (registers, "instruction pointer", branches, etc., what makes a CPU a CPU, etc.) ... Now I want to do some 'self-study' on embedded CPU and firmware systems. That got me looking at Xilinx's EDK (and Insight's Spartan IIE-Microblaze kit.) Hear's the problem -- the posts in this newsgroup worry me. It seems like the Xilinx EDK's audience is 'expereienced' firmware people. I.e., people who know the ins/outs of compiling/linking/"object relocation", and the dreaded "make-files." And if you are trying to use the EDK with an 'unsupported FPGA board' (target), good luck! Are all my fears unfounded? Does the EDK come with a "embedded design for dummies" tutorial? Or is it so complex, would it frustrate Linus Torvalds himself? I'm willing to do a little bit of learning while hair-pulling, but if the EDK just isn't for the novice, I'd rather not waste the $$$.Article: 73334
"Jake Janovetz" <jakespambox@yahoo.com> wrote in message news:d6ad3144.0409181559.64fbafc6@posting.google.com... > Hi folks- > > I was wondering if it is possible to reconfigure a Spartan 3 during > operation without losing the BRAM contents or overwriting it. Is this > possible with other FPGAs? Column-wise reconfiguration, would work, I > suppose. Spartan-3 FPGAs only support column-wise reconfiguration. As long as you avoid reconfiguring the DCM/Block RAM columns, you should be okay. -- SKKArticle: 73335
On Sun, 2004-09-19 at 18:04 +0000, Andre Bonin wrote: > cristian wrote: > > > Andre, > > > > I do agree with Symon, specially if you have a software background. Be > > careful when trying to synthesize (HARDWARE) your software. > > The goal of the project is ADPCM encoding and a 10x10 integer matrix > multiplication, i think that could be done within the FPGA. it would be > *nice* to be able to implement any C algo within hardware but i do > accept their are limitations. Though for some odd reason VHDL seems > more apt and less 'picky' about these kinds of loops. Or am i being > deceived? > > > Anyway, below is an example of how to implement a while_loop in VHDL. > > I added some comments reagarding the conditions under which the > > whil_loop is implemented; > > Thank you for this piece of code, it helps me get started and play > around with VHDL. VHDL seems more 'higher level' then verilog. For > this type of task, do you reccomend VHDL or Verilog? VHDL is an older > standard but my work with verilog gives me the hint that its lower level. <snip> There is always Handel-C which supports most of the C constructs (for, while, arrays, pointers, functions, etc) in FPGA hardware.Article: 73336
You might try the Xlinix ML310 ATX motherboard. It has XC2VP30 with 256MB RAM, 4 PCI slots, USB, 500MB Compact Flash, IDE interface, etc. Nice thing about this is that it boots Linux and/or Vxworks. "actela" <actela@nowhere.net> wrote in message news:0Lo3d.23081$CD7.8068@newssvr29.news.prodigy.com... > > Hi all. I'm looking for FPGA for real-time video processing. > > The requirements are not yet fixed, but I think something > > like Xilinx Virtex-II Pro from XC2VP7 to XC2VP30 would be > > a good choice. PCI interface would be nice so that I could > > plug the card in and transfer uncompressed video frames into > > the card and get compressed frames back. Something like, > > say 100 Mbit/s Ethernet, might also work but then it would > > use pretty much all of the bandwidth. > > > AVNET sells a Spartan3 and Virtex2p development board. > Both have PCI edge-connectors. > > The Spartan 3 board is ~$500 USD (XC3S1500). > Unfortunately, it doesn't have any SDRAM (just 1MB of SRAM), > so it's probably not suitable for video-processing. > > The Virtex2p board starts at $2500 (price depends on the > size of the bundled V2P FPGA.) It has 32MB SDRAM and > 2MB of SRAM, which hopefully is enough to get you started! > The XC2VP30-6 version is $3700 USD. > > Take a lot at http://www.ads.avnet.com, for details on > each kit. > > (Click on "Evaluation and Development Kits", then scroll > down to the "Xilinx" section. Look for > "Xilinx Spartan-3 Evaluation Kit" and > "Xilinx Virtex2 Pro Development Board") > > Oh, don't forget you'll need to get Foundation ISE (another +$2400 ISE.) > The free webpack software won't target these high-capacity FPGAs! > > If you can rig-up your own I/O interface (to transfer the video > data), also take a look at http://www.insight-electronics.com > I admit these are 'less likely' to fit your criteria, but > you could build a system using multiple boards (1 from Avnet, > another from Insight.) Insight has a few (non-PCI) FPGA-boards. > > Finally, both companies have rather long 'lead times' for ordering. > If you placed an order tomorrow, you'd be lucky to your FPGA > boards 2-3 weeks from now (4-6 weeks is more typical.) > > At least that was my experience with Avnet, 4 years ago. > > Tuukka Toivonen wrote: > > > Also, I want to do development on Linux (Debian) host, > > so the tools should run on that. Running Linux on the > > FPGA PowerPCs sounds like a nice idea too. > > > > My question is: what hardware and software do I need? > > Looks like I need: > > - The development board. Prospective candidates are > > Alpha Data's ADM-XPL and Amirix boards. Something > > from Avnet might also do, except that it appears > > they don't support Linux. Not sure about Alpha Data > > either. And then there's Xilinx's > > ML310 which appears to be a complete computer with > > PCI slots and Ethernet. But it might have some bandwidth > > problems, unless I connect camera directly into the > > PCI slots in the board. > > - Hardware development tools. Are there other alternatives > > than ISE Foundation/BaseX? And are there differences > > between the two except that the latter supports > > devices only up to XC2VP7? > > - Software development tools. Should I get them from the > > board vendor or is it possible to use them from third > > party? I have found EDK from Xilinx and the TimeSys SDK. > > What is the difference between the two? Other alternatives? > > - Operating system for the PowerPC inside the FPGA. Does > > this come with the development kits or would I need > > to get one separately? > > - Something else? > > > > I hope the questions were not too silly, but I haven't > > done any work with FPGAs before. >Article: 73337
David R Brooks wrote: > Does anyone know of a planned/released Development Board for the > larger Virtex-4 parts (preferably XC4VLX100)? > Google doesn't find anything. > TIA > Take a look here: http://www.fpgajournal.com/news_stories2004/Sept/20040914_01.htm -- ---------------------------------------- Mostafa Kassem M Dot Kassem At ieee Dot org ---------------------------------------Article: 73338
Hi, actela wrote: > Hear's the problem -- the posts in this newsgroup worry me. > It seems like the Xilinx EDK's audience is 'expereienced' > firmware people. I.e., people who know the ins/outs of > compiling/linking/"object relocation", and the dreaded > "make-files." > > And if you are trying to use the EDK with an 'unsupported > FPGA board' (target), good luck! Are all my fears unfounded? > Does the EDK come with a "embedded design for dummies" > tutorial? Or is it so complex, would it frustrate > Linus Torvalds himself? Put it this way - EDK has come a long way in the last couple of years, and it's still infinitely better than trying to hand-roll this stuff yourself. They have created a fairly push-button flow for instantiating processors, busses, peripherals, launching synthesis tools, compiling source code, inserting object code into the bitstreams, downloading said bitstreams, interfacing with simulation and debug tools, and so on. No matter how complex or otherwise EDK might be, it's still probably a lot better than trying to do all of that yourself, no? There are tutorials that will take you by the hand to demonstrate the basics of the flow. However, like all things once you need to step off that path, there is a learning curve. The fact that you see plenty of traffic here on the subject demonstrates an active user community and a variety of sources of help. Regards, JohnArticle: 73339
greg wrote: >>Hello all, i'me doing a school project requiring Cyclone2 chips, but all >>the distributors I called (that allow single-order) have only the >>EP1C7's (Cyclone1's speed grade 7). And furthermore they sell it for >>around 300$ us (500 canadian). >> >>Am i missing something? Altera says they cost under 3$ each. I concure >>that yes volume pricing etc, but from 3$ to 500$ seems a rather large >>increase. > > > I bought EP1C3CT144-8 for < 16EUR > and EP1C6Q240 - 8 for < 30EUR in EBV > when you buy 10000, you ca get them at Altera's prices. > Cyclone II will appear in a few months > > Do you mind e-mailing me your distributor? Thanks!Article: 73340
He's correct, there is no comparison. Xilinx once again makes a huge leap in technology. It's a slam dunk. V4 blows Stratix II out of the water in every regard. Austin Lesea <austin@xilinx.com> wrote in message news:<cifbj9$822@cliff.xsj.xilinx.com>... > Tim, > > There is no comparison. Seriously. Just go to the websites and compare > the features. > > V4 - triple oxide, low leakage, no power on surge in the core, faster, > over 100 new technical features (like SSIO, DSP48 MAC's, BRAM/FIFO, > 256AES, etc.) 4VLX25ES shipping now, development pcbs order entry open > and shipping ... > > Stratix II - ... (I'll let them play marketing) > > Austin > > Tim Michaels wrote: > > Although I have not posted yet to this group, I have an FPGA question. > > > > I am doing an evaluation of the Stratix II and the Virtex 4. Does > > anyone have any comparisons or experience of the features, > > performance, etc. of the two devices? I am trying to understand the > > tradeoffs of the two different platforms.Article: 73341
Simon Peacock wrote: > > Seriously... when are you planning to build? or are you after a one off... > If its not been in the market a year its not worth trying to buy them yet! > Only those in beta and those ordering thousands have any likelihood of > seeing any. So its not what features they have got... but what features > that you need that's important. We still use Spartan 2E's at work... why go > to Spartan 3 or vertex if you don't need them ??? One reason to use a newer part vs. an older part is that they typically cost less per LUT. The Spartan 3 is much cheaper than a Spartan II or IIE. The Cyclone II is much cheaper than the Cyclone (I) or the ACEX parts. Of course it is not a good idea to use a part that you can't get. But you should be able to get Spartan 3 parts by now and from what I have seen Altera has not had the same availability problems that Xilinx always seems to have on new parts. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73342
> > S3 is not 5V IO tolerant. You will need to have level shifter to pass > > from 3.3VIO to 5VIO. > > Hi friend, May i know what type of signal in Spartan-3 can interface with pc/104 via a level shifter? Pls help me. i'm a new this kind of design. give me some suggestion. Regards Senthil chett..Article: 73343
Andre Bonin wrote: > > cristian wrote: > > > Andre, > > > > I do agree with Symon, specially if you have a software background. Be > > careful when trying to synthesize (HARDWARE) your software. > > The goal of the project is ADPCM encoding and a 10x10 integer matrix > multiplication, i think that could be done within the FPGA. it would be > *nice* to be able to implement any C algo within hardware but i do > accept their are limitations. Though for some odd reason VHDL seems > more apt and less 'picky' about these kinds of loops. Or am i being > deceived? I think you are being deceived. I have coded in both VHDL and Verilog and have seen little difference in the two other than syntax. Both are capable of coding the same structures in similar ways. > > Anyway, below is an example of how to implement a while_loop in VHDL. > > I added some comments reagarding the conditions under which the > > whil_loop is implemented; > > Thank you for this piece of code, it helps me get started and play > around with VHDL. VHDL seems more 'higher level' then verilog. For > this type of task, do you reccomend VHDL or Verilog? VHDL is an older > standard but my work with verilog gives me the hint that its lower level. A piece of code is not really going to help you understand your problem or how to code in HDL. You need to consider that an HDL is just that, a Hardware Description Language and *NOT* a software programming language. I know that not everyone thinks or works like I do, but I find I fight the language much less if I design my hardware in my head or on paper and then use the HDL to describe my hardware. If you want to do a matrix operation, you really need to design the hardware to do that, then code that hardware. Just trying to write a software description of the problem will not in general give you a reasonable solution in the generated hardware. So think about the architecture you expect and then learn how to describe that hardware in your chosen HDL. Directly translating C to HDL is not a good way to go. You might even think about getting some assistance from a consultant or a training class. I found a little bit of training to go a long way with HDLs. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73344
"Andre Bonin" <Yoyoma_2@[at-]Hotmail.com> wrote in message news:B_r3d.457396$M95.217950@pd7tw1no... > greg wrote: >>>Hello all, i'me doing a school project requiring Cyclone2 chips, but all >>>the distributors I called (that allow single-order) have only the >>>EP1C7's (Cyclone1's speed grade 7). And furthermore they sell it for >>>around 300$ us (500 canadian). >>> >>>Am i missing something? Altera says they cost under 3$ each. I concure >>>that yes volume pricing etc, but from 3$ to 500$ seems a rather large >>>increase. >> >> >> I bought EP1C3CT144-8 for < 16EUR >> and EP1C6Q240 - 8 for < 30EUR in EBV >> when you buy 10000, you ca get them at Altera's prices. >> Cyclone II will appear in a few months >> >> > Do you mind e-mailing me your distributor? Thanks! He mentioned it - EBV. 8-) LeonArticle: 73345
glen herrmannsfeldt wrote: > > Stephen Williams wrote: > > (snip) > > > This can't be good advice. I have a co-worker who does that often, > > and I get to write drivers for the resulting chips. It bugs me a lot. > > > Using the configuration process to initialize things to a safe > > startup state is nice and all (especially for "roms" and the like) > > but RESET is *not* the same thing. > > I thought Xilinx FPGA's have the ability to connect reset inputs > to a global reset line. That can only reset to the same state > that the initial startup state is, though. This gets discussed here a lot. On both the Xilinx and Altera FPGAs there is a global reset line. This can establish an initial condition of all FFs in the device (but not RAM). It is activated on configuration (power up or otherwise) and can also be driven to a signal from inside or from an external pin. The problem with using this global signal is its slow propagation speed. Even if you release the reset synchronously with the clock (asynchronous release is guaranteed to create problems at some point) the slow prop speed means that with a fast clock different FFs can be released from reset on different clock cycles. This can result in bad values in counters and finite state machines (FSMs), possibly even locking up the design. There are many ways to deal with this problem. I typically design my circuits to not care if the global reset release is slow. This is done by giving a given section a separate synchronous reset that is part of the circuit. I think this may be discussed in the c.a.f FAQ. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73346
Ben Jackson wrote:
>
> If you use a continuous or non-blocking assignment in Verilog and
> the right hand expression is something that in a real device takes
> time to become valid after the inputs become valid, how do you
> ensure the output IS valid when you want to use it?
>
> For example:
>
> input [1000:0] megaparity;
> assign foo = ^megaparity;
>
> always @(posedge clk)
> // megaparity valid on this clk
> saved_parity <= foo; // when is this valid?
>
> What if the cascaded xor chain is so slow it's more than one clk period?
> More than 20? If you assume it's slower than it is (waiting some fixed
> number of clocks) don't you risk having it change with the input?
This is called a multi-cycle timing. You need to figure out just how
slow it will be and use a clock enable on your register. My Verilog is
rusty, but I am pretty sure you just use an IF statement, something like
this example I pulled from some public code.
always @(posedge clk)
begin : sr_proc
if (rst == 1'b 1)
begin
shift_reg <= 8'b 00000000; // sync reset
end
else
begin
if (spi_go == 1'b 1) // This would be your clock enable...
begin
shift_reg <= datain; // load with data from CPU
end
end
end
The signal spi_go in this example would need to go high for one clock
cycle N clocks after the inputs "megaparity" were valid.
Another way to do this is to structure your parity yourself, by xoring M
inputs into a FF and then xoring M FFs into the next stage. The delay
will then be in units of clock cycles, roughly O(logM (N)). Then you
adjust M to make it work in single clock cycles. This makes it much
easier to constrain your timing too.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 73347"Steven K. Knapp" wrote: > > "Jake Janovetz" <jakespambox@yahoo.com> wrote in message > news:d6ad3144.0409181559.64fbafc6@posting.google.com... > > Hi folks- > > > > I was wondering if it is possible to reconfigure a Spartan 3 during > > operation without losing the BRAM contents or overwriting it. Is this > > possible with other FPGAs? Column-wise reconfiguration, would work, I > > suppose. > > Spartan-3 FPGAs only support column-wise reconfiguration. As long as you > avoid reconfiguring the DCM/Block RAM columns, you should be okay. I have been meaning to send you an email to ask if the Spartan 3s are supported for modular reconfiguration yet. How is that going? I seem to recall that there were a couple of things that had to be resolved before the work could even begin. One was a "bug" or some aspect of the ISE software and the other was a work around for the fact that Spartan 3s don't have any tristate buffers. Have either of these issues been worked? How close are we to having a solution? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 73348
Andre Bonin wrote: > cristian wrote: >> I do agree with Symon, specially if you have a software background. Be >> careful when trying to synthesize (HARDWARE) your software. > The goal of the project is ADPCM encoding and a 10x10 integer matrix > multiplication, i think that could be done within the FPGA. it would be > *nice* to be able to implement any C algo within hardware but i do > accept their are limitations. Though for some odd reason VHDL seems > more apt and less 'picky' about these kinds of loops. Or am i being > deceived? (snip) Well, you can code a processor in VHDL, or use an FPGA that includes one, and then you can run any C algorithm on it. 10x10 matrix multiply in combinatorial logic is a little large even for today's FPGAs. Multiplying two 10x10 matrices is 10000 multiplies. Did you want to synthesize 10000 multipliers? I believe ADPCM encoders are well understood and not hard to implement, though I don't happen to know how to do it. Are the words coming in one at a time, one per clock cycle? How much work do you need to do on each cycle? Implement the hardware to do just that. Often the implementation of an algorithm, or even the algorithm itself is completely different done in hardware than in C. -- glenArticle: 73349
yes and no... older parts can be cheaper..... we are paying about $12 for our parts... and Spartan 3 maybe cheaper per LUT... but when you don't need as many as are available.. you are paying for a lot of unused silicon... and the extra regulator of course... :-) "rickman" <spamgoeshere4@yahoo.com> wrote in message news:414E72FC.BE94C870@yahoo.com... > Simon Peacock wrote: > > > > Seriously... when are you planning to build? or are you after a one off... > > If its not been in the market a year its not worth trying to buy them yet! > > Only those in beta and those ordering thousands have any likelihood of > > seeing any. So its not what features they have got... but what features > > that you need that's important. We still use Spartan 2E's at work... why go > > to Spartan 3 or vertex if you don't need them ??? > > One reason to use a newer part vs. an older part is that they typically > cost less per LUT. The Spartan 3 is much cheaper than a Spartan II or > IIE. The Cyclone II is much cheaper than the Cyclone (I) or the ACEX > parts. Of course it is not a good idea to use a part that you can't > get. But you should be able to get Spartan 3 parts by now and from what > I have seen Altera has not had the same availability problems that > Xilinx always seems to have on new parts. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX
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