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Hello again,
I need a 32 bit or so counter, clocked as fast as possible. Last
week, Mark Ng (thanks again!) sent me a very simple counter that can
be clocked > 400 MHz. Here is the code:
-- start Mark's code
entity count32m is
Port (clk : in std_logic;
reset : in std_logic;
MSB_Out : out std_logic);
end count32m;
architecture Behavioral of count32m is
signal counter : std_logic_vector(31 downto 0);
begin
process(clk, reset)
begin
if(reset = '0') then
counter <= (others => '0');
elsif (clk'event and clk = '1') then
counter <= counter + 1;
end if;
end process;
MSB_Out <= counter(31);
end Behavioral;
-- end Mark's code
This runs pretty nicely; WebPACK reports max clock of 416.667 MHz.
But the output cannot be read, so I added an output vector. I also
added an enable signal. The semantics I need is when the counter is
enabled, it counts clocks. When it is not enabled, it holds the last
count. I will only read the output count when the counter is not
counting. Pretty simple, but it drops my maximum clock frequency to
333.333 MHz! The enable signal is not the culprit; adding it to
Mark's code does not decrease the max freq, nor does removing it from
my code increase the freq. So it is clearly making the counter value
an output that causes the problem. Here is my version:
-- start Bob's code
entity count32 is
Port (enable: in std_logic;
clk : in std_logic;
reset : in std_logic;
dataout: out std_logic_vector(31 downto 0));
end count32;
architecture Behavioral of count32 is
signal counter : std_logic_vector(31 downto 0);
begin
process(clk, reset, enable)
begin
if (reset = '0') then
counter <= (others => '0');
elsif (enable = '1' and clk'event and clk = '1') then
counter <= counter + 1;
end if;
end process;
dataout <= counter;
end Behavioral;
-- end Bob's code
I don't understand what is going on here; can anyone help?
Thanks!
-Bob
Mark Ng <mark.ng@xilinx.com> wrote in message news:<civncn$7lh1@cliff.xsj.xilinx.com>...
> Hi Bob,
>
Article: 73726
"Rune Christensen" <rune.christensen@adslhome.dk> skrev i en meddelelse
news:4159c8c6$0$275$edfadb0f@dread12.news.tele.dk...
> "Symon" <symon_brewer@hotmail.com> skrev i en meddelelse
> news:2rti2pF1e4a0qU1@uni-berlin.de...
>> Rune,
>> Have you run the timing analyser to find out which path is failing? The
>> '(Levels of Logic = 9)' implies that it's not the carry chain, which, for
>> a
>> 28 bit counter, would be about 14 levels, 2 bits/level. I suggest you run
>> the analyser and post your failing path.
>> Cheers, Syms.
>> "Rune Christensen" <rune.christensen@adslhome.dk> wrote in message
>> news:41596bb8$0$257$edfadb0f@dread12.news.tele.dk...
>>>
>>>
>>> I have already done that but my goal is 8 ns and a simple implementation
>>> gives
>>>
>>> Slack: -1.380ns (requirement - (data path - clock path
>> skew
>>> + uncertainty))
>>> Source: cnt_0 (FF)
>>> Destination: cnt_3 (FF)
>>> Requirement: 8.000ns
>>> Data Path Delay: 9.373ns (Levels of Logic = 9)
>>> Clock Path Skew: -0.007ns
>>> Source Clock: clk_BUFGP rising at 0.000ns
>>> Destination Clock: clk_BUFGP rising at 8.000ns
>>> Clock Uncertainty: 0.000ns
>>>
>>
>>
>
> ================================================================================
> Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 8 nS HIGH 50.000000 %
> ;
>
> 3436 items analyzed, 17 timing errors detected. (17 setup errors, 0 hold
> errors)
> Minimum period is 8.347ns.
> --------------------------------------------------------------------------------
> Slack: -0.347ns (requirement - (data path - clock path
> skew + uncertainty))
> Source: cnt_0 (FF)
> Destination: cnt_19 (FF)
> Requirement: 8.000ns
> Data Path Delay: 8.337ns (Levels of Logic = 11)
> Clock Path Skew: -0.010ns
> Source Clock: clk_BUFGP rising at 0.000ns
> Destination Clock: clk_BUFGP rising at 8.000ns
> Clock Uncertainty: 0.000ns
>
> Data Path: cnt_0 to cnt_19
> Location Delay type Delay(ns) Physical Resource
> Logical Resource(s)
> ------------------------------------------------- -------------------
> CLB_R23C3.S0.YQ Tcko 1.292 cnt<1>
> cnt_0
> CLB_R28C2.S0.F1 net (fanout=4) 1.800 cnt<0>
> CLB_R28C2.S0.COUT Topcyf 1.486 _n0006<1>
>
> Madd__n0006_inst_lut2_01
>
> Madd__n0006_inst_cy_0
>
> Madd__n0006_inst_cy_1
> CLB_R27C2.S0.CIN net (fanout=1) 0.000
> Madd__n0006_inst_cy_1
> CLB_R27C2.S0.COUT Tbyp 0.096 _n0006<2>
>
> Madd__n0006_inst_cy_2
>
> Madd__n0006_inst_cy_3
> CLB_R26C2.S0.CIN net (fanout=1) 0.000
> Madd__n0006_inst_cy_3
> CLB_R26C2.S0.COUT Tbyp 0.096 _n0006<4>
>
> Madd__n0006_inst_cy_4
>
> Madd__n0006_inst_cy_5
> CLB_R25C2.S0.CIN net (fanout=1) 0.000
> Madd__n0006_inst_cy_5
> CLB_R25C2.S0.COUT Tbyp 0.096 _n0006<6>
>
> Madd__n0006_inst_cy_6
>
> Madd__n0006_inst_cy_7
> CLB_R24C2.S0.CIN net (fanout=1) 0.000
> Madd__n0006_inst_cy_7
> CLB_R24C2.S0.COUT Tbyp 0.096 _n0006<8>
>
> Madd__n0006_inst_cy_8
>
> Madd__n0006_inst_cy_9
> CLB_R23C2.S0.CIN net (fanout=1) 0.000
> Madd__n0006_inst_cy_9
> CLB_R23C2.S0.COUT Tbyp 0.096 _n0006<10>
>
> Madd__n0006_inst_cy_10
>
> Madd__n0006_inst_cy_11
> CLB_R22C2.S0.CIN net (fanout=1) 0.000 Madd__n0006_inst_cy_11
> CLB_R22C2.S0.COUT Tbyp 0.096 _n0006<12>
>
> Madd__n0006_inst_cy_12
>
> Madd__n0006_inst_cy_13
> CLB_R21C2.S0.CIN net (fanout=1) 0.000 Madd__n0006_inst_cy_13
> CLB_R21C2.S0.COUT Tbyp 0.096 _n0006<14>
>
> Madd__n0006_inst_cy_14
>
> Madd__n0006_inst_cy_15
> CLB_R20C2.S0.CIN net (fanout=1) 0.000 Madd__n0006_inst_cy_15
> CLB_R20C2.S0.COUT Tbyp 0.096 _n0006<16>
>
> Madd__n0006_inst_cy_16
>
> Madd__n0006_inst_cy_17
> CLB_R19C2.S0.CIN net (fanout=1) 0.000 Madd__n0006_inst_cy_17
> CLB_R19C2.S0.Y Tciny 0.545 _n0006<18>
>
> Madd__n0006_inst_cy_18
>
> Madd__n0006_inst_sum_19
> CLB_R17C3.S0.F3 net (fanout=1) 1.094 _n0006<19>
> CLB_R17C3.S0.CLK Tick 1.352 cnt<19>
> _n0002<19>1
> cnt_19
> ------------------------------------------------- ---------------------------
> Total 8.337ns (5.443ns logic,
> 2.894ns route)
> (65.3% logic, 34.7%
> route)
>
>
I have reached my goal by rearrange the circuit.
Now I only need to test the new circuit to see if it works :-)
Thanks to all the answer.
Cheers
Rune Christensen
-- frequency counter
f_cnt : freqcounter_28bit
port map (
rst => rst,
clk => clk,
pps => pps,
freq_meas => freq_meas,
running => running
);
-- pulse per second
-- pos edge detection
p_pps_edge : process(rst, clk)
begin
if (rst = '1') then
pps_edge_new <= '0';
pps_edge_old <= '0';
pps_edge <= '0';
elsif (clk'event and clk = '1') then
pps_edge_new <= pps;
pps_edge_old <= pps_edge_new;
pps_edge <= not pps_edge_old and pps_edge_new and running;
end if;
end process p_pps_edge;
-- running
-- edge detection
p_running_edge : process(rst, clk)
begin
if (rst = '1') then
running_edge_new <= '0';
running_edge_old <= '0';
cnt_step <= X"000_0001";
elsif (clk'event and clk = '1') then
running_edge_new <= running;
running_edge_old <= running_edge_new;
if ((running_edge_old and not running_edge_new) = '1') then
cnt_step <= not freq_meas;
else
cnt_step <= X"000_0001";
end if;
end if;
end process p_running_edge;
-- clock counter
p_counter : process(clk)
begin
if (clk'event and clk = '1') then
if (pps_edge = '1') then
cnt <= X"000_0000";
else
cnt <= (cnt + cnt_step) and not SXT(overflow & overflow, 28);
end if;
end if;
end process p_counter;
-- overflow detection
-- reference mode - when pps is present
-- local mode - when pps is missing
-- output:
-- overflow : std_logic;
p_overflow : process(cnt, freq_meas, running)
begin
if ((cnt & running)= (freq_meas & '0')) then
overflow <= '1';
else
overflow <= '0';
end if;
end process p_overflow;
-- trigger
-- pos edge detection
p_trigger_edge : process(rst, clk)
begin
if (rst = '1') then
trigger_edge_new <= '0';
trigger_edge_old <= '0';
elsif (clk'event and clk = '1') then
trigger_edge_new <= trigger;
trigger_edge_old <= trigger_edge_new;
trigger_edge <= not trigger_edge_old and trigger_edge_new;
end if;
end process p_trigger_edge;
-- timestamp register
-- timestamp / freq_meas => fraction of second
p_timestamp_reg : process(rst, clk)
begin
if (rst = '1') then
timestamp <= X"000_0000";
elsif (clk'event and clk = '1') then
if (trigger_edge = '1') then
timestamp <= cnt;
end if;
end if;
end process p_timestamp_reg;
================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 8 nS HIGH 50.000000 % ;
3110 items analyzed, 1 timing error detected. (1 setup error, 0 hold
errors)
Minimum period is 8.026ns.
--------------------------------------------------------------------------------
Slack: -0.026ns (requirement - (data path - clock path skew
+ uncertainty))
Source: cnt_2 (FF)
Destination: cnt_2 (FF)
Requirement: 8.000ns
Data Path Delay: 8.026ns (Levels of Logic = 9)
Clock Path Skew: 0.000ns
Source Clock: clk_BUFGP rising at 0.000ns
Destination Clock: clk_BUFGP rising at 8.000ns
Clock Uncertainty: 0.000ns
Data Path: cnt_2 to cnt_2
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
CLB_R21C4.S1.YQ Tcko 1.292 cnt<3>
cnt_2
CLB_R24C4.S0.G4 net (fanout=3) 1.304 cnt<2>
CLB_R24C4.S0.COUT Topcyg 1.396
Mcompar__n0006_inst_cy_28
Mcompar__n0006_inst_lut4_15
Mcompar__n0006_inst_cy_28
CLB_R23C4.S0.CIN net (fanout=1) 0.000
Mcompar__n0006_inst_cy_28
CLB_R23C4.S0.COUT Tbyp 0.096
Mcompar__n0006_inst_cy_30
Mcompar__n0006_inst_cy_29
Mcompar__n0006_inst_cy_30
CLB_R22C4.S0.CIN net (fanout=1) 0.000
Mcompar__n0006_inst_cy_30
CLB_R22C4.S0.COUT Tbyp 0.096
Mcompar__n0006_inst_cy_32
Mcompar__n0006_inst_cy_31
Mcompar__n0006_inst_cy_32
CLB_R21C4.S0.CIN net (fanout=1) 0.000
Mcompar__n0006_inst_cy_32
CLB_R21C4.S0.COUT Tbyp 0.096
Mcompar__n0006_inst_cy_34
Mcompar__n0006_inst_cy_33
Mcompar__n0006_inst_cy_34
CLB_R20C4.S0.CIN net (fanout=1) 0.000
Mcompar__n0006_inst_cy_34
CLB_R20C4.S0.COUT Tbyp 0.096
Mcompar__n0006_inst_cy_36
Mcompar__n0006_inst_cy_35
Mcompar__n0006_inst_cy_36
CLB_R19C4.S0.CIN net (fanout=1) 0.000
Mcompar__n0006_inst_cy_36
CLB_R19C4.S0.COUT Tbyp 0.096
Mcompar__n0006_inst_cy_38
Mcompar__n0006_inst_cy_37
Mcompar__n0006_inst_cy_38
CLB_R18C4.S0.CIN net (fanout=1) 0.000
Mcompar__n0006_inst_cy_38
CLB_R18C4.S0.COUT Tbyp 0.096
Mcompar__n0006_inst_cy_40
Mcompar__n0006_inst_cy_39
Mcompar__n0006_inst_cy_40
CLB_R17C4.S0.CIN net (fanout=1) 0.000
Mcompar__n0006_inst_cy_40
CLB_R17C4.S0.XB Tcinxb 0.046 overflow
Mcompar__n0006_inst_cy_41
CLB_R21C4.S1.G3 net (fanout=28) 2.060 overflow
CLB_R21C4.S1.CLK Tick 1.352 cnt<3>
_n0004<2>1
cnt_2
------------------------------------------------- ---------------------------
Total 8.026ns (4.662ns logic,
3.364ns route)
(58.1% logic, 41.9%
route)
--------------------------------------------------------------------------------
1 constraint not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 8.026| | | |
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 1 Score: 26
Constraints cover 3110 paths, 0 nets, and 575 connections
Design statistics:
Minimum period: 8.026ns (Maximum frequency: 124.595MHz)
Article: 73727
Rune,
make everything (more) synchronous. e.g.
-- clock counter
counter : process(clk, cnt, freq_meas)
begin
if (clk'event and clk = '1') then
if (reset = '1') then
cnt <= X"000_0000";
else
cnt <= cnt + 1;
end if;
-- local mode when reference is missing
if (cnt = freq_meas and localmode = '1') then
overflow <= '1';
else
overflow <= '0';
end if;
reset <= ref_edge or overflow;
end if;
end process counter;
Any better timing wise?
Cheers, Syms.
Article: 73728Austin Lesea <austin@xilinx.com> wrote: : Rick, : This issue is (was) new: the ESD protection of the Vcco pins was firing : on a high (very fast) dV/dt. Later mask sets got fixed, but some early : mask sets are still in production with this restriction. Any hints for decoding the top marking for that issue? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 73729
And tidy up the sensitivity list ;-)
counter : process(clk)
begin
if rising_edge(clk) then
...
...
Not to mention making cnt an integer type and overflow,
reset, localmode booleans. This could go on and on so
a wise deity invented comp.lang.vhdl
Symon wrote:
> Rune,
> make everything (more) synchronous. e.g.
>
> -- clock counter
> counter : process(clk, cnt, freq_meas)
> begin
> if (clk'event and clk = '1') then
> if (reset = '1') then
> cnt <= X"000_0000";
> else
> cnt <= cnt + 1;
> end if;
> -- local mode when reference is missing
> if (cnt = freq_meas and localmode = '1') then
> overflow <= '1';
> else
> overflow <= '0';
> end if;
> reset <= ref_edge or overflow;
> end if;
> end process counter;
Article: 73730Robert S. Grimes wrote: (snip of fast counter code) > This runs pretty nicely; WebPACK reports max clock of 416.667 MHz. > But the output cannot be read, so I added an output vector. I also > added an enable signal. The semantics I need is when the counter is > enabled, it counts clocks. When it is not enabled, it holds the last > count. I will only read the output count when the counter is not > counting. Pretty simple, but it drops my maximum clock frequency to > 333.333 MHz! Does the timing analysis know you will only read it when it is not enabled? I would guess it is setup time to the latch reading the count. Static timing analysis probably assumes it could be counting. -- glenArticle: 73731
Got it. Thanks.Article: 73732
Thanks. I'm on Spartan 3s so I'll use the COREGEN.Article: 73733
There doesn't appear to be any way to put timing constraints on the internal signals of a design. I have a fast clock and a slow clock and it would be best if I could put a timing constraint on the fast signals.Article: 73734
Followup to: <5c1de958.0306261459.7fe34c7d@posting.google.com>
By author: gregs@altera.com (Greg Steinke)
In newsgroup: comp.arch.fpga
>
> For either device, you do not need to compute the PLL values - if you
> tell Quartus the requirements it will compute the PLL settings for
> you.
>
I've had problems with Quartus II 4.1 (Web Edition SP0-2) and getting
the PLL values to make sense. In particular, if I feed it:
fin = 50 MHz
c0 = 4/1 = 200 MHz
c1 = 1/4 = 12.5 MHz
... it says it cannot make the desired PLL. 2.x and 3.x both did this
correctly, and if I lie and specify fin = 75 MHz it builds the correct
PLL and it works correctly with a 50 MHz input. The timing analyzer
spits out a message that the input frequency has been overridden (by
specifying clkin = 50 MHz as a timing constraint) and does the right
thing.
This is for a Cyclone EP1C20F400C7 device.
-hpa
Article: 73735On Tue, 28 Sep 2004 15:52:42 -0700, Brad Smallridge wrote: > There doesn't appear to be any way to put timing constraints on the internal > signals of a design. I have a fast clock and a slow clock and it would be > best if I could put a timing constraint on the fast signals. You can put a constraint from anything to anything in the UCF file. You can also put period constraints on all of your clocks. Read the CGD manual.Article: 73736
"Antti Lukats" <antti@case2000.com> wrote in message news:<cjc3ae$ves$01$1@news.t-online.com>... > "Roman Zeilinger" <Patrick.Bateman23@gmx.at> wrote in message > news:2rtd9aF1eq2mjU1@uni-berlin.de... > > Hi > > > > And where can I find the download link for the Verilog model? > > Because I can nowhere on the project site of aeMB! > > > > cheers > > Roman > > http://www.opencores.com/pdownloads.cgi/list/aemb > > get the archive, the verilog source is inside there, checked :) > > Antti If you check out the syn directory in that archive it lists the sythesis results for various FPGA's. What is interesting is the frequency of operation in a Xilinx device is >3X the Altera device. I would be very interested to see the results of a Nios-II core in a Xilinx Device!!Article: 73737
Hi All finally today the project maintainer at opencores uploaded the verilog design files for MicroBlaze compliant IP-Core. Download is available at opencores.com - as project aeMB !! for PicoBlaze there are 2 different open source 3rd party implementations known, i wonder when first NIOS-II open source IP-core will be available :) Antti xilinx.openchip.orgArticle: 73738
Whoops, forgot sensitivity list. Because I'm posting in CAF not CLV I should be cut some slack on my coding! ;-) IMHO, I think this does belong in this newsgroup; the thread is more about coding for an FPGA than VHDL per se. Cheers, Syms. "Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:cjcnbh$jut$1$830fa17d@news.demon.co.uk... > And tidy up the sensitivity list ;-) > > counter : process(clk) > begin > if rising_edge(clk) then > ... > ... > > Not to mention making cnt an integer type and overflow, > reset, localmode booleans. This could go on and on so > a wise deity invented comp.lang.vhdl >Article: 73739
I don't know where else to post this, so I hope ya'll won't mind a little complaining: First of all, the NGDBuild; it's way too picky on constraint names. I don't care if there is nothing in blah blah timing group, don't stop the compile! So the inst/net doesn't exist in my project? Whoopdy freakin' dupe. Don't stop the compile. edif2ngd: "2 0 0" Need I say more? Talk about minimal support. You'd think it was 1988. While we're on the topic, XST does a heck of a lot of optimization that could be done in the mapper or the edif2ngd. Those of us not using XST or some other $50k synthesizer are pretty much SOL on automatic optimizations. I'm talking about automatic use of local signals, muxf and carry chain inferrence, etc. Mapper: those messages about multiple references to padlocs are confusing at best. Not only that, it takes ages for it to realize there's a problem with hardset location constraints. PAR: This tool has improved a lot in the past five years. Nevertheless, I still lose at least an hour a day to it. I'd pay $1500+ for a board with a few Spartans (or something) and RAM chips to accelerate the tool, if it supported some kind of accelerator board. Is anybody working on this? I need some feature to autotrigger the "user requested termination" after x minutes after 0 untrouted signals, if that makes sense. Impact: $500 for the USB cable? Good thing it's only five times the price of the parallel cable. Eeesh. I expect Vasaline with my next shipment. The DMA stuff for the Parallel 4 is so picky, I've only got it to work on one of my ten boards. Does it have to be that exact? How about some timeouts on the verify for when it gets stuck? The batch support on the tool is nice but I have no way to pass in parameters. You know, like %1 %2 etc. -- general features to make the batch stuff usable on a real project? I suppose that's enough ranting for one day..... -- Prepend a 'b' to email me. Thanks.Article: 73740
For the Altera people in this group... One of the things I find really annoying with Quartus II is that whenever it gives resource counts, like in the final synthesis report or in the SignalTap configurator, it gives "bits of memory." The chip has some combination of M512, M4K and MRAM blocks, not "bits of memory." This makes it very hard to determine what actually going on, especially so since I've found it hard to get Quartus to use the 9th bit of M4K blocks, even when it should be possible. It would be a lot nicer to get the counts of actual physical resources used. -hpaArticle: 73741
"Roman Zeilinger" <Patrick.Bateman23@gmx.at> wrote in message news:2rtd9aF1eq2mjU1@uni-berlin.de... > Hi > > And where can I find the download link for the Verilog model? > Because I can nowhere on the project site of aeMB! > > cheers > Roman http://www.opencores.com/pdownloads.cgi/list/aemb get the archive, the verilog source is inside there, checked :) AnttiArticle: 73742
"Roger Planger" <ernte23@gmx.at> wrote in message news:2rtj7iF1ctckiU1@uni-berlin.de... > Hi > > I am currently developing a Co Processor which performs some arithmetic > operations more efficiently, and I want to test this within a processor. I > have done this once with den LEON Processor, but now I wanna try it with > Microblaze or Power PC Processor if this is possible. I use VHDL as design > language, so is there some online tutorial which explains me how I can add > my Co Processor and the new op-Codes which should be performed by the > Coprocessor. Unfortunately I wasnt able to find any information about this > on the web > > Cheers > Roger actually there is something, not exactly but indirect - for microblaze its more efficient to design the co-processor as FSL peripheral, I think there are some new articles and possible examples for that in new EDK 6.3 release unfortunatly that is not possible for PPC ASFAIK, so if you want both should possible design as an IPIF attachment anttiArticle: 73743
Thanks for the answer. However, if I use the locked signal as asynchronous reset, any glitch will reset the whole state machine. Since there are no other clock in the design, I won't be able to reset the DCM and start everything again...I'm not sure I understand your second statement about latching the falling edge. Even if I generate a flag, I don't see how I would reset the DCM. Thanks, David "Chris Alexander" <info@bostonsemiconductor.com> wrote in message news:376c28cd.0409280459.713d8c76@posting.google.com... > Yes - use the locked signal as an asynchronous reset. That will keep > your logic in a known state until the frequency is stable. > > Another thought is to latch the falling edge transitions in an error > flag so that if your DCM goes unlocked when you don't expect it to, > you can correct / cleanup with software. > > Chris > > "Dave" <gretzteam@hotmail.com> wrote in message news:<urSdnShroJyVN8XcRVn-hA@comcast.com>... > > Hi, > > I have a design (basically a FIR filter) that is clocked by the output of a > > DCM. I understand that I should not do anything before the locked signal > > goes high. However, what is the right way to do this? > > > > I also have a small state machine that resets the FIR filter, sets some > > stuff, and then enable everything. The state machine is also clocked by the > > output of the DCM (it is the only clock of the design). Should I use the > > locked signal as an asynchronous reset of the state machine so that nothing > > happens before locked goes high? I wonder if this is what people do, or if > > there is an easier way. > > Thanks, > > DavidArticle: 73744
Hi, I get the following error, I am not sure how to fix that. I have tried increasing the memory size, but that doesnt help. mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .sdata2) mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .sdata2) mb-ld: section .data [00000000 -> 0000005f] overlaps section .text [00000000 -> 0000109f] make: *** [TestApp/executable.elf] Error 1 Any suggestion in this direction will help. Thanks, MadhuraArticle: 73745
"Tony Burch" <tony@burched.com.au> wrote in message news:<4149187b$0$23897$afc38c87@news.optusnet.com.au>... > Hi Darien, > > Here is a new board that may meet your needs > http://www.trenz-electronic.de/prod/proden19.htm > > It's dimension is 50.7 x 43.6mm, however if you > took off the USB connector, and then used a dremel > tool, or a small mill, to route off the top egde and > the left edge (no, I'm serious:) ), then I think you > may be able to bring it down to your needed size. > > You could then solder your wires to the bottom > edge connector. > > Best regards, > > Tony Burch > B U R C H E D > Simple FPGA Boards, The Most Free I/O, Easy Prototyping > http://www.burched.biz Hm, sounds interesting, I might just try that... thanks for the advice. -DaragothArticle: 73746
I've seen a lot of boards that use FPGAs as a PCI logic core. For example, www.ads.avnet.com, www.insight-electronics.com, and www.dinigroup.com offer FPGA-devices mounted on a PCI form-factor (with the FPGA-device serving 'double-duty' as the PCI logic interface.) ... If I need to use an FPGA as a PCI-controller, are there any tricks I should know about? For example, when you 'turn on' a PC, the PCI-reset line is held for some # of cycles, then the PC's BIOS starts scanning the PCI-bus for devices. After a reset/powerup, will the FPGA configure itself in time? And what happens if you want to do 'on the fly' FPGA re-configuration? Will that lock-up the PC? (I.e., do the FPGA's I/O-pads go-crazy during the configuration op?) I apologize for these novice questions. I've been doing a lot of crash-course reading at xilinx.com's website, but perhaps I missed a few appnotes here and there.Article: 73747
Followup to: <g1r6d.2613$JG2.1445@newssvr14.news.prodigy.com> By author: don <don@don.com> In newsgroup: comp.arch.fpga > > If I need to use an FPGA as a PCI-controller, are there > any tricks I should know about? For example, when you > 'turn on' a PC, the PCI-reset line is held for some > # of cycles, then the PC's BIOS starts scanning the > PCI-bus for devices. > > After a reset/powerup, will the FPGA configure itself in time? > Typically not. Instead you need to: a) generate your own reset *in addition to* the external reset. This can be done with a counter which initializes to 0 and uses the MSB as a negative clock enable; your internal reset is then external RST_n & counter[MSB]. b) follow the predefined protocol for a device which needs to "join the PCI bus late." It basically means don't do anything or respond to anything until you've seen at least one cycle of the bus completely idle (see PCI bus spec for more details.) Another pitfall (for masters): make sure you implement all the stop conditions correctly. You cannot assume that you can always restart a transfer after a stop; some bridges don't handle crossing certain boundaries so "stop with data" is mandatory. > And what happens if you want to do 'on the fly' FPGA > re-configuration? Will that lock-up the PC? (I.e., do the FPGA's > I/O-pads go-crazy during the configuration op?) Most FPGA will tristate the "regular" I/O pads during configuration -- some small number of pads might not (so avoid using those for the PCI bus.) However, your OS might get confused about your device disappearing and reappearing in a resetted state as opposed to how it was configured. It is mostly a matter of how you write your driver -- you should issue the reconfiguration commands, remove the software end of the device from the OS stack, and re-insert it after the device comes back up. > I apologize for these novice questions. I've been doing a lot of > crash-course reading at xilinx.com's website, but perhaps I missed a > few appnotes here and there. I just did my first FPGA PCI design last year, so this is pretty fresh to me. -hpaArticle: 73748
Hi, I added the unisim and it works now. Thanks "Ken McElvain" <ken@synplicity.com> wrote in message news:a9k6d.11436$NC6.9087@newsread1.mlpsca01.us.to.verio.net... > Can you tell me which version of Synplify you are using? > 7.7 is the current release. > > Make sure you are not including a unisim.vhd file from anywhere > in your project. Synplify will automatically use a pre-compiled version with > some mapping attributes. If you include the unisim simulation > library, then those attributes will be missing. > > - Ken > > > van de Kerkhof wrote: > > > Hi, > > > > The solution of ken doesn't work i still het the same error. > > > > Error Code <xcmap.c:3416 Invalid LUT instantiation. Have you included the > > virtex.v(hd) file, and an INIT value?> > > @E:Internal Error > > > > The lut has an init value. > > > > When i add the virtex2 library this is gone, but with vcomponents it is > > still there. > > > > Bram > > > > > > > > "Symon" <symon_brewer@hotmail.com> wrote in message > > news:2rqv0sF1bi104U1@uni-berlin.de... > > > >>...or, if you're using ModelSIM (say), you can map the virtex2 library to > >>the UNISIM one. But Ken's solution is better... > >>Cheers, Syms. > >>"Ken McElvain" <ken@synplicity.com> wrote in message > >>news:GwV5d.11117$NC6.495@newsread1.mlpsca01.us.to.verio.net... > >> > >>>Use the unisim library instead. > >>> > >>>library unisim; > >>>use unisim.vcomponents.all; > >>> > >>>the "virtex2.components" package is only > >>>there for compatability with old projects. > >>> > >>>- Ken > >>> > >>> > >>>van de Kerkhof wrote: > >>> > >>> > >>>>Hi, > >>>> > >>>>How do I get this library trough compilation. When I include this in > > > > my > > > >>vhdl > >> > >>>>it gives an error with compilation. > >>>>If I leave it out synplify giveas an error with synthesis. And I don't > >> > >>like > >> > >>>>to manual add this to the vhdl every thime. > >>>> > >>>>Bram > >>>> > >>>> > >>> > >> > > > > >Article: 73749
Hi. I made a programmable lut delay. Xilinx ise thinks it may optimize some luts away how can i prevent this. I use synplicity for synthesis. I already tried: keep keep_architecture syn_noprune syn_keep syn_preserve. Changing the lut init by making an other design will change the number of luts it will optimize but it should be possible to say dont touch the luts?? Bram
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