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Hello: Sorry by my badly english, I have it very oxidized. I´m Spanish. My question is the following one, is become fond of to the electronic and is beginning with the CPLD subject (I want to have level to begin with FPGA, but I have left myself very great); I´m beginning to program them with VHDL and to understand its operation, I have several files *.jed of different devices. There is some way to turn them to VHDL. Thank you very much. A greeting!Article: 72301
"novato" <potxoka3a@yahoo.es> wrote in message news:cfj504$ahc4@eui1nw.euskaltel.es... > I have several files > *.jed of different devices. There is some way to turn them to VHDL. In theory it can be done but the result certainly will not be very readable and/or useful for education purposes. So, unless you are trying to hack somebody else's design this approach to studying VHDL and FPGAs or CPLDs is wrong. If you can't write your own code start with an example from a book or search online, there are plenty of free designs available. /MikhailArticle: 72302
Hi group,
I am trying to develop a digital camera around the NIOS II using the
Stratix development board.
I need to instantiate a large buffer (2MW) in the SDRAM.
In my code I instantiated my array like this:
alt_u16 Image_Buffer[0x2000000] __attribute__ ((section (".sdram"));
The SOPC builder has an SDRAM of 4MX32bits, so I should have enough
space to instantiae the array.
When I am trying to compile I am getting a messege that my SDRAM is
full unless I am reducing the array size to like 20000.
All of my program and data are stored in different memories (ext sram
and internal sram).
Questions:
1. What is the limitations of the array size?
2. Am I doing the right thing in instantiating the array like this?
I will appreciate any help,
Zohar
Article: 72303On Thu, 12 Aug 2004 16:04:44 -0600, Brian Philofsky wrote: > XST in the WebPack is the same as XST in Base-X to my knowledge. If you > have the same versions including service pack, I can not think of any > reason why the two would act differently in this respect. I have seen a > few strange things in the past like a hidden control character in the code > or left over "garbage" from a previous run in the working directory cause > situations like this. You might want to take another look at the code > and/or try creating a new project directory in the WebPack software to see > if it changes anything for you. May help you track down the problem. > > -- Brian You were right. I tried a new project and it works. Thank you for the tips. FrankArticle: 72304
I need some quick help: I am using the independent clock FIFO supplied by Xilinx in xapp175 on my digilent D2SB board, it is a Spartan 2E(300) with a 50Mhz external clock. I am using the dll_4x module also supplied by xilinx in an xapp to generate 2x(100Mhz) and 4x(200Mhz) clocks. The fifo works fine when driven with 50Mhz read and write clocks. However, I want to write at 100Mhz and read at 50Mhz. Whenever I attempt this, i am getting corrupt data through the fifo...either i am loosing data or duplicating it. Is 100Mhz too much to expect from this configuration, or is there something wrong with my design? I am using the exact same code that works at 50Mhz, but I am changing the write clock port map on the fifo to 100Mhz, as well as the clock of the process which generates data to write to the fifo. The process just generates a simple data pattern, and feeds a byte to the fifo if it is not full on that clock. The only curious note is that the FIFO module has BUFG's on both clock inputs, and it wouldn't compile with the BUFG's in place. I had to remove them and then it would compile fine. If I left the BUFG's in place it would give me multiple 'illegal' connection errors. Any help would be greatly appreciated. JuanArticle: 72305
hi all; is it possible to time optimize a compbinational logic with no time constraints (no clock specified) to get the best delay? (Using LeonardoSpectrum) thank youArticle: 72306
"zg" <zohargolan@hotmail.com> wrote in message
news:e24ecb44.0408131303.4bd272e2@posting.google.com...
> Hi group,
>
> I am trying to develop a digital camera around the NIOS II using the
> Stratix development board.
> I need to instantiate a large buffer (2MW) in the SDRAM.
> In my code I instantiated my array like this:
>
> alt_u16 Image_Buffer[0x2000000] __attribute__ ((section (".sdram"));
>
> The SOPC builder has an SDRAM of 4MX32bits, so I should have enough
> space to instantiae the array.
> When I am trying to compile I am getting a messege that my SDRAM is
> full unless I am reducing the array size to like 20000.
> All of my program and data are stored in different memories (ext sram
> and internal sram).
> Questions:
> 1. What is the limitations of the array size?
> 2. Am I doing the right thing in instantiating the array like this?
>
> I will appreciate any help,
> Zohar
0x2000000 is 20 megawords; 0x20000 is 2 megawords (4 megabytes,
4*1024*1024). You have one zero too much, that 16 times too much.
Jeroen
Article: 72307I, like others, am a little upset by the lack of a free (ISE Webpack) version of impact for GNU/Linux. As discussed in an earlier thread impact will not run under wine, it will not access the parallel port. However it can be made to produce SVF files. Using information from XAPP188 I was able to configure the Xilinx Spartan3 Starter Kit (the FPGA, not the Flash yet). I am not able to compare the speed with impact, but I can tell you that I configured a xc3s200 in about 4.3 seconds. http://www.rogerstech.co.uk/XC3Sprog.tar.gz This software is at it's early stage of development and I have only tested it on the Xilinx Spartan3 Starter Kit. It doesn't need to run as root since it uses /dev/parport0. Oh, it doesn't need its own kernel module driver either, unlike some programs! With ISE WebPack running on wine and now being able to configure the FPGA from GNU/Linux, do we have a complete tool chain for GNU/Linux that is free? Regards Andrew RogersArticle: 72308
<byseid@yahoo.com> wrote in message news:783d4d57.0408100407.68f1d8f6@posting.google.com... >I am not new for logic design but I need help for designing a > sequential Logic circuit analysis and design. > I want to design a traffic light controller for crossroad(of four > direction) the controller at each direction say A,B,C,D detects the > number of cars on each then the line having more cars will get the > priority... for more details please mail me <byseid@yahoo.com>. I would be happy to post here the schematic design for traffic lights for a cross road . Works fine for Australian roads:-) Edif fine ? AlexArticle: 72309
"Philip Freidin" <philip@fliptronics.com> wrote in message news:roqph0p144og9d8mp3h1n1g0lrd5uacapn@4ax.com... > On Thu, 12 Aug 2004 22:07:43 -0400, "Jerry" <nospam@nowhere.com> wrote: >>I don't have a pop up blocker since I get all kinds of loan, lonely heart >>and insurance offers as I >>surf around looking for the latest tech advances. > > Google, the company that tries to "Do No Evil" , has a toolbar > addon/plugin > for common web browsers: http://toolbar.google.com/ > > It's Free, it's easy and convenient to use, and it has an excellent > pop-up > and pop-under blocker. Probbably the most anti-evil thing I have on > my computer, and very well appreciated. Or get a copy of firefox and install the pop up blocker for that. http://www.mozilla.org/products/firefox/ Small fast and standards compliant. AlexArticle: 72310
Hi
Tested and working on my board (Avnet kit). A small patch was needed :
diff -urN XC3Sprog.org/devlist.txt XC3Sprog/devlist.txt
--- XC3Sprog.org/devlist.txt 2004-08-14 11:08:44.334268136 +0200
+++ XC3Sprog/devlist.txt 2004-08-14 11:09:04.034273280 +0200
@@ -1,3 +1,4 @@
# IDCODE IR Length Text
01414093 6 XC3S200
-05045093 8 XCF02S
\ No newline at end of file
+0141c093 6 XC3S400
+05045093 8 XCF02S
diff -urN XC3Sprog.org/ioparport.cpp XC3Sprog/ioparport.cpp
--- XC3Sprog.org/ioparport.cpp 2004-08-14 11:08:44.362263880 +0200
+++ XC3Sprog/ioparport.cpp 2004-08-14 11:09:21.670592152 +0200
@@ -80,7 +80,7 @@
bool IOParport::txrx(bool tms, bool tdi)
{
unsigned char ret;
- unsigned char data=0;
+ unsigned char data=0x10;
if(tdi)data|=1; // D0 pin2
if(tms)data|=4; // D2 pin4
ioctl(fd, PPWDATA, &data);
Sylvain Munaut
Andrew Rogers wrote:
> I, like others, am a little upset by the lack of a free (ISE Webpack)
> version of impact for GNU/Linux.
>
> As discussed in an earlier thread impact will not run under wine, it
> will not access the parallel port. However it can be made to produce SVF
> files.
>
> Using information from XAPP188 I was able to configure the Xilinx
> Spartan3 Starter Kit (the FPGA, not the Flash yet).
>
> I am not able to compare the speed with impact, but I can tell you that
> I configured a xc3s200 in about 4.3 seconds.
>
>
> http://www.rogerstech.co.uk/XC3Sprog.tar.gz
>
> This software is at it's early stage of development and I have only
> tested it on the Xilinx Spartan3 Starter Kit. It doesn't need to run as
> root since it uses /dev/parport0. Oh, it doesn't need its own kernel
> module driver either, unlike some programs!
>
> With ISE WebPack running on wine and now being able to configure the
> FPGA from GNU/Linux, do we have a complete tool chain for GNU/Linux that
> is free?
>
> Regards
> Andrew Rogers
>
Article: 72311
> Using information from XAPP188 I was able to configure the Xilinx Spartan3
> Starter Kit (the FPGA, not the Flash yet).
Can you tell me if your program works also for Spartan2 FPGA's ?
Regards,
Martin
Article: 72312Already I have received a few bug reports, thanks Sylvain. A new release, Release 0.3, can be found at http://www.rogerstech.co.uk/XC3Sprog.tar.gz I have included more Spartan3 devices in the device list. Regards AndrewArticle: 72313
Martin Maurer wrote: >>Using information from XAPP188 I was able to configure the Xilinx Spartan3 >>Starter Kit (the FPGA, not the Flash yet). > > > Can you tell me if your program works also for Spartan2 FPGA's ? > > Regards, > > Martin > > I think the programming algorithm is different, but try it and let us know. I have included some XC2Sxxx definitions in the device list to make easier to try. Unfortunately I only have the Xilinx Spartan3 Starter Kit and cannot verify its operation with other devices. Donations will be appreciated! Thanks AndrewArticle: 72314
Has anyone encountered this problem with Altera/Quartus? I have a set of cascaded registers which can either be implemented using cascaded lpm_ffs or an altshift_taps unit. I have a main clock and an enable signal with a clock enable multicycle setting of 5. If I implement the registers using lpm_ffs then the required clock setup time is correctly stated in the timing analyzer as being 33.33ns (main clock is at 150MHz -> 6.666ns period, 5*6.666ns = 33.33ns). However if I implement the registers using altshift_taps the required clock setup time is stated as being 6.666ns in the timing analyzer section of the compilation report, ie the clock enable multicycle setting of 5 has been ignored. I first noticed this type of problem when I had the auto shift register replacement option in the analysis and synthesis settings turned on, which converts lpm_shiftregs to altshift_taps. I can provide design files if anyone wants to try and help, I have waited 5 days for a response from Altera support.Article: 72315
Hi Friends, Minford Technology has Altera FPGA and CPLD downloader, it can replace Altera ByteBlaster II directly and work in AS mode, PS mode, JTAG mode. It supports all Altera FPGA, CPLD and configuration devices (EPC, EPCS1 and EPCS4). For more technical or ordering information, please visit us at www.minford.ca, we ship our products worldwide. Very low price compared with Altera ByteBlaster II(US$150) Sincerely, James Wang Minford Technology Inc. Tel: 1 (416) 953-8926 E-mail: info@minford.caArticle: 72316
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<XXYQc.2169$zS6.258026@news02.tsnz.net>... > It does seem to be down at the moment : what they offered was a DIP28 > footprint, done using a BGA ProASIC FPGA. > A quick google shows some links for their IP, but I did not see > photos/details of their PCB, best general description looks like > > http://www.us.design-reuse.com/news/news3814.html Hm, sounds interesting, I would be interested to know more information about it. > Anyone know if anything has happened to Quickcores & Jerry D. Harthcock ? It has been almost two weeks now and it is still down... perhaps the site is gone for good? -DAGArticle: 72317
Uwe Bonnes wrote: > glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > :> In some TDCs, the ramp is generated by trigger signal and sampled by the > For TDCs, look at http://www.acam.de I looked for some TDC descriptions before posting, but I didn't find a good one. Within the above site, http://www.acam.de/Content/English/tdc_method.html seems to be the one with an actual description. This is a little different from the one I knew about before, but interesting anyway. They call it fully digital, though it depends on the delay through a series of inverters. -- glenArticle: 72318
Hello: Thanks for the answer, tapeworm the intuition of which serious dificil can but. It is that I have files * jed and I want to see but or except its operation. Nothing but. Thank you very much. A greeting. MM escribió: > "novato" <potxoka3a@yahoo.es> wrote in message > news:cfj504$ahc4@eui1nw.euskaltel.es... > >>I have several files >>*.jed of different devices. There is some way to turn them to VHDL. > > > In theory it can be done but the result certainly will not be very readable > and/or useful for education purposes. So, unless you are trying to hack > somebody else's design this approach to studying VHDL and FPGAs or CPLDs is > wrong. If you can't write your own code start with an example from a book or > search online, there are plenty of free designs available. > > > /Mikhail > > >Article: 72319
1 Using the version 2.1 open the schematic to understand how the system work. 2 Using the WebPack write a NEW VHDL code to do the same function. And don't use schematic any more, with a good generic VHDL code you are free to use more than one software tool with minimum problems. Walter. "buke2" <cubah@tlen.pl> a écrit dans le message de news:cfhs71$2d1$1@atlantis.news.tpi.pl... > > "INS122595" <walter@chasque.apc.org> wrote in message > news:10hmpo4eg7tb20b@news.supernews.com... > > THX > > > > Open the schematic with the older software to know what do and know how > > work; and then redo the project into the most generic VHDL as possible; > > without trying to copy a schematic into VHDL. > > But I have only these 2 tools above - old tool - I can generate netlist but > new - ISE I cannot import it! > > > > > > ( One more reason to use VHDL standard ) > > > > Walter > > > > "buke2" <cubah@tlen.pl> a écrit dans le message de > > news:cff932$pv0$1@atlantis.news.tpi.pl... > > > Anybody knows how convert schemtic from Xilinx 2.1 to ISE6.2 Webpack? > > > It is very strange that ISE6.2 cannot convert earlier version of > schematic > > > (the same company). > > > > > > THX > > > > > > > > > > > >Article: 72320
"novato" <potxoka3a@yahoo.es> wrote in message news:cflphm$nfr1@eui1nw.euskaltel.es... > Hello: > > Thanks for the answer, tapeworm the intuition of which serious dificil > can but. It is that I have files * jed and I want to see but or except > its operation. Nothing but. Thank you very much. > > A greeting. Are you using a Spanish-to-English automatic translator? No offence, but it is difficult to understand what you were trying to say... /MikhailArticle: 72321
Hi Wilhelm, Please send me the .qar for your project, so that we can check if it is a bug or not and help you. Subroto Datta (sdatta@altera.com) Altera Corp. "Wilhelm Klink" <kommandantklink@hotmail.com> wrote in message news:6011e208.0408140511.1eecd45a@posting.google.com... > Has anyone encountered this problem with Altera/Quartus? > > I have a set of cascaded registers which can either be implemented > using cascaded lpm_ffs or an altshift_taps unit. I have a main clock > and an enable signal with a clock enable multicycle setting of 5. If > I implement the registers using lpm_ffs then the required clock setup > time is correctly stated in the timing analyzer as being 33.33ns (main > clock is at 150MHz -> 6.666ns period, 5*6.666ns = 33.33ns). However > if I implement the registers using altshift_taps the required clock > setup time is stated as being 6.666ns in the timing analyzer section > of the compilation report, ie the clock enable multicycle setting of 5 > has been ignored. I first noticed this type of problem when I had the > auto shift register replacement option in the analysis and synthesis > settings turned on, which converts lpm_shiftregs to altshift_taps. I > can provide design files if anyone wants to try and help, I have > waited 5 days for a response from Altera support.Article: 72322
In article <411d7665$1_1@127.0.0.1>, Andrew Rogers <andrew@_NO_SPAM_rogerstech.co.uk> wrote: >I, like others, am a little upset by the lack of a free (ISE Webpack) >version of impact for GNU/Linux. > >As discussed in an earlier thread impact will not run under wine, it >will not access the parallel port. However it can be made to produce SVF >files. > >Using information from XAPP188 I was able to configure the Xilinx >Spartan3 Starter Kit (the FPGA, not the Flash yet). Not sure what you mean by "the FPGA, not the Flash yet". Can you explain? Does this imply that we can now use the $99 board that Xilinx is selling with Linux now? What limitations are implied by "not the Flash yet"? > >I am not able to compare the speed with impact, but I can tell you that >I configured a xc3s200 in about 4.3 seconds. > > >http://www.rogerstech.co.uk/XC3Sprog.tar.gz > >This software is at it's early stage of development and I have only >tested it on the Xilinx Spartan3 Starter Kit. It doesn't need to run as >root since it uses /dev/parport0. Oh, it doesn't need its own kernel >module driver either, unlike some programs! > Good work! PhilArticle: 72323
I need some quick help: I am using the independent clock FIFO supplied by Xilinx in xapp175 on my digilent D2SB board, it is a Spartan 2E(300) with a 50Mhz external clock. I am using the dll_4x module also supplied by xilinx in an xapp to generate 2x(100Mhz) and 4x(200Mhz) clocks. The fifo works fine when driven with 50Mhz read and write clocks. However, I want to write at 100Mhz and read at 50Mhz. Whenever I attempt this, i am getting corrupt data through the fifo...either i am loosing data or duplicating it. Is 100Mhz too much to expect from this configuration, or is there something wrong with my design? I am using the exact same code that works at 50Mhz, but I am changing the write clock port map on the fifo to 100Mhz, as well as the clock of the process which generates data to write to the fifo. The process just generates a simple data pattern, and feeds a byte to the fifo if it is not full on that clock. The only curious note is that the FIFO module has BUFG's on both clock inputs, and it wouldn't compile with the BUFG's in place. I had to remove them and then it would compile fine. If I left the BUFG's in place it would give me multiple 'illegal' connection errors. Any help would be greatly appreciated. JuanArticle: 72324
kubik wrote: > I' m a beginner in the FPGA world so i went to Xilinx and Altera site to > download the free design software for learning the basics. > I have saw that all the software downloadable is for windows. > Am i wrong or is really so? > If so for me is very strange or wrong. Because for a design kit that is > freely distributed what platform is better than a free Operating System? > Without entering in the discussion of the better quality of Linux. > I hope i'm wrong and that someone tell me that i can download these > software for my gentoo Linux distribution. > > Thanks to all. > You can (at least) get the Xilinx webpack to run to a large extend. Look at my directions at http://www.danbbs.dk/~kibria/xilinx.html for more information. -- Brian
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