Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Wouldn't it be better using that memory as system memory? Physical space permitting, of course. Cheers, Syms. "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote in message news:B0OQc.277$5_.206@newsr2.u-net.net... > I can't speak specifically about this product but I do use RAID arrays and > previously RAMDISKs to improve performance and they do work. Looking at this > product I would think there is a good chance that it would help. Let me know > the results if you try it. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk > > > "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message > news:9LNQc.1135$x73.1112@newssvr27.news.prodigy.com... > > Has anyone looked into using this product, > > http://www.cenatek.com/product_rocketdrive.cfm > > to improve build time? > > > > Would there be any advantages? > > > > > > -- > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Martin Euredjian > > > > To send private email: > > 0_0_0_0_@pacbell.net > > where > > "0_0_0_0_" = "martineu" > > > > > >Article: 72051
I am currently working with a digilent pegasus board and trying to
connect wtih their Ram module using the OPB_emc. The problem is I am not
really sure where to start, I have the data sheets and shcematics for the
ram and boards. But i am confused on how the external memory controller
itself will deat with the ram. Any good tutorials you can point me towards
doing this would be very helpful.
Thank you,
Barron Barnett, barnettb@u.washington.**NOSPAM**.edu
Article: 72052Pete Fraser wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:41133277.590BD487@yahoo.com... > > > > > How exactly is Virtex II considered "old" technology. Virtex 2 is the > > newest, fastest parts that Xilinx has. Virtex2pro may be a bit > > newer/faster, but they are not the same generic parts, they all include > > Power PC CPUs internally driving up the cost considerably. > > > I guess "old" was the wrong term. > I was just pointing out that it might be more appropriate to compare > StratixII with Virtex4. Is that possible? Is Virtex4 supported by the current tools? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72053
"mihau" <spam@gohere.com> wrote in message news:cf027c$jlm$1@srv.cyf-kr.edu.pl... > Hi all, > > I design CAN controller in VHDL, and I don't know how it should start > working after power on. In the spec is written that CAN node can begin > transmission only during bus IDLE which means after at least 3 recessive > bits of intermission. But 3 recessive bits can also occur during > transmission from other node, so it is possible to violate spec by my CAN > controller starting transmission during these. Could someone clear this? > I will answer to myself :) Just wait for 11 recessive bits and you are in bus idle. MihauArticle: 72054
Rick, If you subscribed to the early access program, you would be using tools to develop your Virtex 4 design. Since that is a select few (one might even say insignificant number compared to the total number of users), I would not expect anyone out there to know about it, unless they were a customer who had expressed an interest in being an early adopter of the latest technology (also because if someone was part of the program, they sign the agreement not to divulge). Once the product is announced, and all software enabled, the good news is that there were many who had gone through it before you did, and helped hammer out all of the bugs. We greatly appreciate those who volunteer to be early access customers, and we hope that they feel that we have done everything we can to have supported them, as this is definitely something that benefits everyone. Austin rickman wrote: > Pete Fraser wrote: > >>"rickman" <spamgoeshere4@yahoo.com> wrote in message >>news:41133277.590BD487@yahoo.com... >> >> >>>How exactly is Virtex II considered "old" technology. Virtex 2 is the >>>newest, fastest parts that Xilinx has. Virtex2pro may be a bit >>>newer/faster, but they are not the same generic parts, they all include >>>Power PC CPUs internally driving up the cost considerably. >>> >> >>I guess "old" was the wrong term. >>I was just pointing out that it might be more appropriate to compare >>StratixII with Virtex4. > > > Is that possible? Is Virtex4 supported by the current tools? > >Article: 72055
> From: rickman <spamgoeshere4@yahoo.com>
> Virtex 2 is the
> newest, fastest parts that Xilinx has. Virtex2pro may be a bit
> newer/faster, but they are not the same generic parts, they all include
> Power PC CPUs internally driving up the cost considerably.
Not true. The Virtex-IIPro fabric is almost identical with Virtex-II, with
PowerPC and Multi-gigabit transceivers added to it. But the more advanced
processing makes V-IIPro both faster and -lo and behold- even cheaper than
the same logic in Virtex-II.
So you can ignore ("throw away") the PPC and the MGTs, and V-IIPro is still
less expensive than Virtex-II. If you use the PPC and/or the MGT, it is just
that much more of a bargain.
Just one of the benefits of Moore's Law and aggressive process innovation...
Peter Alfke
>
>
Article: 72056mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408051935.4b2c1d96@posting.google.com>... > Rick--Thanks very much for your offer to help. I hand coded FSM's for > years before StateCAD came along. The advantage of StateCAD is > accurate visual documentation to support checkout, less room for human > error, repeatability when making changes, and productivity. I might buy that if simulation were not available, but I have to agree with Rick. Consider coding in text, writing a standard testbench and thus eliminate the dependence on an obsolete tool. > The > current project I'm doing has six packed pages with over a hundred > states. I'll trade hours of tedious error-prone hand coding for the > click of a mouse any day. Six pages of circles and arrows might fit on one page of code and comments. > (BTW, I found that the free Xilinx version of Webpack ISE reads my old > Version 4.11 files fine and spits out Verilog, VHDL, and ABEL. I need > the C output, however. Evidently Xilinx dropped that.) Do you have the generated C code from the previous revision? What are you doing with C code? Good Luck, -- Mike TreselerArticle: 72057
Hi Martin, > Has anyone looked into using this product, > http://www.cenatek.com/product_rocketdrive.cfm > to improve build time? > Would there be any advantages? A faster storage device is only useful if you are disk I/O limited. There should not be a significant amount of time spent on disk access (in Quartus, at least) provided that you have sufficient physical memory for the design being compiled. If your computer is thrashing (swapping to disk frequently), then the easiest solution is more RAM. If it isn't thrashing, then I'm afraid you'll be limited by CPU speed. - PaulArticle: 72058
Just got my Xilinx Spartan 3 board operational. One part of the board sends digital data to a video DAC at 48 MHz. I did a priliminary program to send a test pattern to this DAC but the results change with a modification to the VGACLK'event and VGACLK='1' line. If I change the '1' to a '0' I get better results. I suppose I should now go Spartan 3 specific and use the Xilinx DCMs? Can someone point me to beginners doc on clock distribution and DCMs? I am printing the 68 page XAPP462 as I write this post but sheesh what a horse! Thanks, BradArticle: 72059
I'm using ISE 6.2i and when ever i use a Block RAM I cant see the Ram output Data the error is Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at simulation time 0.150 ns with respect to CLKB port at simulation time 0.150 ns. Expected setup time is 0.100 ns # Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at simulation time 0.250 ns with respect to CLKB port at simulation time 0.250 ns. Expected setup time is 0.100 ns # Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at simulation time 0.350 ns with respect to CLKB port at simulation time 0.350 ns. Expected setup time is 0.100 ns # Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at simulation time 0.450 ns with respect to CLKB port at simulation time 0.450 ns. Expected setup time is 0.100 ns the Enable pin is high and I change the Address but the out put is always 0 can any one help me with this ?? thanks THE UNFORGIVENArticle: 72060
[snip] > I expect you will find Altera and Xilinx to be pretty much equal for > most apps. The Xilinx parts seem to do a bit better in DSP or other > heavily pipelined apps. This is due to a couple of features they have > such as the SRL16 and the better adders they can make with the extra > input on their LUT in arithmetic mode. Whether this is useful to you > depends on your design requirements. > > Rick "rickman" Collins Rick, Nice post. One thing I'd like to point out though: You should check out the Stratix II ALM. It has very powerful arithmetic -- you can use a 4-LUT in front of each input of the adder when you are adding two numbers. That is more powerful than either Stratix or Virtex2. Also, it can add 3 numbers at a time, which reduces the depth and size of adder trees (this feature is also unique to Stratix II. VaughnArticle: 72061
"Austin Lesea" <austin@xilinx.com> wrote in message news:cf0di4$gju5@cliff.xsj.xilinx.com... > RP: > > There is no employee at Xilinx by that name. Try 1995, perhaps - it could have been faked but it's on the net. > I think the BS meter just pegged and broke! > > <ignore> > > Austin > > Rotund Phase wrote: > > From his IP address he's one > > CustName: J VASUDEVAMURTHY > > > > I found an email address on Google > > > > jagadeesh.vasudevamurthy@Xilinx.COM > > > > How very strange! > > > > "Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message > > news:eog5h0hguncjmoiu7b3cq6gu6beihebhl3@4ax.com... > > > >>On 5 Aug 2004 15:32:23 -0700, a2003zz@yahoo.com (John Smith) wrote: > >> > >> > >>>I am a full professor in a US school and do research > >>>in the area of synthesis. I also teach logic design for > >>>Undergraduate students. I had a six month sabbatical recently > >>>in a design house and I used many FPGA cad tools. I would > >>>like to shed my experiences in this group. > >>> > >> > >>Let's see: > >> - name is John Smith > >> - full professor at US school, but no mention of school name > >> - yahoo e-mail address > >> - Having attended engineering school, I realize that English is > >>not a top priority for students or faculty. Even so, the phrase "I > >>would like to shed my experiences" is not exactly > >>confidence-inspiring. > >> > >>I suppose this could be legit, but the ol' bogosity meter is sitting > >>near full scale. For starters, could you give us the university and > >>department names? > >> > >>Thanks, > >>Bob Perlman > >>Cambrian Design Works > >> > >> > > > > > >Article: 72062
> There > should not be a significant amount of time spent on disk access (in Quartus, > at least) provided that you have sufficient physical memory for the design > being compiled. Right. I knew that to be the case. We are using 2 gigs of RAM on the compile machines, which seems to be enough to avoid any significant disk I/O. I was hoping that there would be a little gem of a trick somewhere to take advantage of this sort of technology. -MartinArticle: 72063
It looks to me like you might be using an older version of the Xilinx library. That message has been changed to something like: Memory Collision Error on RAMB4_S16_S16:NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst at simulation time 0.450 ns. A read was performed on address 0000 (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle. I suggest you update the XE version and/or get the latest version of the libraries and rerun the simulation to see if you get an error message like the one above and if it makes more sense as to what the problem is with the design. Memory collisions are a design issue that must be accounted for proper circuit operation and that is what this error is trying to indicate. Also, looking at the times reported in the error messages, it looks like you might have a fairly fast clock in your testbench, 100 ps or 10 GHz which is far faster than the FPGA could possibly support and likely a mistake that should be corrected. I also suggest you hold off putting simulation stimulus for your design until after 100 ns has passed so that for timing simulation, you are not attempting to simulate during the global set/reset phase of the device simulation. -- Brian unforgiven wrote: > I'm using ISE 6.2i and when ever i use a Block RAM I cant see the Ram > output Data the error is > Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 > instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at > simulation time 0.150 ns with respect to CLKB port at simulation time > 0.150 ns. Expected setup time is 0.100 ns > # Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 > instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at > simulation time 0.250 ns with respect to CLKB port at simulation time > 0.250 ns. Expected setup time is 0.100 ns > # Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 > instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at > simulation time 0.350 ns with respect to CLKB port at simulation time > 0.350 ns. Expected setup time is 0.100 ns > # Timing Violation Error : Setup time 0.000 ns violated on X_RAMB4_S16_S16 > instance NCO_NCO_tf_tf.uut.RAMB4_S16_S16_inst.display_zero on CLKA port at > simulation time 0.450 ns with respect to CLKB port at simulation time > 0.450 ns. Expected setup time is 0.100 ns > > the Enable pin is high and I change the Address but the out put is always > 0 > can any one help me with this ?? > thanks > THE UNFORGIVEN >Article: 72064
pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0407312040.783610f9@posting.google.com>... > mikeandmax@aol.com (Mikeandmax) wrote in message news:<20040730131548.23098.00002650@mb-m07.aol.com>... > > > > > > I've discovered that there is some significant propagation delay > > >between the input and bidirectional pin & bidirectional pin to output > > >pin in my simulation. I've compared the function LPM_BUSTRI within > > >Quartus, a construction made up from Tri-state buffers within Quartus > > > > often prop delays in a tristate pin are due to OE performance - have you looked > > at the OE timinng numbers, or are you indeed looking at the prop delay of the > > in or out buffer. Most modern FPGAs now have syncronous OE and data registers > > at the pin, which can give you much better timing through the I/O. > > > > Mike Thomas > > Lattice fae > > Thanks for the update on where to start looking. After reading > further the specificatios in the delays within the Stratix IOE > structure, I've managed to compute the internal timing and external > timing for a given drive strength at the output for a bidirectional > pin: > > Internal Timing: > ================= > total prop. delay = ip/op register clock-to-output delay + IOE data > input to combinatorial output + setup time + hold time + routing delay > > In equation form I have this as: > > tpd1 = tco_c + tpcombin2pin_c + tsu + th + tlocal > tpd1 = 0.171 + 3.357 + 0.080 + 0.068 + 0.345 > tpd1 = 4.021 ns > > External Timing (4mA drive strength LVTTL) : > ========================================== > > total prop. delay = Setup time for bidi pin using column IOE registers > + Hold Time for bidi pin using column IOE registers + Clock-to-Output > Delay Bidi pin using column IOE registers > > In equation form I have this as: > > tpd2 = tinsu + tinh + toutco > tpd2 = 2.33 + 0 + 4.922 > tpd2 = 7.252 ns > > ** Hopefully I interpreted the specifications correctly? > > If my interpretation is correct, the issue I have now is that I'm not > sure if I should take total prop. delay = tpd1 + tpd2 = 11.273 ns? > Does anyone know if this is the correct thing to do? > > My reasoning for combining both is that the internal one relates to > the IOE internal timing & the external timing is associated directly > to the output bidirectional pin. > > Regards, > Pino Sorry to ask another question, but I wasn't too clear on whether if I am using a bidi pin I only have to take the above bidi pin prop. delay parameters or if I have to use the internal IOE prop. delay as well? Anyone know the answer to this? Cheers, PinoArticle: 72065
Hi,has anyone used ncsim for simulation with edk6.2.03i? I am having trouble finding the precompiled edk cores (e.g. microblaze) for ncsim. The documentation states that ncsim is supported, but the compedklib utility complains that it can't find any precompliled cores nor does any thing resembling it exists anywhere in the EDK installation. Thanks in advance for any help. JinArticle: 72066
Jim Granville <no.spam@designtools.co.nz> wrote in message news:<MoBPc.1495$zS6.183791@news02.tsnz.net>... > Did you look at the ones at www.quickcores.com - they are smaller than > your target size ? > -jg Actually, no I didn't... but unfortunately that link doesn't seem to work. Did the site go down? Is there another site like it? Thanks. -DAGArticle: 72067
Daragoth wrote: > Jim Granville <no.spam@designtools.co.nz> wrote in message news:<MoBPc.1495$zS6.183791@news02.tsnz.net>... > >> Did you look at the ones at www.quickcores.com - they are smaller than >>your target size ? >>-jg > > > Actually, no I didn't... but unfortunately that link doesn't seem to > work. Did the site go down? Is there another site like it? Thanks. It does seem to be down at the moment : what they offered was a DIP28 footprint, done using a BGA ProASIC FPGA. A quick google shows some links for their IP, but I did not see photos/details of their PCB, best general description looks like http://www.us.design-reuse.com/news/news3814.html Anyone know if anything has happened to Quickcores & Jerry D. Harthcock ? -jgArticle: 72068
Hi, This may be a basic question. I have read that 'reset' should not be de-asserted asynchronously. To de-assert this synchronously, is there any special circuit needed. I have come across a ciruit, where in it is given that use the synchronizer without reset to synchronize the reset going to main design. Also use as many synchronizers equal to the clock domains in the design. But my doubt is, what is it meant by synchronizer without reset, will the reset be tied to high for these flip-flops. Also, is there any difference in ASIC and FPGA environments in Synchronizing the reset. Thanks and regards, SatyaArticle: 72069
Yesterday I bought a LEGO mindstorms set (getting infantil in my old days...). After building the first robot, I want to substitue the RCX by an FPGA. Has anyone done this so far? Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 72070
Hi. I have an old ABEL source code (no JEDECīs) for an 82S100/PLS100 FPLA. Problem is that I can't find any company supporting ABEL compilers for these chips anymore. Xilinx, which aquired Synario/ABEL from Dataio, does only support it's own families of FPGAS/CPLDS. ABEL support for small PLDS has been taken over by Lattice also supporting only their own PLD families. Anyone know if Xilinx released legacy ABEL compilers as freeware, opensource or similar? EirikArticle: 72071
Satya wrote: > Hi, > This may be a basic question. I have read that 'reset' should not be > de-asserted asynchronously. To de-assert this synchronously, is there > any special circuit needed. There might be a cpu on your board. Run the fpga on the cpu clock. At boot time, have the cpu load the fpga then provide the reset pulse. -- Mike TreselerArticle: 72072
>Yesterday I bought a LEGO mindstorms set (getting infantil in my old >days...). After building the first robot, I want to substitue the RCX by >an FPGA. Has anyone done this so far? Why? Do you need microsecond level timing on some control loop? In general, if you can do the problem in software, it's better to use a uP rather than a FPGA. The developement software is more user friendly. That makes it much faster to try a new idea. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 72073
http://news.bbc.co.uk/1/hi/sci/tech/3542586.stm One of yours Austin? From the fix, it sounds like an FPGA thing!! ;-) Cheers Quote:- Rover project manager Jim Erickson said the likely solution to Spirit's problem would be to insert a delay between the signals to the component in question, called a gate array.Article: 72074
Very interesting marketing BS. Have you realy read the original questions and try to answer those? Sumit, if you need DSP functions, look at FPGA's with DSP alike architectures, if price is important (obviously, you are looking for high volumes), try to figure out what will be to total system cost (don't forget the configuration device!). If you want to design a uC in your FPGA, add security, etc... in other words, make a checklist with mins and max's and try to describe your design to the FAEs of Actel, Altera, Lattice and Xilinx (if you want to compare them all). If you like the idea of flash based - some devices will fall of the checklist, if you like SRAM, some others will fall of, etc. If you need 5V tolerance, well ... you won't select one of the newer devices as the aren't tolerant at all. Best regards, Luc On Thu, 05 Aug 2004 03:02:57 GMT, "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca> wrote: >> Thanks for your reply Thomas. I guess I should ask the question in a >> different way: for devices from different vendors with the same number >> of gates, will I get better performance and/or cost from a Flash or a >> SRAM based FPGA ? Also, I assume that the comment about usability of >> Xilinx cells being low is related to routability ? Is it any better >> with the Altera/Actel etc parts ? > >As another poster has indicated, Flash-based devices are just SRAM FPGAs >with an integrated Flash IP block. This removes the need for a stand-alone >EEPROM/Flash chip for configuration, and can provide a higher bandwidth >Flash-to-SRAM connection enabling faster configuration times, giving a >"instant-on" capability. > >The downside of Flash is that you are stuck on a Flash process. Flash >processes are behind standard CMOS processes -- I think I've seen 0.13u >Flash talked about somewhere in EETimes, but that's about the best you get >these days, and its immature. > >We've opted to include an on-die Flash memory in our Max II family of CPLDs. >These devices can't really take advantage of cutting-edge process technology >due to pad limitation and voltage/power requirements of the target market, >so the process "penalty" isn't an issue. And CPLD users want a simple, >one-chip solution and instant-on capabilities. > >To first order, chips manufactured in smaller process geometries are >faster -- our 90 nm Stratix II family is ~50% faster than our 130 nm Stratix >family. However, comparing two chips with different architecture (Stratix >vs. Virtex II, Cyclone vs. Spartan 3) by using process technology is not >going to necessarily give the right answer. For example, we find that >Cyclone is significantly faster than Spartan-3, despite being manufactured >on 130 vs. 90 nm. This can be due to numerous reasons -- power vs. speed >trade-offs, software quality, architectural advantages, etc. The bottom >line is you have to try out your design on the chips in question (via the >software) to really know. > > >As for usability/routability, Altera's FPGAs are designed to be routable at >100% utilization (both LUTs and registers) for all but the hairiest of >designs. I don't have any first-hand knowledge of the routability of >competitors parts and thus will not comment on that. > >Regards, > >Paul Leventis >Altera Corp. >
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z