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Hi Vikram, We have a custom FPGA board with two Optical Gigabit Ethernet ports and two SONET Compliant OC48 ports. We are using VirtexII-3000 and VirtexII-6000 parts. These are fully operational boards. As you may or may not be aware that 6000 parts are very expensive so are these boards. We use these boards for wire rate/performance testing for new designs. I do not know whether we are selling these boards. Surender Alliance Semiconductors Corp.Article: 72026
Matthew E Rosenthal wrote:
> Hi Mark,
> When I say fail, I mean the tool works fine and I d/l the design to my
> chip, but then after I run the design it fails in the lab after a few
> minutes. I know most of the logic is still functioning but some
> critical parts of it have stopped causing complete failure.
Howdy Matt,
I'm sure others in the group will come up with better ideas, but here's
the first thoughts that ran through my mind when you say it fails after
a few minutes:
1. Is it overheating?
2. Does it take about the same amount of time to fail every time you put
power to it? If you change the inputs to the FPGA, does the amount of
time change?
3. Are there any floating inputs on the device?
4. Any domain crossings that could lead to metastability (which could
cause a partial lockup)?
Without knowing what it is that is locking up, these are about the only
questions I know to ask.
Good luck,
Marc
Article: 72027Rick--Thanks very much for your offer to help. I hand coded FSM's for years before StateCAD came along. The advantage of StateCAD is accurate visual documentation to support checkout, less room for human error, repeatability when making changes, and productivity. The current project I'm doing has six packed pages with over a hundred states. I'll trade hours of tedious error-prone hand coding for the click of a mouse any day. And the dividends pay out every time I make a significant change. I'm grateful for your offer for help. (BTW, I found that the free Xilinx version of Webpack ISE reads my old Version 4.11 files fine and spits out Verilog, VHDL, and ABEL. I need the C output, however. Evidently Xilinx dropped that.) rickman <spamgoeshere4@yahoo.com> wrote in message news:<4112AB03.EAE7F85B@yahoo.com>... > I don't use it. I tried it or a similar program awhile back and I found > that it just put another level of confusion between me and the > hardware. I normally like to have better control over the bits in an > FPGA. If you read some examples on the web, I am sure you will find it > easy to code FSMs directly in VHDL (or verilog). If you email me a GIF > or PDF of your state diagram I would be happy to show you how I would > code it. > > > mmock wrote: > > > > As is suprnova, etc. no luck at all... I can't be the only person in > > the world using StateCAD to generate C code!! > > > > sense_1909S_VDB@yahoo.com (google_guy) wrote in message news:<cc4cf599.0408041328.7a6e24cd@posting.google.com>... > > > mwm11@cornell.edu (mmock) wrote in message news:<b2c16e8.0408032014.5129bb5c@posting.google.com>... > > > > Due to a calamtity of computer problems, including some affecting my > > > > backups, I'm suddenly in desparate need of StateCad Version 4.11 (or > > > > possibly Version 5.0) to support an active project. An evaluation > > > > version is fine. Can anyone help? > > > > > > eMule is your friend. Check it out and see if you can find a copy there. :) > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72028
On Thu, 05 Aug 2004 18:00:07 -0700, Sumit wrote: > > Is there some way of comparing how big Altera devices are versus > Xilinx devices. Whereas Xilinx lists the "System Gates", Altera lists > logic elements. So, I am not sure how to equate the product families > from the two vendors. Any help will be appreciated. > > Thanks > Sumit They are both based on 4 input LUTs, if you do a little math you can figure out how many LUTs they have in a device. As a first approximation this is a pretty good measure. Comparing the RAM is little easier since they both specify the number of bits of Block RAM although you have to take into account that Xilinx LUTs can also be used as RAM whereas Altera uses dedicated small Block RAMs instead of LUT RAMs.Article: 72029
Search Partial Reconfiguration and XAPP290 on Xilinx... Kelvin "supradeep narayana" <supradeep@gmail.com> wrote in message news:3e4ee61a.0408051030.43438c60@posting.google.com... > Hi, > I am looking for a topic for my Ms thesis on reconfigurable systems > design. I would like to know which are the current topics of research > in this area. > I would very much appreciate your help. > thanking you, > supradeepArticle: 72030
> Why not simply use two GPIO of the XScale for that ... and the linux driver would already been written. :( unfortunately the Xscale is not connected directly to the I2C devices on board, that is why I have to implement the I2C core in FPGA, I use FPGA as glue logic and now is the problem of chose the easiest way. Driver or core, that is a question now :) thanks, BartArticle: 72031
From his IP address he's one CustName: J VASUDEVAMURTHY I found an email address on Google jagadeesh.vasudevamurthy@Xilinx.COM How very strange! "Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message news:eog5h0hguncjmoiu7b3cq6gu6beihebhl3@4ax.com... > On 5 Aug 2004 15:32:23 -0700, a2003zz@yahoo.com (John Smith) wrote: > > >I am a full professor in a US school and do research > >in the area of synthesis. I also teach logic design for > >Undergraduate students. I had a six month sabbatical recently > >in a design house and I used many FPGA cad tools. I would > >like to shed my experiences in this group. > > > > Let's see: > - name is John Smith > - full professor at US school, but no mention of school name > - yahoo e-mail address > - Having attended engineering school, I realize that English is > not a top priority for students or faculty. Even so, the phrase "I > would like to shed my experiences" is not exactly > confidence-inspiring. > > I suppose this could be legit, but the ol' bogosity meter is sitting > near full scale. For starters, could you give us the university and > department names? > > Thanks, > Bob Perlman > Cambrian Design Works > >Article: 72032
Jim Granville wrote: > > rickman wrote: > > Jim Granville wrote: > > > >>rickman wrote: > >><snip> > >> > >>>I have one socket on a board that Xilinx could not fill. I needed 5 > >>>volt compatibility in a relatively low power device. All of the newer > >>>(read supported by current software) devices that are 5 volt tolerant > >>>have a power on current surge that makes it hard to use in a low power > >>>design without extra circuitry. So I ended up using an Altera ACEX > >>>(EP1K) device which is only about 3-4 years old. Otherwise their newer > >>>chips are mostly similar. > >> > >>.. Perhaps the new Virtex-4 that Peter A. is dying to tell us about also > >>solves the 5V i/o issues ;) > > > > > > I can assure you that it does not. The problem is twofold, 1) with the > > thinner oxides that are being used, it gets harder and harder to provide > > 5 volt tolerance without adding processing steps which drives up the > > cost and 2) 5 volt tolerance is becomming less and less important as > > various standards evolve away from the use of 5 volt interfaces. > > > > It has been explained to me several times that in the FPGA world, they > > had two choices, retain 5 volt tolerance or compete effectively in the > > high dollar, most current technology markets. > > You may have missed my smiley ? ;) Ah, yes I did!! :) -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72033
Pete Fraser wrote: > > "John Smith" <a2003zz@yahoo.com> wrote in message > news:b97fd375.0408051432.6baf5760@posting.google.com... > > I am a full professor in a US school and do research > > in the area of synthesis. I also teach logic design for > > Undergraduate students. I had a six month sabbatical recently > > in a design house and I used many FPGA cad tools. I would > > like to shed my experiences in this group. > > > > I worked on 15 big designs, already coded, targeting both virtexII > > and StratixII. All the designs were in verilog and I used > > Xilinx XST and Altera QNS at the front end. I spent lot > > of time to see the quality of results from the synthesis > > tools. For 11 designs, QNS won both in area and final > > fmax. XST was not even comparable in the quality of results. > > QNS compiler seems to do very good job compared to > > XST. Also, QNS does very good job in removing redundant logic > > and registers. So in my experience, QNS is a much better logic synthesis > > tools compared to XST. > > I'm not sure what this is telling us. It looks like you compared the > fmax of some designs in VirtexII (quite old technology) and > StratixII (quite new/future technology), and observed that the StratixII > implementation was faster. > > From this you deduced that the Altera synthesis was better. > > What am I missing here? How exactly is Virtex II considered "old" technology. Virtex 2 is the newest, fastest parts that Xilinx has. Virtex2pro may be a bit newer/faster, but they are not the same generic parts, they all include Power PC CPUs internally driving up the cost considerably. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72034
"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> writes: > If you want to create some initial designs for your XC3S50 > application without needing to build hardware, you might want to > investigate the Spartan-3 Starter Kit Board. By the way, I have one of these and it's great. - aArticle: 72035
Hi,
At least somebody who uses C++ for nios.
Do you need a linker script for that? I thought the dynamic area was placed
after RAMLimit (NiosI) or &end (NIOSII) automatically. So it changes with
the program size. Or is this your problem?
"Alessandro Strazzero" <alessandro.strazzero@virgilio.it> wrote in message
news:391fed46.0408050911.19b93bb9@posting.google.com...
> Dear everybody,
>
> I'm using GNU toolchain for NIOS and I have some problems using the
> C++ new
> operator. I think my problems depend of my linker script, so I hope
> any "guru"
> can help me.
>
> I have defined my ".data" section starting at 0xB0000. Once software
> is running I'm able to verify that dynamic objects are allocated after
> static memory. But,
> if I delete one object and allocate it again, the new operator
> allocate it at
> an address below 0xB0000.
>
> Is my linker script missing of any directive to define the dynamic
> memory area ?
> In general, how can I define dynamic memory area using ld ?
>
> Below I have attached my linker script. "nasys_data_mem" is equal to
> 0x80000
>
> I hope someone can help me.
>
> Best Regards
>
> /Alessandro
>
>
> ENTRY(_start)
>
> SECTIONS
> {
> /* Read-only sections, merged into text segment: */
>
> . = nasys_data_mem;
>
> /*
> * Begin the read-only code section here.
> */
>
> .text :
> {
> *(.text.prefix) /* Force prefix to be first */
> *(.init)
> *(.init.*)
> *(.text)
> *(.text.*)
> *(.gnu.linkonce.t*)
> } =0
>
> . = ALIGN(4);
> _etext = .;
>
> PROVIDE (etext = .);
>
> /*
> * Begin the read-only but not-relocated section of
> * memory here.
> */
>
> _nasys_rodata = .;
>
> .ctors :
> {
> _ctors_begin = .;
> KEEP (*(.ctors))
> _ctors_end = .;
> }
> .dtors :
> {
> _dtors_begin = .;
> KEEP (*(.dtors))
> _dtors_end = .;
> }
> .rodata :
> {
> *(.rodata)
> *(.rodata.*)
> *(.gnu.linkonce.r*)
> }
>
> _nasys_rodata_end = .;
>
> /*
> * --------------------------------------------------
> * the .data section contains initialized and writeable
> * variables. If we have separate code & data, we need
> * to have it load in code area, but have the symbols
> * resolve to the data area.
> */
>
> _nasys_data_source = .;
> /*_nasys_data_destination = (nasys_program_mem == nasys_data_mem) ?
> _nasys_data_source : nasys_data_mem;*/
> _nasys_data_destination = nasys_data_mem + 0x30000;
>
> .data _nasys_data_destination : AT (_nasys_data_source)
> {
> _data = .;
> *(.data)
> *(.data.*)
> *(.gnu.linkonce.d*)
> SORT(CONSTRUCTORS)
>
> . = ALIGN(4);
> _edata = .;
> _nasys_data_destination_end = .;
> PROVIDE (edata = .);
> }
>
> _nasys_data_source_end = _nasys_data_source + SIZEOF(.data);
>
> /*
> * Lastly, the noninitialized storage area.
> * This will start immediately following
> * the initialized data destination address end.
> * This is either right next to the code,
> * if code address = data address, or out in
> * the data memory, if they're different.
> */
>
> __bss_start = .;
> _nasys_uninitialized_storage = .;
>
> .bss :
> {
> _bss = .;
> *(.dynbss)
> *(.bss)
> *(.bss.*)
> *(COMMON)
> *(.dynsbss)
> *(.sbss)
> *(.sbss.*)
> *(.scommon)
> . = ALIGN(4);
> }
> _nasys_uninitialized_storage_end = .;
>
> /*
> * "_end" is used as the start of the mallocable memoryarea
> */
>
> _end = .;
> PROVIDE (end = .);
>
> /*
> * To see if you've exceeded memory, you can
> * check the symbols "_end" for the end of all static
> * data memory, and "_etext" for the end of the code,
> * against your memory map. -- dvb
> */
>
> /*
> * ------------------------------------------------------------
> * dvb say: "I'll leave all this stuff down here exactly
> * as I found it, for debugging info, without
> * understanding it."
> */
>
> /* Stabs debugging sections. */
> .stab 0 : { *(.stab) }
> .stabstr 0 : { *(.stabstr) }
> .stab.excl 0 : { *(.stab.excl) }
> .stab.exclstr 0 : { *(.stab.exclstr) }
> .stab.index 0 : { *(.stab.index) }
> .stab.indexstr 0 : { *(.stab.indexstr) }
> .comment 0 : { *(.comment) }
> /* DWARF debug sections.
> Symbols in the DWARF debugging sections are relative to the
> beginning
> of the section so we begin them at 0. */
> /* DWARF 1 */
> .debug 0 : { *(.debug) }
> .line 0 : { *(.line) }
> /* GNU DWARF 1 extensions */
> .debug_srcinfo 0 : { *(.debug_srcinfo) }
> .debug_sfnames 0 : { *(.debug_sfnames) }
> /* DWARF 1.1 and DWARF 2 */
> .debug_aranges 0 : { *(.debug_aranges) }
> .debug_pubnames 0 : { *(.debug_pubnames) }
> /* DWARF 2 */
> .debug_info 0 : { *(.debug_info) }
> .debug_abbrev 0 : { *(.debug_abbrev) }
> .debug_line 0 : { *(.debug_line) }
> .debug_frame 0 : { *(.debug_frame) }
> .debug_str 0 : { *(.debug_str) }
> .debug_loc 0 : { *(.debug_loc) }
> .debug_macinfo 0 : { *(.debug_macinfo) }
> /* SGI/MIPS DWARF 2 extensions */
> .debug_weaknames 0 : { *(.debug_weaknames) }
> .debug_funcnames 0 : { *(.debug_funcnames) }
> .debug_typenames 0 : { *(.debug_typenames) }
> .debug_varnames 0 : { *(.debug_varnames) }
> /* These must appear regardless of . */
> }
Article: 72036Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote: > I would rather not use the ultracontroller design anymore. I want to create a > EDK project from scratch, add a plb buss, add a few peripherials(gpio and > uart). Doesnt sound like i am asking for the world but i am having a tough time > finding some simple instructions on how to do it. > anybody know where i can find some instructions for this? Well, I can only tell you how I learned to use the EDK (no tutorial, sorry): use the included wizard to generate a basic system for one of the supported boards, for example the ML300, and then either start from this (and make whatever changes to the UCF), or read through the generated files to understand them. Since the ML300 supports gpio and uarts, the wizard should generate all the necessary components, i.e. ppc, plb, plb2opb, opb, opb_gpio, opb_uart16550. Good luck. EDK really isn't that hard to use :-) -gArticle: 72037
Rotund Phase wrote: > From his IP address he's one > CustName: J VASUDEVAMURTHY How'd you figure that then?Article: 72038
Hi,
I am not even a novice in this area but I do know that the
technology that IBM was employing was trying to mimic logic levels
similar to semiconductor based logic. They had a lot of problems doing
that and the final clock frequencies that they could achieve was
rather low for the investment. It was then that two researchers from
MSU, Moscow (Dr Likharev and Dr Semenov) came up with the idea of RSFQ
logic wherein logic is defined in terms of the presence or absence of
a quantum flux in the presence of a clock (which again is quantum flux
pulse). I hear that this approach has infact generated a lot of
quantifiable results and recently NEC, Japan even demonstrated a
partially functional RSFQ Processor. Here, in the U.S, Hypres Inc in
collaboration with a Prof from Stony Brook has generated a lot of
results and are even currently funded by NSF or DARPA for a RSFQ ADC
to be employed in the very first Software Defined Radio. Seeing all
this, I believe that "superconducting chips" are far from dead. Maybe
for certain applications, they might prove to be the only solution,
only time can tell. I have no idea though about what it takes to be a
researcher in this area nor can I comment on the future that it
entails.
Regards,
Digvijay.
johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0408051645.7f50ee61@posting.google.com>...
> supradeep@gmail.com (supradeep narayana) wrote in message news:<3e4ee61a.0408051028.1f0d694d@posting.google.com>...
> > Hello,
> > I have recently read some articles on superconducting circuits, and I
> > would like a n opinion on if the area of superconducting circuits is a
> > good and growing for doing research. particularly at stony brook,
> > where researchers have produced a lot of work.
> > Does this area require lot of knowledge on superconductivity and
> > physics.
> > you suggestions are welcome.
> > thanking you
> > supradeep
>
> For the purposes of the digital engineer, superconducting chips are
> super dead, IBM cancelled that no-producing technology 10-15yrs ago.
>
> But for power engineering and magnetics theres still some future I
> guess.
>
> regards
>
> johnjakson_uas_com
Article: 72039Hi all, I design CAN controller in VHDL, and I don't know how it should start working after power on. In the spec is written that CAN node can begin transmission only during bus IDLE which means after at least 3 recessive bits of intermission. But 3 recessive bits can also occur during transmission from other node, so it is possible to violate spec by my CAN controller starting transmission during these. Could someone clear this? MihauArticle: 72040
John Williams wrote: > Rudolf Usselmann wrote: >> Just wondering if anybody has a uLinux port for the Memec-Insight >> Virtex 2 pro 20 board ? > > Hi Rudi, > > There's an existing board port for the Insight/Memec 2VP7 board. It > would be an excellent starting point to get it going on the board you > mention. > > The microblaze-uclinux mailing list archives would be a good place to > start: > > http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Mailing_List/ > > Cheers, > > John Hi John, thanks a lot, I have seen you excellent work !!! Yes, we will look in to it ... Kind Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 72041
Has anyone looked into using this product, http://www.cenatek.com/product_rocketdrive.cfm to improve build time? Would there be any advantages? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 72042
Kelvin,
I just confirmed that this is the type of error that has been
addressed by the patch and it was included as a part of Service Pack 3
so I believe this has been fixed. If you want to verify whether this
problem does still exist for you, you should re-run the design through
the software after installing service pack 3 starting at least the Map
phase since the fix for this resides in that portion of the flow. The
problem in Map effects the hierarchy preservation of the design but does
not effect the functionality or other aspects so it would not cause any
issues until hierarchy is attempted to be reconstructed by the netgen
program which can cause the type of errors that you saw and disallow
hierarchy reconstruction.
If for some reason you still see this problem with Service Pack 3
or a newer version, just contact me or the Xilinx hotline and we would
like to get to the bottom of the problem.
-- Brian
Kelvin wrote:
> Anyway, maybe it is because I didn't upgrade my software. I am using 6.2.02i
> only.
> The error is pasted below, though my partial implementation and assembly had
> no error.
>
>
> Kelvin
>
>
> C:\projects\bt11a_jul28\top_bt\assemble>netgen -sim -ofmt
> verilog -w -ism -sdf_anno true -ngm top_sdr_map.ngm top_sdr.ncd
> Release 6.2.02i - netgen G.30
> Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
>
> Loading device database for application netgen from file "top_sdr.ncd".
> "top_sdr" is an NCD, version 2.38, device xc2v6000, package bf957,
> speed -6
> Loading device for application netgen from file '2v6000.nph' in environment
> C:/Xilinx6.2.
> The STEPPING level for this design is 0.
> ERROR:Anno - Cannot correlate logic element
> '"Mmux__n0004_inst_mux_f6_0/MUXF6"
> (tag=32161 in view "FRAGCOVERED")' is with this component 'bus_left(0)' -
> cannot continue hierarchical correlation)
> ERROR:Anno -
> -
> - This application found errors in the Ngm and/or Ncd data files
> - KEEP_HIERARCHY was corrupted and ignored (database will be flattened)
> -
<snip>
Article: 72043I can't speak specifically about this product but I do use RAID arrays and previously RAMDISKs to improve performance and they do work. Looking at this product I would think there is a good chance that it would help. Let me know the results if you try it. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:9LNQc.1135$x73.1112@newssvr27.news.prodigy.com... > Has anyone looked into using this product, > http://www.cenatek.com/product_rocketdrive.cfm > to improve build time? > > Would there be any advantages? > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > >Article: 72044
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:41133277.590BD487@yahoo.com... > > How exactly is Virtex II considered "old" technology. Virtex 2 is the > newest, fastest parts that Xilinx has. Virtex2pro may be a bit > newer/faster, but they are not the same generic parts, they all include > Power PC CPUs internally driving up the cost considerably. > I guess "old" was the wrong term. I was just pointing out that it might be more appropriate to compare StratixII with Virtex4.Article: 72045
Hi, I'm looking for recommendations for a power supply for development boards with Xilinx VirtexE parts (ie. XCV405E, XCV300E) that require 2.5 V, 3.3 V and 5 V. I'm looking for something cheap or a website that explains how to build such a beast. I'm also interested in hearing anybody's experiences of what works and doesn't. Thanks, Derrke SimmonsArticle: 72046
Matthew E Rosenthal wrote: > I would rather not use the ultracontroller design anymore. I want to create a > EDK project from scratch, add a plb buss, add a few peripherials(gpio and > uart). Doesnt sound like i am asking for the world but i am having a tough time > finding some simple instructions on how to do it. > > anybody know where i can find some instructions for this? > My approach was to take an existing project, and then figuring out how the pieces went together. I found the EDK gui to be more trouble than it is worth, at least for me. The fundamental thing to notice is that the EDK "project" is really just a makefile, generally system.make, that is created by the GUI. This makefile can be executed manually on the command line. When you run the makefile, it invokes a bunch of programs, and you can see what it is invoking and with what parameters. Each command invoked is documented somewhat (though the documentation as usual is somewhat lacking), so looking up how each command was invoked allows you to soon figure out what it is doing. Then to make changes, I just add and remove pieces and edit the the project files manually. The inevitable resulting error messages generally have been enough to steer me in the right direction. -- My real email is akamail.com@dclark (or something like that).Article: 72047
Pete, You are correct. 4VLX25 ES samples are available, too. Austin Pete Fraser wrote: > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:41133277.590BD487@yahoo.com... > > >>How exactly is Virtex II considered "old" technology. Virtex 2 is the >>newest, fastest parts that Xilinx has. Virtex2pro may be a bit >>newer/faster, but they are not the same generic parts, they all include >>Power PC CPUs internally driving up the cost considerably. >> > > I guess "old" was the wrong term. > I was just pointing out that it might be more appropriate to compare > StratixII with Virtex4. > >Article: 72048
RP: There is no employee at Xilinx by that name. I think the BS meter just pegged and broke! <ignore> Austin Rotund Phase wrote: > From his IP address he's one > CustName: J VASUDEVAMURTHY > > I found an email address on Google > > jagadeesh.vasudevamurthy@Xilinx.COM > > How very strange! > > "Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message > news:eog5h0hguncjmoiu7b3cq6gu6beihebhl3@4ax.com... > >>On 5 Aug 2004 15:32:23 -0700, a2003zz@yahoo.com (John Smith) wrote: >> >> >>>I am a full professor in a US school and do research >>>in the area of synthesis. I also teach logic design for >>>Undergraduate students. I had a six month sabbatical recently >>>in a design house and I used many FPGA cad tools. I would >>>like to shed my experiences in this group. >>> >> >>Let's see: >> - name is John Smith >> - full professor at US school, but no mention of school name >> - yahoo e-mail address >> - Having attended engineering school, I realize that English is >>not a top priority for students or faculty. Even so, the phrase "I >>would like to shed my experiences" is not exactly >>confidence-inspiring. >> >>I suppose this could be legit, but the ol' bogosity meter is sitting >>near full scale. For starters, could you give us the university and >>department names? >> >>Thanks, >>Bob Perlman >>Cambrian Design Works >> >> > > >Article: 72049
Derek, Hmmm, what input power do you have? Are you any good at PCB layout? How many are you making? Why are you using Virtex-E? Have you ever been in a Turkish prison? Whatever, my current (ha ha) favourites are LT parts. I've got a good FAE! LTC3728 is a dual controller can take up to 24V in and make 5V and 3.3V. I use LTC3414s to make core voltages from these supplies. LT do demo boards for both parts. Be environmentally friendly, ditch the evil linear regulators, use switchers! Especially as you can get 6.3V 100uF X5R ceramic in a 1210 package these days. And check out Panasonic's specialty polymer electrolytics. Bloody marvellous, 5 milliohm ESR. Cheers, Syms. "Derek Simmons" <Derek_SImmons@msn.com> wrote in message news:14030831.0408060846.73ab7ffe@posting.google.com... > Hi, > > I'm looking for recommendations for a power supply for development > boards with Xilinx VirtexE parts (ie. XCV405E, XCV300E) that require > 2.5 V, 3.3 V and 5 V. I'm looking for something cheap or a website > that explains how to build such a beast. > > I'm also interested in hearing anybody's experiences of what works and > doesn't. > > Thanks, > Derrke Simmons
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