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Martin Euredjian wrote: > > A good article in the latest IEEE Spectrum. Probably a ways out, but I'll > ask. Any work/thoughts on this technology applied to FPGA's? I'm not so sure it is "a ways out". Lasts weeks EE Times had a good article about several IP vendors and one will have product this year. "Cavendish Kinetics is introducing its cantilevered-beam approach this year initially for electroic fuse components in analog and mixed-signal circuits. That will be followed by a one-tim-programmable memory for embedded applications and then a many-times-programmable variety." I would expect this would make a great FPGA configuration memory technology. It is 10 times smaller than an SRAM cell, not affected by alpha particles (the article did not say about higher energy radiation) and non-volitile. They don't say what size CMOS process they are working with, but they indicate it should be scalable down to 22 nm. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72126
Now I am more confused. If I divide the number of slices by two, I get a number that is more than 4 times less than what is given in the data sheet. I don't understand how Altera data sheets relate to your data sheets. If marketing is going to write your data sheets, can you at least get them to give an honest definition of the logic cell??? "Logic Cell = ((1) 4-input LUT + (1)FF + Carry Logic) * 1.125" I don't care how you market, but right now your data sheets are not consistent and will confuse anyone who does not read this newsgroup. Peter Alfke wrote: > > This debate is getting long in the tooth. > Just take the number of slices and divide by two. > In the meantime, Altera has jumped on this bandwagon and they multiply their > ALE numbers by 1.25. > As long a there is Marketing, there will be "creativity" with numbers. > Just grin and bear it! > Peter Alfke > > > From: rickman <spamgoeshere4@yahoo.com> > > Reply-To: john@bluepal.net > > Newsgroups: comp.arch.fpga > > Date: Mon, 09 Aug 2004 13:46:36 -0400 > > Subject: Now I am really confused! > > > > While brushing up on the V2Pro, I saw in the data sheet where they > > actually define what a Logic Cell is, "Logic Cell = (1) 4-input LUT + > > (1)FF + Carry Logic". When I read this I thought maybe Xilinx has > > finally started printing facts in their data sheets about logic cell > > counts rather than marketing numbers. But no, somehow Xilinx still > > can't count and they are saying that 3,008 slices are equal to 6,768 > > logic cells. > > > > If Xilinx is going to define a logic cell, it makes sense to me that > > they should actually start counting them! > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72127
Peter Alfke wrote: > This debate is getting long in the tooth. > Just take the number of slices and divide by two. > In the meantime, Altera has jumped on this bandwagon and they > multiply their ALE numbers by 1.25. > As long a there is Marketing, there will be "creativity" with numbers. > Just grin and bear it! > Peter Alfke Our stuff still has a way to go before it catches up with the real smoke and mirror artists. Did the Citroen 2CV ever have a two horsepower engine, even when first introduced - whenever that was? Actually I don't understand that one... it's as if X advertised "Virtex-4: more than one LUT"Article: 72128
Hello everyone, My project needs quite a bit of RAM (1 MB is enough, more would be nice), and unfortunately, it needs to interface to a 5V CMOS device (35 inputs, 16 bi-dir, 3 outputs). Since I'm probably going to need level converting for pretty much any FPGA, I was thinking why not get a modern high-capacity one that is not even 5V tolerant. I could probably get away with just using resistors to pull a 3.3 output up to 5V, as the host system will be running under 10 MHz, but I saw someone mention that clamping diodes aren't active during configuration (at least on the cyclone). Is this true for most/all FPGA's? I can't prevent 5V signals from getting to the FPGA during configuration, since the 5V system will be configuring the thing eventually. My wish list is: At least 1 MB of RAM (preferably SRAM, since speed and bandwidth aren't a major factor and its a lot easier than trying to learn how SDRAM works, but I'm up for a challenge) 5V CMOS compatible I/O's (at least 54 not shared with the SRAM or anything else) At least 50 K gates, but speed isn't critical More of any is of course better, as would be a VGA port, but they're not essential Since this doesn't seem to exist, I've been thinking about just getting the $99 Spartan 3 kit (seems to be a great bargain) and adding on 74LVC4245A's, but I'd certainly prefer a board with them (or some other conversion technique) already on. Would this work fine? Are there any boards affordable to a hobbyist ($200 or less), with something like a bank of 74LVC4245A's already installed? Other peripherals like VGA and PS2 are nice but not essential, although they'd let me play with other things in the future and increase the value of the board a lot. Sorry for the long post, but I've been doing a lot of research and still getting nowhere. I plan on designing a custom built board in the end, but I don't think I could design one properly with my current knowledge, so I want to get a built, tested board first, and go from there. -- Michael NolandArticle: 72129
ok, I should have said multiply by two. I just think this argumenting about an extra 12.5%, silly as it may be, is not worth our combined efforts. Everybody knows where the factor comes from, most of us disagree with the reasoning. Grin and bear it. Do you want to argue about the meaning of "100%" in wine merchandizing? Do you want to fight the funny factor two in the "%proof" calculation? Or have you measured a "2 by 4 inch" piece of lumber? There is lots of fiddling with numbers going on... Peter Alfke > From: rickman <spamgoeshere4@yahoo.com> > Reply-To: john@bluepal.net > Newsgroups: comp.arch.fpga > Date: Mon, 09 Aug 2004 15:28:54 -0400 > Subject: Re: Now I am really confused! > > Now I am more confused. If I divide the number of slices by two, I get > a number that is more than 4 times less than what is given in the data > sheet. > > I don't understand how Altera data sheets relate to your data sheets. > If marketing is going to write your data sheets, can you at least get > them to give an honest definition of the logic cell??? > > "Logic Cell = ((1) 4-input LUT + (1)FF + Carry Logic) * 1.125" > > I don't care how you market, but right now your data sheets are not > consistent and will confuse anyone who does not read this newsgroup. > > > Peter Alfke wrote: >> >> This debate is getting long in the tooth. >> Just take the number of slices and divide by two. >> In the meantime, Altera has jumped on this bandwagon and they multiply their >> ALE numbers by 1.25. >> As long a there is Marketing, there will be "creativity" with numbers. >> Just grin and bear it! >> Peter Alfke >> >>> From: rickman <spamgoeshere4@yahoo.com> >>> Reply-To: john@bluepal.net >>> Newsgroups: comp.arch.fpga >>> Date: Mon, 09 Aug 2004 13:46:36 -0400 >>> Subject: Now I am really confused! >>> >>> While brushing up on the V2Pro, I saw in the data sheet where they >>> actually define what a Logic Cell is, "Logic Cell = (1) 4-input LUT + >>> (1)FF + Carry Logic". When I read this I thought maybe Xilinx has >>> finally started printing facts in their data sheets about logic cell >>> counts rather than marketing numbers. But no, somehow Xilinx still >>> can't count and they are saying that 3,008 slices are equal to 6,768 >>> logic cells. >>> >>> If Xilinx is going to define a logic cell, it makes sense to me that >>> they should actually start counting them! >>> >>> -- >>> >>> Rick "rickman" Collins >>> >>> rick.collins@XYarius.com >>> Ignore the reply address. To email me use the above address with the XY >>> removed. >>> >>> Arius - A Signal Processing Solutions Company >>> Specializing in DSP and FPGA design URL http://www.arius.com >>> 4 King Ave 301-682-7772 Voice >>> Frederick, MD 21701-3110 301-682-7666 FAX > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72130
On Mon, 09 Aug 2004 15:28:54 -0400, rickman wrote: > Now I am more confused. If I divide the number of slices by two, I get > a number that is more than 4 times less than what is given in the data > sheet. > > I don't understand how Altera data sheets relate to your data sheets. > If marketing is going to write your data sheets, can you at least get > them to give an honest definition of the logic cell??? > > "Logic Cell = ((1) 4-input LUT + (1)FF + Carry Logic) * 1.125" > > I don't care how you market, but right now your data sheets are not > consistent and will confuse anyone who does not read this newsgroup. > > > Peter Alfke wrote: >> >> This debate is getting long in the tooth. >> Just take the number of slices and divide by two. >> In the meantime, Altera has jumped on this bandwagon and they multiply their >> ALE numbers by 1.25. >> As long a there is Marketing, there will be "creativity" with numbers. >> Just grin and bear it! >> Peter Alfke >> >> > From: rickman <spamgoeshere4@yahoo.com> >> > Reply-To: john@bluepal.net >> > Newsgroups: comp.arch.fpga >> > Date: Mon, 09 Aug 2004 13:46:36 -0400 >> > Subject: Now I am really confused! >> > >> > While brushing up on the V2Pro, I saw in the data sheet where they >> > actually define what a Logic Cell is, "Logic Cell = (1) 4-input LUT + >> > (1)FF + Carry Logic". When I read this I thought maybe Xilinx has >> > finally started printing facts in their data sheets about logic cell >> > counts rather than marketing numbers. But no, somehow Xilinx still >> > can't count and they are saying that 3,008 slices are equal to 6,768 >> > logic cells. >> > >> > If Xilinx is going to define a logic cell, it makes sense to me that >> > they should actually start counting them! >> > >> > -- >> > >> > Rick "rickman" Collins >> > >> > rick.collins@XYarius.com >> > Ignore the reply address. To email me use the above address with the XY >> > removed. >> > >> > Arius - A Signal Processing Solutions Company >> > Specializing in DSP and FPGA design URL http://www.arius.com >> > 4 King Ave 301-682-7772 Voice >> > Frederick, MD 21701-3110 301-682-7666 FAX Peter should have said multiply by two instead of divide by two. There are two LUTs in a slice, 4 slices in a CLB. So take the number of slices and multiply by 2 to get LUTs. It looks like Xilinx is also counting the IOBs in their logic cell count.Article: 72131
Peter Alfke wrote: > > ok, I should have said multiply by two. > I just think this argumenting about an extra 12.5%, silly as it may be, is > not worth our combined efforts. > Everybody knows where the factor comes from, most of us disagree with the > reasoning. Grin and bear it. > Do you want to argue about the meaning of "100%" in wine merchandizing? Do > you want to fight the funny factor two in the "%proof" calculation? Or have > you measured a "2 by 4 inch" piece of lumber? There is lots of fiddling > with numbers going on... I agree Peter, this is not really worth much effort. I don't understand why you bring in unrelated issues such as the proof of spirits or the size of lumber. A 2x4 is sized according to a spec, no one says it is 2" x 4". The proof of spirits is not percentage, so I don't see why you are comparing the two, again, this is clearly stated. But the V2Pro data sheets defines a logic cell one way and are counted another way that is not discussed unless someone reads your posts here on the newsgroup. I understand who is doing it and why. At one point I thought it was just a matter of marketing getting into the data sheets. But if they contradict their own definition of what a logic cell is, then the data sheet contains falsehoods. If you don't want to discuss it, then feel free not to. I am not trying to sound rude or insulting. I belive I have only stated facts. So please don't feel that I have a grudge, I am just trying to get the facts straight. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 72132
John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<cf6uvm$211$1@bunyip.cc.uq.edu.au>...
> yujia jin wrote:
> > Hi,has anyone used ncsim for simulation with edk6.2.03i? I am having
> > trouble finding the precompiled edk cores (e.g. microblaze) for ncsim.
> > The documentation states that ncsim is supported, but the compedklib
> > utility complains that it can't find any precompliled cores nor does
> > any thing resembling it exists anywhere in the EDK installation.
> > Thanks in advance for any help.
>
> Have you tried `compedklib --help` ?
>
> ==== quote====
> Use Case I: Compiling HDL sources in the built-in repositories in
> the EDK
>
> The most common use case is as follows:
>
> compedklib -o <compedklib-output-dir-name>
> -X <compxlib-output-dir-name>
>
> In this case the 'pcores' available in the EDK install are compiled
> and the stored in <compedklib-output-dir-name> . The value to the
> '-X' option indicates the directory containing the models outputted
> by 'compxlib'. such as the 'unisim', 'simprim' and 'XilinxCoreLib'
> compiled libraries.
> ==== end quote ====
>
> Does that work?
>
> Regards,
>
> John
Hi John,
Thanks for your advice. I did look up compedklib --help before, along
with the info that is contained in the platform_studio_ug.pdf under
the compiling EDK behavioral simulation libraries section. Here is a
more detailed description of the problem.
The exact compedklib command that I used is
compedklib -s ncsim -o output-dir-name -X compxlib-output-dir-name
I was able to run the compxlib utility successfully earlier, which
generated ncsim compiled libraries for unisim, simprim, and
XilinxCorelib. The -X option is pointing to the corresponding xilinx
libraries directory.
The above compedklib gave me the following error message at the prompt
Scanning repositories for pcores ...
10 pcores located with (0) errors
20 pcores located with (0) errors
30 pcores located with (0) errors
40 pcores located with (38) errors
See compedklib.log for execution log.
Exiting: too many errors
The log file contains many lines that looks like the following
ERROR::Cannot locate pre-compiled library microblaze_v1_00_c
I also looked into the resulting output directory. It only contains
many empty sub directories.
I tried to look for the pre-compiled library for ncsim because
according to compedklib --help
Some 'pcores' are secure in that their source code is not
available.
In such cases, the repository contains the compiled
models. These are copied out into <compedklib-output-dir-name>
and the microblaze vhdl source files in the pcores directory are
encrypted. I only found the compiled models for the mti version under
EDK/hw/XilinxProcessorsIPLib/CompiledModels. Nothing similar for
ncsim was found. That is why I am confused. If simulation with ncsim
is supported as according to the documentation, then where are the
precompiled libraries for the EDK?
Thanks again.
Jin
Article: 72133"Peter Alfke" <peter@xilinx.com> wrote in message news:BD3D2E1B.7E71%peter@xilinx.com... > ok, I should have said multiply by two. > I just think this argumenting about an extra 12.5%, silly as it may be, is > not worth our combined efforts. > Everybody knows where the factor comes from, most of us disagree with the > reasoning. Grin and bear it. > Do you want to argue about the meaning of "100%" in wine merchandizing? Do > you want to fight the funny factor two in the "%proof" calculation? Or have > you measured a "2 by 4 inch" piece of lumber? There is lots of fiddling > with numbers going on... If people who market to engineers took to heart what engineers need - accurate information - then this discussion wouldn't involve *any* combined effort. I'd like to think the silicon vendors are more precise than the lumber industry or more informative than a centuries-old form of labeling alcohol content; after all, are the words "percent" and "proof" commonly used *together* in the wine industry? A troy ounce isn't an ounce. We know that. If definitions are provided and spec sheets adhere to those definitions, we're happy. If the spec sheet for a "2 by 4" specifies 2.00" x 4.00", we'll be unhappy with the undersized product - any spec sheet *should* have the actual dimensions and tolerance. Give an engineer precision and there won't be arguments. Complacency with marketing slop - inaccuracies for the sole purpose of justifying a position - may have a place in consumer advertising but is seen as marketing "lies" whenever we LEARN about the BLATANT inaccuracies of the marketing literature. Remember 19" displays (16.2" visible)? Suits forced the industry to properly specify the numbers. I know to go into the rows and columns to get my LUT or LE counts the way that I know they should be specified. It's because I know better now. What impression are we giving the new engineers looking to develop their first FPGA designs? Distorted information is expected from the silicon vendors? That's what they take away once they learn their original estimates were wrong because they didn't KNOW to do conflicting arithmetic on their datasheets. We - as engineers - will never be truly complacent with marketing distortions propagated by our organizations or those we do business with. I think there would be more respect and appreciation garnered from the engineering community if DATASHEETS were fully accurate and didn't include marketing distortions. I can see calling a device a "1Mgate" device where the definition of a gate varies with perspective, but don't tell me there are 12.5 lbs of manure in a 10 lb bag because it smells better to marketing. This is a distortion we continue wrestling with because we cannot change it. We can only work around it as individuals. How about taking up with other marketing slants and use verbiage like "compare with units having 12.5% more resources" or similar sidestepping? Those within the organizations selling FPGAs have to communicate that the numbers are "justified" because it's not right to call your own company's literature misleading. It's easy to "believe" that the numbers are okay because "that's the way it's always been" or that "everyone else is doing it" but it's wrong and there should be internal and external pressures to make the information *accurate* when accuracy is called for. And from where I sit, I feel I'm significantly less frustrated than rickman.Article: 72134
Oh... and remember years ago when Brand A illustrated 3 registers in their I/Os? My initial work with the datasheets said my timing was good. It was only after getting further into the design that I realized those I/O cells only contained SINGLE registers and couldn't possibly achieve my required performance. Some high-management folks eventually visited us to hear our rants and apologize for the confusion. They not only lost a socket to Brand X for the technical aspects of the design requirements but lost first consideration on most future sockets from a previously "biased" engineer. If I had the "correct" information in the front end of the design cycle, the marketing issues wouldn't have become engineering and financial issues. I would have had stronger respect for the currently offered solutions than I have now. Time heals many things.Article: 72135
John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<cf6uvm$211$1@bunyip.cc.uq.edu.au>...
> yujia jin wrote:
> > Hi,has anyone used ncsim for simulation with edk6.2.03i? I am having
> > trouble finding the precompiled edk cores (e.g. microblaze) for ncsim.
> > The documentation states that ncsim is supported, but the compedklib
> > utility complains that it can't find any precompliled cores nor does
> > any thing resembling it exists anywhere in the EDK installation.
> > Thanks in advance for any help.
>
> Have you tried `compedklib --help` ?
>
> ==== quote====
> Use Case I: Compiling HDL sources in the built-in repositories in
> the EDK
>
> The most common use case is as follows:
>
> compedklib -o <compedklib-output-dir-name>
> -X <compxlib-output-dir-name>
>
> In this case the 'pcores' available in the EDK install are compiled
> and the stored in <compedklib-output-dir-name> . The value to the
> '-X' option indicates the directory containing the models outputted
> by 'compxlib'. such as the 'unisim', 'simprim' and 'XilinxCoreLib'
> compiled libraries.
> ==== end quote ====
>
> Does that work?
>
> Regards,
>
> John
Hi John,
Thanks for you help. I did look up compedklib --help before, along
with the info in platform studio user guide under the section
compiling EDK behavioral simulation libraries. Here are some more
detail to my problem.
The exact command that I executed is
compedklib -s ncsim -o compedklib -X compxlib
The compxlib directory contains the ncsim compiled librarys for
unisim, simprim, and XilinxCoreLib. The errors I are got at prompt
are
Scanning repositories for pcores ...
10 pcores located with (0) errors
20 pcores located with (0) errors
30 pcores located with (0) errors
40 pcores located with (38) errors
See compedklib.log for execution log.
Exiting: too many errors
The errors in the log files are all similar to
ERROR::Cannot locate pre-compiled library microblaze_v1_00_c
The output directory contains only empty sub directories.
I tried to find the precompiled libraries for ncsim, but only found
those for mti under EDK/hw/XilinxProcessorIPLib/CompiledModels.
Thanks again
jin
Article: 72136Hi Jin, yujia jin wrote: > John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<cf6uvm$211$1@bunyip.cc.uq.edu.au>... > >> >>Have you tried `compedklib --help` ? > > I tried to look for the pre-compiled library for ncsim because > according to compedklib --help > > Some 'pcores' are secure in that their source code is not > available. > In such cases, the repository contains the compiled > models. These are copied out into <compedklib-output-dir-name> > > and the microblaze vhdl source files in the pcores directory are > encrypted. I only found the compiled models for the mti version under > EDK/hw/XilinxProcessorsIPLib/CompiledModels. Nothing similar for > ncsim was found. That is why I am confused. If simulation with ncsim > is supported as according to the documentation, then where are the > precompiled libraries for the EDK? Ah yes I see now what you mean. I'd be contacting Xilinx support on this one - there's really not much you can do with that encrypted VHDL... Regards, JohnArticle: 72137
Hi Andrew, Andrew Rogers wrote: > Does anyone have impact running under wine? > > Can I configure my Spartan3 Starter Kit from GNU/Linux? If so, how? > > I have tried to run impact under wine but it fails to connect even as > root. Perhaps this is due to some wrong configuration in my wine.conf. I'd be very surprised if you could run impact under Wine - it needs direct hardware access to the parallel port. If you are using normal Xilinx ISE tools they can be installed native under Linux - Impact works fine. Regards, JohnArticle: 72138
Hi How much of a consideration is the quality of design tools while choosing the FPGA vendor/device for a design? I guess this comes down to - are most of the tools out there almost of similar quality in terms of leading to designs with similar performance, area (FPGA usage), etc ? I know a lot of folks are partial to Xilinx and Altera, but I am trying to consider others as well, and want to know how carefully I have to look at tool offerings to evaluate all of them. Thanks SumitArticle: 72139
mmock wrote: >>Eirik Seljelid wrote: >> >>>considered the PA7536, but I find it way easyer to get an older version >>>of ABEL, compile the code for 82S100 and burn the chips. >> > Eirik, > > Have you located it? I'm not familiar with the 82S100. I have an > ancient version of ABEL, circa 1988. Is that too ancient? > > Mike Not sure. I've found Abel 2.0 and Abel 4.0 on the net and tried to compile the source, but in both versions I got the message "fatal error: out of memory". It worked when I tried to compile only parts of the source. EirikArticle: 72140
Philip Freidin <philip@fliptronics.com> wrote in message news:<etptg09pd0bgf0b0438544aah7td9hnpif@4ax.com>... > try http://alternatezone.com/electronics/files/PCBDesignTutorialRevA.pdf Ah, thanks a lot. It was helpful. > You could try this freeware version: > > http://www.cadsoft.de/freeware.htm I haven't gotten around to downloading that yet, but thanks for the link. -DAGArticle: 72141
Jim Granville wrote: > Eirik Seljelid wrote: > >> Thanks for answering. The 82S100 is now in production reintroduced to >> the marked by QP Semi. Anyway, this is not an issue for me as my >> organisation has 82S100's in-house in adequate numbers. My project >> consist of replacing an older version of the programmed chip with a >> newer one on a limited number of circuit cards. I have already >> considered the PA7536, but I find it way easyer to get an older >> version of ABEL, compile the code for 82S100 and burn the chips. > > > Wow, a PLS100 data sheet with June 2004 on it :) > Google did find what looks like (most of?) Amaze, here > http://www.filelibrary.com/Contents/DOS/80/ > - in case you have problems finding an old ABEL > with the 82S100/PLS100. > You could also try direct fuse editing :) > -jg > Thanks, but I've found and downloaded it when you gave me the name. Haven't tried it though, as disk 2 was missing and I later on found Abel on a web site. EirikArticle: 72142
John_H wrote: > Oh... and remember years ago when Brand A illustrated 3 registers in their > I/Os? My initial work with the datasheets said my timing was good. It was > only after getting further into the design that I realized those I/O cells > only contained SINGLE registers and couldn't possibly achieve my required > performance. Some high-management folks eventually visited us to hear our > rants and apologize for the confusion. They not only lost a socket to Brand > X for the technical aspects of the design requirements but lost first > consideration on most future sockets from a previously "biased" engineer. > > If I had the "correct" information in the front end of the design cycle, the > marketing issues wouldn't have become engineering and financial issues. I > would have had stronger respect for the currently offered solutions than I > have now. Time heals many things. Here's a radical thought : Given that 'marketing numbers' have caused, over time, at a minimum annoyance or bemusement, and at a maximum (above) outright customer flight, what about the idea that instead of excusing this silliness, it actually gets fixed, and data sheets get provided with accurate formula for available resource ? If that formula includes a [Real World Calculation] * MFF = HahSoThere we could live with that - even 'grin and bear it'. The MFF ( marketing fiddle factor ) would only be used by the marketdroids, and they alone would boast and compare the right hand side, whilst the designers would use the real world numbers in the multi term equation on the left hand side. Marketing would not have to go 'cold turkey' as their number would still be in the data sheet - just now it is clearly identified :) Or, will we see 'marketing MHz' and 'narketing ns' numbers next..... :( -jgArticle: 72143
Eirik Seljelid wrote: > mmock wrote: > >>> Eirik Seljelid wrote: >>> >>>> considered the PA7536, but I find it way easyer to get an older >>>> version of ABEL, compile the code for 82S100 and burn the chips. >>> >>> >> Eirik, >> >> Have you located it? I'm not familiar with the 82S100. I have an >> ancient version of ABEL, circa 1988. Is that too ancient? >> >> Mike > > > Not sure. I've found Abel 2.0 and Abel 4.0 on the net and tried to > compile the source, but in both versions I got the message "fatal error: > out of memory". It worked when I tried to compile only parts of the source. Some (most?) ABEL's needed keys, this may be a security artifact ? It is hard to believe the 82S100, which my info shows has just 1928 fuses (smaller than a 16V8), would tax memory ? CUPL probably also supported the 82S100. -jgArticle: 72144
"Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:cf8jpk$82o$1$8302bc10@news.demon.co.uk... > Peter Alfke wrote: > > This debate is getting long in the tooth. > > Just take the number of slices and divide by two. > > In the meantime, Altera has jumped on this bandwagon and they > > multiply their ALE numbers by 1.25. > > As long a there is Marketing, there will be "creativity" with numbers. > > Just grin and bear it! > > Peter Alfke > > Our stuff still has a way to go before it catches up with the > real smoke and mirror artists. Did the Citroen 2CV ever have > a two horsepower engine, even when first introduced - whenever > that was? Actually I don't understand that one... it's as if > X advertised "Virtex-4: more than one LUT" > > Anybody old enough to remember Radio Shack's spec on the stereo amps? 150 WATTS to us means out put power to speakers. From Radio Shacks spec it was input power on the AC side.Article: 72145
Does anyone know who won the camera from Altera on that Cyclone 2 web presentation?Article: 72146
> Given that 'marketing numbers' have caused, over time, at a minimum >annoyance or bemusement, and at a maximum (above) outright customer >flight, what about the idea that instead of excusing this silliness, it >actually gets fixed, and data sheets get provided with accurate formula >for available resource ? Would it do any good if several people wrote (paper) letters to the marketing dept? Mayve we could convince some of them to use real numbers and brag about having honest info. They could even make up a fancy name for it. :) or :( I think it terms of LUTs/FFs so an accurate table is what I'm looking for. Extra columns for RAM, multipliers, and such would be handy. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 72147
Hi, What are the differences between FPGA & CPLD? Thnaks!Article: 72148
similar to RAM and flash cards... Kelvin "terry" <leonlai2k@yahoo.com> wrote in message news:9904d48.0408091634.5c8d050d@posting.google.com... > Hi, > > What are the differences between FPGA & CPLD? > > Thnaks!Article: 72149
Eric, camera wise, you may look at the mindstorm Vision Command. It looks somewhat new on Lego website so I am wondering whether it is on sell already... kelvin "Eric DELAGE" <eric_delage@yahoo.fr> wrote in message news:41160BFA.8000702@yahoo.fr... > > In general, if you can do the problem in software, it's better > > to use a uP rather than a FPGA. The developement software > > is more user friendly. That makes it much faster to try a new > > idea. > > It depends how far you want to go w/ your robot. One of the LEGO > extension sets includes a Logitech USB Camera. Unfortunately, the camera > is connected to the PC via the USB cable (limiting the movemens of your > robot), then few pieces of information are sent back to the RCX for > robot control. > > We can't call really it an autonomous agent, can't we? It would be a > better idea to handle the camera directly from the robot itself. You > would need a processor to handle the USB protocol stack, but an FPGA > would be nice to compute in real-time the images that you capture in > order to improve the robot capability to react to what it sees. > > In such a case, the processor would indeed offer more flexibility but > wouldn't be able to compute the huge amount of data so effiently. > Therefore, an approach incl. a processor + an FPGA would be nice. > > Eric
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