Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Dear, I have a V2PRO design using PPC405 and several peripheral including plb_ddr. When i try to implement my top_level deign i got the following error during PAR : Phase 8.24 ERROR:Place:17 - The current designer locked placement of the IOBs IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a physical routing limitation. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be driven by the same signal or one of the signals will be unroutable. Before continuing with this design please unlock or move one of these IOBS to a new location. I can't move then i use a AVNET Dev board so schematic is fixed !! I use ISE / EDK 6.2 with latest Service Pack on Linux. I found a answer record on xilinx website (N° 18780) reporting this problem for ise 6.1 fixed with 6.1 SP3, and they say that il will be fixed in 6.2. But, it's still here !!! 2 questions : - Did anyone get this kind of problem with 6.2, and what the solution ? - It is a good idea to install ISE 6.1 SP3 on my PC ? Thanks for your suggestions GillesArticle: 72201
"Jerry" <nospam@nowhere.com> wrote in message news:10hip30b8p0f237@corp.supernews.com... > "Captain Bly" <Bobcrap@aol.com> wrote in message > news:yT3Sc.53161$zc4.22664573@news4.srv.hcvlny.cv.net... > > I got a tee shirt, I could only assume it's someone that works for Altera > > > > "Jerry" <nospam@nowhere.com> wrote in message > > news:10hg4i8oulqp5af@corp.supernews.com... > > > Does anyone know who won the camera from Altera on that Cyclone 2 web > > > presentation? > > WOW, you got the tee-shirt? I didn't even get to register to win the camera > after sitting through > an hour of rehashed info then listening to questions that were answered by > the marketerr. Yes I > did complain to Altera about it but it hasn't done me any good. The big > question is will this > incident affect my decision to go Altera or Xilinx on the next design? No it > won't. > So only one person on this newsgroup got a tee-shirt? I thought the first > 300 were going to > receive one. > > ARRRRRGGGGG oh wait.................... > If you are saying ARRRRRRGGGGG a lot lately you may be designing with > Altera. You know how it, if you give Altera $100K in orders then they will get you a tee shirt "after you win a contest" - actually who knows, maybe the other 299 tee-shirt wins don't subscribe to this group.Article: 72202
Hello, I'm using SelectMAP to access the xc2vp20 on a HW-AFX-1152 board. For the controller I'm using the PPC on the xc2vp7 on an ML300 board, the SelectMAP is connected to GPIO2 pins (using a custom OPB peripheral, not opb_gpio). I am using SelectMAP Slave Mode and controlled CCLK (less than 200 kHz). So far, I've got configuration and read_idcode working. However it just won't work when I try to read *anything* but the IDCODE register, whatever I try :( Read IDCODE works right as in the book, writing five words: FFFF_FFFF, AA99_5566, 2801_C001, 0000_0000, 0000_0000 and then reading the first four bytes after BUSY deasserts. It doesn't matter whether the device is configured (Persist:Yes) or not, it just works :) But when I try to read the STATUS register, for example, using 2800_E001 as the third command word, with everything else (including control signals and timing) completely the same, it doesn't work any more. It returns one byte of zeros, then goes into ABORT for just _two_ cycles (status 0xF1), then reverts to non-abort status (0xF9). The same goes for a number of other registers I tried so far (CTL, MASK, CRC, ..). I also tried reading back a single frame via FDRO, using the right commands (well, the same ones I am successfully using on the ICAP), but again no luck. Again, it doesn't matter whether the device is configured (with Persist) or not, read IDCODE works, everything else fails. Anybody got *any* idea what I might be doing wrong? regards, -g -- In crustulum beatitas.Article: 72203
All, Does anyone know of an automated way to convert an RPM with macro grid RLOCs to one using RPM grid RLOCs? As far as I can tell, the only way to convert right now is to manually replace the RLOCs in the Floorplanner-generated UCF with the RPM values found with FPGA Editor. My RPM is about 1K LUTS, so this approach is not feasible. Can FPGA Editor create a file that I can then parse with a Perl script? JohnArticle: 72204
gilles wrote: > Dear, > > I have a V2PRO design using PPC405 and several peripheral including > plb_ddr. When i try to implement my top_level deign i got the following > error during PAR : > > Phase 8.24 > ERROR:Place:17 - The current designer locked placement of the IOBs > IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a > physical routing limitation. This device has a shared routing resource > connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction > means that these pairs of pins must be driven by the same signal or one > of the signals will be unroutable. Before continuing with this design > please unlock or move one of these IOBS to a new location. > > > I can't move then i use a AVNET Dev board so schematic is fixed !! > > I use ISE / EDK 6.2 with latest Service Pack on Linux. > > I found a answer record on xilinx website (N° 18780) reporting this > problem for ise 6.1 fixed with 6.1 SP3, and they say that il will be > fixed in 6.2. > But, it's still here !!! Hello Gilles, The problem described in Answer 18780 is indeed fixed in version 6.2i but you still need to set the environment variable mentioned there. It's also possible that the problem you are seeing is unrelated to problem described in Answer 18780. The same errors can occur for other reasons. If you are seeing the 18780 problem, the IOB sites involved will be located next to DCMs. Check this in FPGA Editor for confirmation. If that is not the case, consider the possibility that the error messages are valid and that you have a design issue. If you do have a design issue, It may be possible to correct the problem by controlling the FF BEL usage (BEL = IFF1|IFF2|OFF1|OFF2) or by disabling a FF pack in the IOB (IOB = FALSE). If you are in fact needing to get more than two input or two output clocks into a single IOB pair then you are running into a hardware limitation with the routing resources (Answer 11747) and there is no solution. Regards, Bret Wade Xilinx Product Applications > > 2 questions : > - Did anyone get this kind of problem with 6.2, and what the solution ? > - It is a good idea to install ISE 6.1 SP3 on my PC ? > > Thanks for your suggestions > > GillesArticle: 72205
Hi.Can anyone help? I am completely new to FPGA's and wonder if any of the many PLD-type manufacturers provides software to take a schematic/logic digram and enter this in some way to compile the program for the chip, without having to start to learn VHDL or Verilog. The circuit to be made into a chip would consiste of say 12 decade counters similar to the CD4518, 5 7-segment decoder similar to CD4511 and a few bits of random 'glue'. TIA Alistair MacfarlaneArticle: 72206
On Mon, 09 Aug 2004 15:49:35 -0700, Sumit wrote: > Hi > > How much of a consideration is the quality of design tools while > choosing the FPGA vendor/device for a design? I guess this comes down > to - are most of the tools out there almost of similar quality in terms > of leading to designs with similar performance, area (FPGA usage), etc ? > I know a lot of folks are partial to Xilinx and Altera, but I am > trying to consider others as well, and want to know how carefully I have > to look at tool offerings to evaluate all of them. > > Thanks > Sumit Software tools are very important. The Xilinx tools give you more control then the Altera tools and they are much easier to script. If you do everything from the GUIs they are fairly similar but once you get proficient you'll want to start doing everything with scripts and constraint files, that's when Xilinx pulls ahead. With either toolset the important thing is learning what works and what doesn't. It's for this reason that once someone has become familiar with one or the other they tend to stick with that vendor for years. As for synthesis tools, Synplify is 10-15% better than the XST (the Xilinx synthesis tool). By better I mean the number of slices tends to be 10% fewer with Synplify and par has an easier time meeting timing. However XST has been improving at a pretty good rate, last year it didn't work at all now it does a very credible job.Article: 72207
Hi all, I'm cuurently working on a xilinx spartan 2e design for debug I'm using the chipscope pro LA. the problem is as follows: I'm using the chipscope pro for looking at the logic lines (bus) that define the "state" of the state machine in order to determine the present state of the machine at a given time. but the chipscope is giving me the binary (or oct, hex etc.) value of the bus. when I'm declaring the state machine in VHDL I'm giving each state a name (the synt' does the enumeration automatically) so I do not know what is the corresponding bus value for each state. I'm pretty sure that the Xilinx synthisizer generates this kind of data but I dont know where to find it and so is their FAE :) for example: if I declare a simple state machine with the follwoing states: type state_type is (idle , first , second , last) I would like to get a reference data such as: idle = 00 first = 01 second = 10 last = 11 that would be very helpfull when debugging large state machines with chipscope. So if anyone knows where to find it (if possible) I would realy appreciate it. thanks in advance, Moti.Article: 72208
"K4MON" <k4mon@aol.com> wrote in message news:20040811120212.11415.00002174@mb-m23.aol.com... > Hi.Can anyone help? > I am completely new to FPGA's and wonder if any of the many PLD-type > manufacturers provides software to take a schematic/logic digram and enter this > in some way to compile the program for the chip, without having to start to > learn VHDL or Verilog. The circuit to be made into a chip would consiste of say > 12 decade counters similar to the CD4518, 5 7-segment decoder similar to CD4511 > and a few bits of random 'glue'. The Altera Quartus software allows schematic entry. LeonArticle: 72209
gilles wrote: > Dear, > > I have a V2PRO design using PPC405 and several peripheral including > plb_ddr. When i try to implement my top_level deign i got the following > error during PAR : > > Phase 8.24 > ERROR:Place:17 - The current designer locked placement of the IOBs > IMM_MASK<0> and DIMM_STROBE<0> makes this design unroutable due to a > physical routing limitation. This device has a shared routing resource > connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction > means that these pairs of pins must be driven by the same signal or one > of the signals will be unroutable. Before continuing with this design > please unlock or move one of these IOBS to a new location. > > > I can't move then i use a AVNET Dev board so schematic is fixed !! > This is in my opinion a bug on the Avnet board. It turns out that the IOBs in the V2Pro have the clock "hardwired" in pairs, which you can easily see in fpga_editor. The pins for DIMM_MASK<0> and DIMM_STROBE<0> occupy one of these pairs (P22 and R22), as do most of the other mask and strobe signals, so they must use the same output clock. However, this really violates the required timing for these signals. My solution to this involved recognizing that in my application, the mask would never change during a burst. So I used the strobe clock for both outputs, and simply made sure that the mask signals were valid a half clock earlier, and remained valid throughout the burst. Another thing to be aware of. Hopefully you noticed that, because Xilinx chose to number all there std_logic_vectors as (0 to n)???? you need to relabel the address signal assignments in your UCF file. Otherwise, the commands to the DDR chips won't work. For example: # These need to be reversed from the schematic labeling, # because Xilinx made all their VHDL models (0 to n) NET "DDR_Addr<11>" LOC = "V25"; NET "DDR_Addr<10>" LOC = "U26"; NET "DDR_Addr<9>" LOC = "T28"; NET "DDR_Addr<8>" LOC = "T25"; NET "DDR_Addr<7>" LOC = "U27"; NET "DDR_Addr<6>" LOC = "T26"; NET "DDR_Addr<5>" LOC = "R27"; NET "DDR_Addr<4>" LOC = "R25"; NET "DDR_Addr<3>" LOC = "R28"; NET "DDR_Addr<2>" LOC = "P26"; NET "DDR_Addr<1>" LOC = "V26"; NET "DDR_Addr<0>" LOC = "M30"; #NET "DDR_Addr<12>" LOC = "P27"; -- My real email is akamail.com@dclark (or something like that).Article: 72210
David Kallberg wrote: > I tried to do it, but it didn't work. > David What did you try? The native version of Impact does work, but unless you are running the officially supported version of RH8, there are a few steps you need to follow. Mainly, you need to recompile the driver against the source for whatever kernel you are using. Not exactly trivial, but it does work. The instructions and source code are available from Xilinx: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18612 > > John Williams <jwilliams@itee.uq.edu.au> wrote in message news:<cf8u9c$4uo$1@bunyip.cc.uq.edu.au>... > >>... >>If you are using normal Xilinx ISE tools they can be installed native >>under Linux - Impact works fine. >> >>Regards, >> >>John -- My real email is akamail.com@dclark (or something like that).Article: 72211
Hello, Can people help me with finding out the issues associated with scheduling in run-time reconfiguration and in dynamic reconfiguration. all your suggestion are welcome thanks supradeepArticle: 72212
In article <car9vf$tp5$1@nobel.pacific.net.sg>, Rudolf Usselmann <russelmann@hotmail.com> wrote: >Stephen Williams wrote: > >> >> Does anybody know if the Xilinx Paralel cable IV cable can >> be made to work under Linux w/ ISE 6.1i.03? And to make it >> even more interesting, my Linux is AMD64, will the driver work >> at all on this system? >> >> >> .... and while we're on the subject, the Linux driver source is >> itself is pretty basic. Is there programming informatino for the >> cable that one can use to write custom software to drive the >> device. > > >Stephen, > >not sure if this will help: > >I have faced the same problem - not being able to program >Xilinx Devices using Xilinx Software and Xilinx hardware >under linux. So I wrote a small dumb program that can take >a bit stream and directly upload it to an FPGA. > >You can find it here: http://www.asics.ws/tools/ljp.c.gz > >This works with both Parallel Cable 3 and 4. > Has anyone tried this program with the $99 Xilinx eval board? PhilArticle: 72213
On 11 Aug 2004 10:32:54 -0700, supradeep@gmail.com (supradeep narayana) wrote: >Hello, >Can people help me with finding out the issues associated with >scheduling in run-time reconfiguration and in dynamic reconfiguration. > >all your suggestion are welcome > >thanks >supradeep Can you please give us the full text of your homework assignment, so that we can be more amused. Maybe also list what you have done so far, before posting your question.Article: 72214
You can download the free Webpack software from Xilinx website. This has ECS schematic entry software included. --Neeraj "K4MON" <k4mon@aol.com> wrote in message news:20040811120212.11415.00002174@mb-m23.aol.com... > Hi.Can anyone help? > I am completely new to FPGA's and wonder if any of the many PLD-type > manufacturers provides software to take a schematic/logic digram and enter this > in some way to compile the program for the chip, without having to start to > learn VHDL or Verilog. The circuit to be made into a chip would consiste of say > 12 decade counters similar to the CD4518, 5 7-segment decoder similar to CD4511 > and a few bits of random 'glue'. > TIA > Alistair MacfarlaneArticle: 72215
Sumit wrote: > > How much of a consideration is the quality of design tools while > choosing the FPGA vendor/device for a design? I guess this comes down > to - are most of the tools out there almost of similar quality in > terms of leading to designs with similar performance, area (FPGA > usage), etc ? I know a lot of folks are partial to Xilinx and > Altera, but I am trying to consider others as well, and want to know > how carefully I have to look at tool offerings to evaluate all of > them. It is great when you have sufficient time to have a look at all available tools. I started with Maxplus2 from Altera and after endless phonecalls over a period of 2 weeks to the support engineer at the Altera distributor I was able to get a trivial design going. I somehow felt never tempted to go though the same at another manufacturers tools. Meanwhile the tools may have evolved and are perhaps easier to use. Just in case you test them all, a feedback on how long a trivial design took would be welcome. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 72216
"buke2" <cubah@tlen.pl> wrote in message news:cfcqgv$e7$1@atlantis.news.tpi.pl... > I use Xilinx Foundation 2.1i build 3.1,162 > and I use HDL Editor build 0.42 > and if I want to create macro from file (Project->Create Macro) I must > specify FLEXim license? > What is this that license? > Anybody knows how solvethis problem? YES! 1) do not use sofware that belongs to museum! 2) download latest ISE WebPack (free) and just use the mouse and right click to create symbols from VHDL or Verilog. Antti http://xilinx.openchip.orgArticle: 72217
I was wondering if anybody knew of any 3D graphics libraries (written in VHDL or Verilog). I came across Manticore but it looks like the developers are going in a different direction. I also came across a couple of other small projects but they looked to be very implementation dependant (one time demo). I'm looking for something that supports triangles (or some other primitives) with materials and light sources (would be nice). Or am I wishing for too much? Thanks, Derek SimmonsArticle: 72218
Hi,
Follow up to a preceding post, I finally decided to use DDR : 2 chips of 16bits wide to have 32bits bus.
Since I got access to a ibis simulator thru a friend, I did a few simulation.
For the shared lines (like clk & address), I used :
Spartan3 DDR Chips
output Input
|\ _______ ________ |\
| >------O_______)------O________)-----| >-
|/ | |/
|
| |\
'-----------------| >-
|/
For the not shared lines ( like data ):
Spartan3 DDR Chips
output Input
|\ _______ |\
| >------O_______)-------| >-
|/ |/
The lines between the spartan3 and DDR are between 2 and 4 inch. I'm trying to get them as short as possible, I haven't done yet the layout and it's just a worst case estimate.
I simulated with a 100Mhz square wave, and (for my inexperienced eyes), it looked awful !
The square wave is FAR from anything close to square or monotonic, 1V undershoot and overshoot.
So I tried to add a series resistor at the output of spartan 3 output. 35 ohm seemed like a good value but it's more try & test than a real computed values ( track impedance is 70 ohm, at least that's what the simulation tool tells me ).
Also, I used the LVCMOS_25 standard, with Slow and Fast and multiple drive strenght. The Fast 16ma seems the best.
But that's for Spartan -> DDR. For bidir lines, should I put R or R/2 series resistor at each end ?
If I decide to use the DCI of Spartan 3 for series termination, the resistor is placed at the output of the output buffer but not at the input of the input buffer, so I suppose it's even better.
I haven't simulated the DDR -> Spartan 3 direction because my tool don't seen to recognize the output driver description in Micron's IBIS models, I still have to investigate this.
I'm not sure of my simulations but they look good. Do the results sounds ok ? Any advice ?
Thanks for any clue or insight you may have. Making such a board is not quite cheap and I can't afford to have to redesign it multiples times, I'd like the first one to work ;)
Sylvain
Article: 72219Also see: http://www.ee.ucla.edu/~dongu/pub/papers/fccm03_dul98.pdf Pierre Wadier <peewee@melix.net> wrote in message news:<4106c89b$0$15280$636a15ce@news.free.fr>... > There are at least two methods : > > 1) generate normaly distributed samples (quantized box-muller algorithm), > add a few of them (4 may be enough), according to the central limit > theorem, it increases the generator's precision > > here is an interesting paper > http://lester.univ-ubs.fr:8080/~boutillon/articles/ICECS_00_Emul.pdf > > > 2) set the quantization of the noise you wish to produce, generate tables > storing values of the integrated density of probability (by software). > To generate a noise sample, generate uniformly distributed samples, search > in the tables for the nearest element and return this element's index. The > indexes returned should be normaly distributed. This is sometimes called the > thresholds method. > > I may not be very clear but it works perfectly (I've tried it) > > PierreArticle: 72220
http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&rd=1&item=3833171100 there is 2M Gate FPGA board for sale 0.99$ starting price no reserve. the board can be seen directly there http://xilinx.openchip.org/proto/ I am just trying to sell off what I can (and what I do not need myself). Antti PS I have been sitting in N.Y. on 2Ave at night selling old razors to buy bananas in the morning - my current situtation is'nt as bad yet, but with 3 kids in foreign country living from unemployment money is'nt fun either. I hope the community does'nt mind this posting, just in case an extra smile for all :)Article: 72221
I'd suggest looking at the results with the series resistor at the S3 driver before the transmission line for a baseline and then moved to the end of the transmission line before the split for a comparison. You may see very little difference, suggesting the location of the resistor isn't critical; but then you might see it is. In motherboards, the series resistors are often at the edge of the DDR connector, not as close to the driver as possible. Having a series resistor at your input shouldn't affect your timing much (such as for bidir lines); at that point the only delay seen is the RC for the series resistor and the input parasitics. For example, 35 ohm and 8 pF gives a 280 ps time constant which is small for the overall timing budget in the slower DDR implementation. The biggest suggestion I have is to keep the DDR-side stubs to a minimum, reducing the problems introduced by the impedance mismatch. "Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:411a7baf$0$285$ba620e4c@news.skynet.be... > Hi, > > Follow up to a preceding post, I finally decided to use DDR : 2 chips of 16bits wide to have 32bits bus. > > Since I got access to a ibis simulator thru a friend, I did a few simulation. > > > For the shared lines (like clk & address), I used : > > Spartan3 DDR Chips > output Input > |\ _______ ________ |\ > | >------O_______)------O________)-----| >- > |/ | |/ > | > | |\ > '-----------------| >- > |/ > > > For the not shared lines ( like data ): > > Spartan3 DDR Chips > output Input > |\ _______ |\ > | >------O_______)-------| >- > |/ |/ > > > > The lines between the spartan3 and DDR are between 2 and 4 inch. I'm trying to get them as short as possible, I haven't done yet the layout and it's just a worst case estimate. > > I simulated with a 100Mhz square wave, and (for my inexperienced eyes), it looked awful ! > The square wave is FAR from anything close to square or monotonic, 1V undershoot and overshoot. > > So I tried to add a series resistor at the output of spartan 3 output. 35 ohm seemed like a good value but it's more try & test than a real computed values ( track impedance is 70 ohm, at least that's what the simulation tool tells me ). > > Also, I used the LVCMOS_25 standard, with Slow and Fast and multiple drive strenght. The Fast 16ma seems the best. > > But that's for Spartan -> DDR. For bidir lines, should I put R or R/2 series resistor at each end ? > If I decide to use the DCI of Spartan 3 for series termination, the resistor is placed at the output of the output buffer but not at the input of the input buffer, so I suppose it's even better. > > I haven't simulated the DDR -> Spartan 3 direction because my tool don't seen to recognize the output driver description in Micron's IBIS models, I still have to investigate this. > > > I'm not sure of my simulations but they look good. Do the results sounds ok ? Any advice ? > > Thanks for any clue or insight you may have. Making such a board is not quite cheap and I can't afford to have to redesign it multiples times, I'd like the first one to work ;) > > > > SylvainArticle: 72222
Just in case you haven't already seen it, I would recommend taking a look at the Spartan-3 133 MHz DDR SDRAM reference design that supports up to DDR266 (PC2100) . Much of the engineering effort is already done. The application note and reference design is on the Xilinx Memory Corner. http://www.xilinx.com/memory http://www.xilinx.com/products/design_resources/mem_corner/resource/xaw_dram_ddr.htm You'll want "XAPP768c: 133 MHz DDR Interface for Spartan-3 HDL Code". The application note and reference design are available to registered Xilinx web site viewers (which is a PITA, but unfortunately, that's the policy). Another recommendation is to take a look at the following overview application note. This one is available without registering. XAPP802: Memory Interface Application Notes Overview http://www.xilinx.com/bvdocs/appnotes/xapp802.pdf Also, depending on the specific memory device you are using, you probably want to use one of the SSTL I/O standards. Likewise, some of the Micron devices, and probably others, have SSTL_2, Class II output buffers and offer a reduced drive strength option for low load or point-to-point designs. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Sylvain Munaut" <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:411a7baf$0$285$ba620e4c@news.skynet.be... > Hi, > > Follow up to a preceding post, I finally decided to use DDR : 2 chips of 16bits wide to have 32bits bus. > > Since I got access to a ibis simulator thru a friend, I did a few simulation. > > > For the shared lines (like clk & address), I used : > > Spartan3 DDR Chips > output Input > |\ _______ ________ |\ > | >------O_______)------O________)-----| >- > |/ | |/ > | > | |\ > '-----------------| >- > |/ > > > For the not shared lines ( like data ): > > Spartan3 DDR Chips > output Input > |\ _______ |\ > | >------O_______)-------| >- > |/ |/ > > > > The lines between the spartan3 and DDR are between 2 and 4 inch. I'm trying to get them as short as possible, I haven't done yet the layout and it's just a worst case estimate. > > I simulated with a 100Mhz square wave, and (for my inexperienced eyes), it looked awful ! > The square wave is FAR from anything close to square or monotonic, 1V undershoot and overshoot. > > So I tried to add a series resistor at the output of spartan 3 output. 35 ohm seemed like a good value but it's more try & test than a real computed values ( track impedance is 70 ohm, at least that's what the simulation tool tells me ). > > Also, I used the LVCMOS_25 standard, with Slow and Fast and multiple drive strenght. The Fast 16ma seems the best. > > But that's for Spartan -> DDR. For bidir lines, should I put R or R/2 series resistor at each end ? > If I decide to use the DCI of Spartan 3 for series termination, the resistor is placed at the output of the output buffer but not at the input of the input buffer, so I suppose it's even better. > > I haven't simulated the DDR -> Spartan 3 direction because my tool don't seen to recognize the output driver description in Micron's IBIS models, I still have to investigate this. > > > I'm not sure of my simulations but they look good. Do the results sounds ok ? Any advice ? > > Thanks for any clue or insight you may have. Making such a board is not quite cheap and I can't afford to have to redesign it multiples times, I'd like the first one to work ;) > > > > SylvainArticle: 72223
hello ng, there are new versions of the 9500xl cpld devices on the xilinx server. See: http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-18744&iLanguageID=1 My distri told me, these products are not recommended for new designs, but they still are PRELIMINARY !?? The question about the write inhibit bit is also curious. In ds054 http://direct.xilinx.com/bvdocs/publications/ds054.pdf on page 14 table 3 shows a state, where the cpld cannot be reprogrammed nor erased. Answer database no 4288 states the opposite: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=4288 Maybe some stimulations for the next datasheet revisions... MIKEArticle: 72224
Phil Tomson wrote:
>>You can find it here: http://www.asics.ws/tools/ljp.c.gz
>>
>>This works with both Parallel Cable 3 and 4.
> Has anyone tried this program with the $99 Xilinx eval board?
>
Hello,
I am trying it on the Spartan-3 board of NuHorizon.
This board has, next to the spartan-3chip, a configuration device in the Jtag-chain
so you have to put that one in BYPASS mode, with an 8-bit command.
The ljp.c program doesn't work, firstly because it is for Virtex that have
5 bit jtag-commands, while the spartan-3 has 6 bit commands, as described in
the BSDL-file.
But alas after changing this, the ID-codes can be read properly, and bypass does also
work. But programming doesnt:(. Both chip's are revision 0 by the way.
The spartan-3 datasheet (part 3: page 38, figure 24) describes some details of how to
program it. But that doesnt help me any further.
As an aside, I make the bitfile with the option "-g StartUpClk:JtagClk" as is mentioned
by the Impact program and in the documentation.
The question is, does the spartan-3 specify the programming in it's datasheet, or is
there some vital part of the specifation missing from the datasheet.
The ljp program follows this, and I tried a lot of variants, also looking in xapp139.pdf about
virtex programming.
If the datasheet is telling the full story it should be fairly trivial to make it work, so I
am afraid I'm missing something, but what?
cheers,
Sietse Achterop
PS. I also tried my luck with the "mitoujtag" program, but I can't get the giveio.sys to function
under wine. Does anyone know how to do this?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z